Documentation/arch/loongarch/irq-chip-model.rst

   1 .. SPDX-License-Identifier: GPL-2.0
   2
   3 =======================================
   4 IRQ chip model (hierarchy) of LoongArch
   5 =======================================
   6
   7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
   8 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
   9 Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
  10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
  11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
  12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
  13
  14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
  15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
  16 in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
  17 and there are two models of hierarchy (legacy model and extended model).
  18
  19 Legacy IRQ model
  20 ================
  21
  22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
  23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
  24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
  25 to LIOINTC, and then CPUINTC::
  26
  27      +-----+     +---------+     +-------+
  28      | IPI | --> | CPUINTC | <-- | Timer |
  29      +-----+     +---------+     +-------+
  30                       ^
  31                       |
  32                  +---------+     +-------+
  33                  | LIOINTC | <-- | UARTs |
  34                  +---------+     +-------+
  35                       ^
  36                       |
  37                 +-----------+
  38                 | HTVECINTC |
  39                 +-----------+
  40                  ^         ^
  41                  |         |
  42            +---------+ +---------+
  43            | PCH-PIC | | PCH-MSI |
  44            +---------+ +---------+
  45              ^     ^           ^
  46              |     |           |
  47      +---------+ +---------+ +---------+
  48      | PCH-LPC | | Devices | | Devices |
  49      +---------+ +---------+ +---------+
  50           ^
  51           |
  52      +---------+
  53      | Devices |
  54      +---------+
  55
  56 Extended IRQ model
  57 ==================
  58
  59 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
  60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
  61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
  62 to CPUINTC directly::
  63
  64           +-----+     +---------+     +-------+
  65           | IPI | --> | CPUINTC | <-- | Timer |
  66           +-----+     +---------+     +-------+
  67                        ^       ^
  68                        |       |
  69                 +---------+ +---------+     +-------+
  70                 | EIOINTC | | LIOINTC | <-- | UARTs |
  71                 +---------+ +---------+     +-------+
  72                  ^       ^
  73                  |       |
  74           +---------+ +---------+
  75           | PCH-PIC | | PCH-MSI |
  76           +---------+ +---------+
  77             ^     ^           ^
  78             |     |           |
  79     +---------+ +---------+ +---------+
  80     | PCH-LPC | | Devices | | Devices |
  81     +---------+ +---------+ +---------+
  82          ^
  83          |
  84     +---------+
  85     | Devices |
  86     +---------+
  87
  88 Virtual Extended IRQ model
  89 ==========================
  90
  91 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt
  92 go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
  93 devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
  94 Extended I/O Interrupt Controller), and then go to CPUINTC directly::
  95
  96        +-----+    +-------------------+     +-------+
  97        | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
  98        +-----+    +-------------------+     +-------+
  99                             ^
 100                             |
 101                       +-----------+
 102                       | V-EIOINTC |
 103                       +-----------+
 104                        ^         ^
 105                        |         |
 106                 +---------+ +---------+
 107                 | PCH-PIC | | PCH-MSI |
 108                 +---------+ +---------+
 109                   ^      ^          ^
 110                   |      |          |
 111            +--------+ +---------+ +---------+
 112            | UARTs  | | Devices | | Devices |
 113            +--------+ +---------+ +---------+
 114
 115
 116 Description
 117 -----------
 118 V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
 119 EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
 120 be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
 121 interrupts can be routed to up to 256 virtual cpus.
 122
 123 With standard EIOINTC, interrupt routing setting includes two parts: eight
 124 bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection.
 125 For CPU selection there is four bits for EIOINTC node selection, four bits
 126 for EIOINTC CPU selection. Bitmap method is used for CPU selection and
 127 CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in
 128 one EIOINTC node.
 129
 130 With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
 131 there are two newly added registers with V-EIOINTC.
 132
 133 EXTIOI_VIRT_FEATURES
 134 --------------------
 135 This register is read-only register, which indicates supported features with
 136 V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.
 137
 138 Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
 139 indicates that CPU Interrupt Pin selection can be normal method rather than
 140 bitmap method, so interrupt can be routed to IP0 - IP15.
 141
 142 Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
 143 indicates that CPU selection can be normal method rather than bitmap method,
 144 so interrupt can be routed to CPU0 - CPU255.
 145
 146 EXTIOI_VIRT_CONFIG
 147 ------------------
 148 This register is read-write register, for compatibility intterupt routed uses
 149 the default method which is the same with standard EIOINTC. If the bit is set
 150 with 1, it indicated HW to use normal method rather than bitmap method.
 151
 152 Advanced Extended IRQ model
 153 ===========================
 154
 155 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
 156 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
 157 to AVECINTC, and then go to CPUINTC directly, while all other devices interrupts
 158 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
 159
 160  +-----+     +-----------------------+     +-------+
 161  | IPI | --> |        CPUINTC        | <-- | Timer |
 162  +-----+     +-----------------------+     +-------+
 163               ^          ^          ^
 164               |          |          |
 165        +---------+ +----------+ +---------+     +-------+
 166        | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
 167        +---------+ +----------+ +---------+     +-------+
 168             ^            ^
 169             |            |
 170        +---------+  +---------+
 171        | PCH-PIC |  | PCH-MSI |
 172        +---------+  +---------+
 173          ^     ^           ^
 174          |     |           |
 175  +---------+ +---------+ +---------+
 176  | Devices | | PCH-LPC | | Devices |
 177  +---------+ +---------+ +---------+
 178                   ^
 179                   |
 180              +---------+
 181              | Devices |
 182              +---------+
 183
 184 ACPI-related definitions
 185 ========================
 186
 187 CPUINTC::
 188
 189   ACPI_MADT_TYPE_CORE_PIC;
 190   struct acpi_madt_core_pic;
 191   enum acpi_madt_core_pic_version;
 192
 193 LIOINTC::
 194
 195   ACPI_MADT_TYPE_LIO_PIC;
 196   struct acpi_madt_lio_pic;
 197   enum acpi_madt_lio_pic_version;
 198
 199 EIOINTC::
 200
 201   ACPI_MADT_TYPE_EIO_PIC;
 202   struct acpi_madt_eio_pic;
 203   enum acpi_madt_eio_pic_version;
 204
 205 HTVECINTC::
 206
 207   ACPI_MADT_TYPE_HT_PIC;
 208   struct acpi_madt_ht_pic;
 209   enum acpi_madt_ht_pic_version;
 210
 211 PCH-PIC::
 212
 213   ACPI_MADT_TYPE_BIO_PIC;
 214   struct acpi_madt_bio_pic;
 215   enum acpi_madt_bio_pic_version;
 216
 217 PCH-MSI::
 218
 219   ACPI_MADT_TYPE_MSI_PIC;
 220   struct acpi_madt_msi_pic;
 221   enum acpi_madt_msi_pic_version;
 222
 223 PCH-LPC::
 224
 225   ACPI_MADT_TYPE_LPC_PIC;
 226   struct acpi_madt_lpc_pic;
 227   enum acpi_madt_lpc_pic_version;
 228
 229 References
 230 ==========
 231
 232 Documentation of Loongson-3A5000:
 233
 234   https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)
 235
 236   https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)
 237
 238 Documentation of Loongson's LS7A chipset:
 239
 240   https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)
 241
 242   https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
 243
 244 .. Note::
 245     - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
 246       in Section 7.4 of "LoongArch Reference Manual, Vol 1";
 247     - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
 248       "Loongson 3A5000 Processor Reference Manual";
 249     - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
 250       "Loongson 3A5000 Processor Reference Manual";
 251     - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
 252       "Loongson 3A5000 Processor Reference Manual";
 253     - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
 254       "Loongson 7A1000 Bridge User Manual";
 255     - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
 256       "Loongson 7A1000 Bridge User Manual".