Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / Documentation / sound / hd-audio / intel-multi-link.rst
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1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 .. include:: <isonum.txt>
4 ================================================
5 HDAudio multi-link extensions on Intel platforms
6 ================================================
8 :Copyright: |copy| 2023 Intel Corporation
10 This file documents the 'multi-link structure' introduced in 2015 with
11 the Skylake processor and recently extended in newer Intel platforms
13 HDaudio existing link mapping (2015 addition in SkyLake)
14 ========================================================
16 External HDAudio codecs are handled with link #0, while iDISP codec
17 for HDMI/DisplayPort is handled with link #1.
19 The only change to the 2015 definitions is the declaration of the
20 LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a
21 backwards-compatible change.
23 LCTL.SPA and LCTL.CPA are automatically set when exiting reset. They
24 are only used in existing drivers when the SCF value needs to be
25 corrected.
27 Basic structure for HDaudio codecs
28 ----------------------------------
32   +-----------+
33   | ML cap #0 |
34   +-----------+
35   | ML cap #1 |---+
36   +-----------+   |
37                   |
38                   +--> 0x0 +---------------+ LCAP
39                            | ALT=0         |
40                            +---------------+
41                            | S192          |
42                            +---------------+
43                            | S96           |
44                            +---------------+
45                            | S48           |
46                            +---------------+
47                            | S24           |
48                            +---------------+
49                            | S12           |
50                            +---------------+
51                            | S6            |
52                            +---------------+
54                        0x4 +---------------+ LCTL
55                            | INTSTS        |
56                            +---------------+
57                            | CPA           |
58                            +---------------+
59                            | SPA           |
60                            +---------------+
61                            | SCF           |
62                            +---------------+
64                        0x8 +---------------+ LOSIDV
65                            | L1OSIVD15     |
66                            +---------------+
67                            | L1OSIDV..     |
68                            +---------------+
69                            | L1OSIDV1      |
70                            +---------------+
72                        0xC +---------------+ LSDIID
73                            | SDIID14       |
74                            +---------------+
75                            | SDIID...      |
76                            +---------------+
77                            | SDIID0        |
78                            +---------------+
80 SoundWire HDaudio extended link mapping
81 =======================================
83 A SoundWire extended link is identified when LCAP.ALT=1 and
84 LEPTR.ID=0.
86 DMA control uses the existing LOSIDV register.
88 Changes include additional descriptions for enumeration that were not
89 present in earlier generations.
91 - multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
92 - number of sublinks (manager IP) in LCAP.LSCOUNT
93 - power management moved from SHIM to LCTL.SPA bits
94 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
95 - mapping of SoundWire codecs to SDI ID bits
96 - move of SHIM and Cadence registers to different offsets, with no
97   change in functionality. The LEPTR.PTR value is an offset from the
98   ML address, with a default value of 0x30000.
100 Extended structure for SoundWire (assuming 4 Manager IP)
101 --------------------------------------------------------
105   +-----------+
106   | ML cap #0 |
107   +-----------+
108   | ML cap #1 |
109   +-----------+
110   | ML cap #2 |---+
111   +-----------+   |
112                   |
113                   +--> 0x0 +---------------+ LCAP
114                            | ALT=1         |
115                            +---------------+
116                            | INTC          |
117                            +---------------+
118                            | OFLS          |
119                            +---------------+
120                            | LSS           |
121                            +---------------+
122                            | SLCOUNT=4     |-----------+
123                            +---------------+           |
124                                                        |
125                        0x4 +---------------+ LCTL      |
126                            | INTSTS        |           |
127                            +---------------+           |
128                            | CPA (x bits)  |           |
129                            +---------------+           |
130                            | SPA (x bits)  |           |
131                            +---------------+         for each sublink x
132                            | INTEN         |           |
133                            +---------------+           |
134                            | OFLEN         |           |
135                            +---------------+           |
136                                                        |
137                        0x8 +---------------+ LOSIDV    |
138                            | L1OSIVD15     |           |
139                            +---------------+           |
140                            | L1OSIDV..     |           |
141                            +---------------+           |
142                            | L1OSIDV1      |       +---+----------------------------------------------------------+
143                            +---------------+       |                                                              |
144                                                    v                                                              |
145              0xC + 0x2 * x +---------------+ LSDIIDx    +---> 0x30000  +-----------------+  0x00030000            |
146                            | SDIID14       |            |              | SoundWire SHIM  |                        |
147                            +---------------+            |              | generic         |                        |
148                            | SDIID...      |            |              +-----------------+  0x00030100            |
149                            +---------------+            |              | SoundWire IP    |                        |
150                            | SDIID0        |            |              +-----------------+  0x00036000            |
151                            +---------------+            |              | SoundWire SHIM  |                        |
152                                                         |              | vendor-specific |                        |
153                       0x1C +---------------+ LSYNC      |              +-----------------+                        |
154                            | CMDSYNC       |            |                                                         v
155                            +---------------+            |              +-----------------+  0x00030000 + 0x8000 * x
156                            | SYNCGO        |            |              | SoundWire SHIM  |
157                            +---------------+            |              | generic         |
158                            | SYNCPU        |            |              +-----------------+  0x00030100 + 0x8000 * x
159                            +---------------+            |              | SoundWire IP    |
160                            | SYNPRD        |            |              +-----------------+  0x00036000 + 0x8000 * x
161                            +---------------+            |              | SoundWire SHIM  |
162                                                         |              | vendor-specific |
163                       0x20 +---------------+ LEPTR      |              +-----------------+
164                            | ID = 0        |            |
165                            +---------------+            |
166                            | VER           |            |
167                            +---------------+            |
168                            | PTR           |------------+
169                            +---------------+
172 DMIC HDaudio extended link mapping
173 ==================================
175 A DMIC extended link is identified when LCAP.ALT=1 and
176 LEPTR.ID=0xC1 are set.
178 DMA control uses the existing LOSIDV register
180 Changes include additional descriptions for enumeration that were not
181 present in earlier generations.
183 - multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
184 - power management with LCTL.SPA bits
185 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
187 - move of DMIC registers to different offsets, with no change in
188   functionality. The LEPTR.PTR value is an offset from the ML
189   address, with a default value of 0x10000.
191 Extended structure for DMIC
192 ---------------------------
196   +-----------+
197   | ML cap #0 |
198   +-----------+
199   | ML cap #1 |
200   +-----------+
201   | ML cap #2 |---+
202   +-----------+   |
203                   |
204                   +--> 0x0 +---------------+ LCAP
205                            | ALT=1         |
206                            +---------------+
207                            | INTC          |
208                            +---------------+
209                            | OFLS          |
210                            +---------------+
211                            | SLCOUNT=1     |
212                            +---------------+
214                        0x4 +---------------+ LCTL
215                            | INTSTS        |
216                            +---------------+
217                            | CPA           |
218                            +---------------+
219                            | SPA           |
220                            +---------------+
221                            | INTEN         |
222                            +---------------+
223                            | OFLEN         |
224                            +---------------+           +---> 0x10000  +-----------------+  0x00010000
225                                                        |              | DMIC SHIM       |
226                        0x8 +---------------+ LOSIDV    |              | generic         |
227                            | L1OSIVD15     |           |              +-----------------+  0x00010100
228                            +---------------+           |              | DMIC IP         |
229                            | L1OSIDV..     |           |              +-----------------+  0x00016000
230                            +---------------+           |              | DMIC SHIM       |
231                            | L1OSIDV1      |           |              | vendor-specific |
232                            +---------------+           |              +-----------------+
233                                                        |
234                       0x20 +---------------+ LEPTR     |
235                            | ID = 0xC1     |           |
236                            +---------------+           |
237                            | VER           |           |
238                            +---------------+           |
239                            | PTR           |-----------+
240                            +---------------+
243 SSP HDaudio extended link mapping
244 =================================
246 A DMIC extended link is identified when LCAP.ALT=1 and
247 LEPTR.ID=0xC0 are set.
249 DMA control uses the existing LOSIDV register
251 Changes include additional descriptions for enumeration and control that were not
252 present in earlier generations:
253 - number of sublinks (SSP IP instances) in LCAP.LSCOUNT
254 - power management moved from SHIM to LCTL.SPA bits
255 - hand-over to the DSP for access to multi-link registers, SHIM/IP
256 with LCTL.OFLEN
257 - move of SHIM and SSP IP registers to different offsets, with no
258 change in functionality.  The LEPTR.PTR value is an offset from the ML
259 address, with a default value of 0x28000.
261 Extended structure for SSP (assuming 3 instances of the IP)
262 -----------------------------------------------------------
266   +-----------+
267   | ML cap #0 |
268   +-----------+
269   | ML cap #1 |
270   +-----------+
271   | ML cap #2 |---+
272   +-----------+   |
273                   |
274                   +--> 0x0 +---------------+ LCAP
275                            | ALT=1         |
276                            +---------------+
277                            | INTC          |
278                            +---------------+
279                            | OFLS          |
280                            +---------------+
281                            | SLCOUNT=3     |-------------------------for each sublink x -------------------------+
282                            +---------------+                                                                     |
283                                                                                                                  |
284                        0x4 +---------------+ LCTL                                                                |
285                            | INTSTS        |                                                                     |
286                            +---------------+                                                                     |
287                            | CPA (x bits)  |                                                                     |
288                            +---------------+                                                                     |
289                            | SPA (x bits)  |                                                                     |
290                            +---------------+                                                                     |
291                            | INTEN         |                                                                     |
292                            +---------------+                                                                     |
293                            | OFLEN         |                                                                     |
294                            +---------------+           +---> 0x28000  +-----------------+  0x00028000            |
295                                                        |              | SSP SHIM        |                        |
296                        0x8 +---------------+ LOSIDV    |              | generic         |                        |
297                            | L1OSIVD15     |           |              +-----------------+  0x00028100            |
298                            +---------------+           |              | SSP IP          |                        |
299                            | L1OSIDV..     |           |              +-----------------+  0x00028C00            |
300                            +---------------+           |              | SSP SHIM        |                        |
301                            | L1OSIDV1      |           |              | vendor-specific |                        |
302                            +---------------+           |              +-----------------+                        |
303                                                        |                                                         v
304                       0x20 +---------------+ LEPTR     |              +-----------------+  0x00028000 + 0x1000 * x
305                            | ID = 0xC0     |           |              | SSP SHIM        |
306                            +---------------+           |              | generic         |
307                            | VER           |           |              +-----------------+  0x00028100 + 0x1000 * x
308                            +---------------+           |              | SSP IP          |
309                            | PTR           |-----------+              +-----------------+  0x00028C00 + 0x1000 * x
310                            +---------------+                          | SSP SHIM        |
311                                                                       | vendor-specific |
312                                                                       +-----------------+