arch/arc/include/asm/arcregs.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4  */
   5
   6 #ifndef _ASM_ARC_ARCREGS_H
   7 #define _ASM_ARC_ARCREGS_H
   8
   9 /* Build Configuration Registers */
  10 #define ARC_REG_AUX_DCCM        0x18    /* DCCM Base Addr ARCv2 */
  11 #define ARC_REG_ERP_CTRL        0x3F    /* ARCv2 Error protection control */
  12 #define ARC_REG_DCCM_BASE_BUILD 0x61    /* DCCM Base Addr ARCompact */
  13 #define ARC_REG_CRC_BCR         0x62
  14 #define ARC_REG_VECBASE_BCR     0x68
  15 #define ARC_REG_PERIBASE_BCR    0x69
  16 #define ARC_REG_FP_BCR          0x6B    /* ARCompact: Single-Precision FPU */
  17 #define ARC_REG_DPFP_BCR        0x6C    /* ARCompact: Dbl Precision FPU */
  18 #define ARC_REG_ERP_BUILD       0xc7    /* ARCv2 Error protection Build: ECC/Parity */
  19 #define ARC_REG_FP_V2_BCR       0xc8    /* ARCv2 FPU */
  20 #define ARC_REG_SLC_BCR         0xce
  21 #define ARC_REG_DCCM_BUILD      0x74    /* DCCM size (common) */
  22 #define ARC_REG_AP_BCR          0x76
  23 #define ARC_REG_ICCM_BUILD      0x78    /* ICCM size (common) */
  24 #define ARC_REG_XY_MEM_BCR      0x79
  25 #define ARC_REG_MAC_BCR         0x7a
  26 #define ARC_REG_MPY_BCR         0x7b
  27 #define ARC_REG_SWAP_BCR        0x7c
  28 #define ARC_REG_NORM_BCR        0x7d
  29 #define ARC_REG_MIXMAX_BCR      0x7e
  30 #define ARC_REG_BARREL_BCR      0x7f
  31 #define ARC_REG_D_UNCACH_BCR    0x6A
  32 #define ARC_REG_BPU_BCR         0xc0
  33 #define ARC_REG_ISA_CFG_BCR     0xc1
  34 #define ARC_REG_LPB_BUILD       0xE9    /* ARCv2 Loop Buffer Build */
  35 #define ARC_REG_RTT_BCR         0xF2
  36 #define ARC_REG_IRQ_BCR         0xF3
  37 #define ARC_REG_MICRO_ARCH_BCR  0xF9    /* ARCv2 Product revision */
  38 #define ARC_REG_SMART_BCR       0xFF
  39 #define ARC_REG_CLUSTER_BCR     0xcf
  40 #define ARC_REG_AUX_ICCM        0x208   /* ICCM Base Addr (ARCv2) */
  41 #define ARC_REG_LPB_CTRL        0x488   /* ARCv2 Loop Buffer control */
  42 #define ARC_REG_FPU_CTRL        0x300
  43 #define ARC_REG_FPU_STATUS      0x301
  44
  45 /* Common for ARCompact and ARCv2 status register */
  46 #define ARC_REG_STATUS32        0x0A
  47
  48 /* status32 Bits Positions */
  49 #define STATUS_AE_BIT           5       /* Exception active */
  50 #define STATUS_DE_BIT           6       /* PC is in delay slot */
  51 #define STATUS_U_BIT            7       /* User/Kernel mode */
  52 #define STATUS_Z_BIT            11
  53 #define STATUS_L_BIT            12      /* Loop inhibit */
  54
  55 /* These masks correspond to the status word(STATUS_32) bits */
  56 #define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
  57 #define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
  58 #define STATUS_U_MASK           (1<<STATUS_U_BIT)
  59 #define STATUS_Z_MASK           (1<<STATUS_Z_BIT)
  60 #define STATUS_L_MASK           (1<<STATUS_L_BIT)
  61
  62 /*
  63  * ECR: Exception Cause Reg bits-n-pieces
  64  * [23:16] = Exception Vector
  65  * [15: 8] = Exception Cause Code
  66  * [ 7: 0] = Exception Parameters (for certain types only)
  67  */
  68 #ifdef CONFIG_ISA_ARCOMPACT
  69 #define ECR_V_MEM_ERR                   0x01
  70 #define ECR_V_INSN_ERR                  0x02
  71 #define ECR_V_MACH_CHK                  0x20
  72 #define ECR_V_ITLB_MISS                 0x21
  73 #define ECR_V_DTLB_MISS                 0x22
  74 #define ECR_V_PROTV                     0x23
  75 #define ECR_V_TRAP                      0x25
  76 #else
  77 #define ECR_V_MEM_ERR                   0x01
  78 #define ECR_V_INSN_ERR                  0x02
  79 #define ECR_V_MACH_CHK                  0x03
  80 #define ECR_V_ITLB_MISS                 0x04
  81 #define ECR_V_DTLB_MISS                 0x05
  82 #define ECR_V_PROTV                     0x06
  83 #define ECR_V_TRAP                      0x09
  84 #define ECR_V_MISALIGN                  0x0d
  85 #endif
  86
  87 /* DTLB Miss and Protection Violation Cause Codes */
  88
  89 #define ECR_C_PROTV_INST_FETCH          0x00
  90 #define ECR_C_PROTV_LOAD                0x01
  91 #define ECR_C_PROTV_STORE               0x02
  92 #define ECR_C_PROTV_XCHG                0x03
  93 #define ECR_C_PROTV_MISALIG_DATA        0x04
  94
  95 #define ECR_C_BIT_PROTV_MISALIG_DATA    10
  96
  97 /* Machine Check Cause Code Values */
  98 #define ECR_C_MCHK_DUP_TLB              0x01
  99
 100 /* DTLB Miss Exception Cause Code Values */
 101 #define ECR_C_BIT_DTLB_LD_MISS          8
 102 #define ECR_C_BIT_DTLB_ST_MISS          9
 103
 104 /* Auxiliary registers */
 105 #define AUX_IDENTITY            4
 106 #define AUX_EXEC_CTRL           8
 107 #define AUX_INTR_VEC_BASE       0x25
 108 #define AUX_VOL                 0x5e
 109
 110 /*
 111  * Floating Pt Registers
 112  * Status regs are read-only (build-time) so need not be saved/restored
 113  */
 114 #define ARC_AUX_FP_STAT         0x300
 115 #define ARC_AUX_DPFP_1L         0x301
 116 #define ARC_AUX_DPFP_1H         0x302
 117 #define ARC_AUX_DPFP_2L         0x303
 118 #define ARC_AUX_DPFP_2H         0x304
 119 #define ARC_AUX_DPFP_STAT       0x305
 120
 121 /*
 122  * DSP-related registers
 123  * Registers names must correspond to dsp_callee_regs structure fields names
 124  * for automatic offset calculation in DSP_AUX_SAVE_RESTORE macros.
 125  */
 126 #define ARC_AUX_DSP_BUILD       0x7A
 127 #define ARC_AUX_ACC0_LO         0x580
 128 #define ARC_AUX_ACC0_GLO        0x581
 129 #define ARC_AUX_ACC0_HI         0x582
 130 #define ARC_AUX_ACC0_GHI        0x583
 131 #define ARC_AUX_DSP_BFLY0       0x598
 132 #define ARC_AUX_DSP_CTRL        0x59F
 133 #define ARC_AUX_DSP_FFT_CTRL    0x59E
 134
 135 #define ARC_AUX_AGU_BUILD       0xCC
 136 #define ARC_AUX_AGU_AP0         0x5C0
 137 #define ARC_AUX_AGU_AP1         0x5C1
 138 #define ARC_AUX_AGU_AP2         0x5C2
 139 #define ARC_AUX_AGU_AP3         0x5C3
 140 #define ARC_AUX_AGU_OS0         0x5D0
 141 #define ARC_AUX_AGU_OS1         0x5D1
 142 #define ARC_AUX_AGU_MOD0        0x5E0
 143 #define ARC_AUX_AGU_MOD1        0x5E1
 144 #define ARC_AUX_AGU_MOD2        0x5E2
 145 #define ARC_AUX_AGU_MOD3        0x5E3
 146
 147 #ifndef __ASSEMBLY__
 148
 149 #include <soc/arc/aux.h>
 150
 151 /* Helpers */
 152 #define TO_KB(bytes)            ((bytes) >> 10)
 153 #define TO_MB(bytes)            (TO_KB(bytes) >> 10)
 154 #define PAGES_TO_KB(n_pages)    ((n_pages) << (PAGE_SHIFT - 10))
 155 #define PAGES_TO_MB(n_pages)    (PAGES_TO_KB(n_pages) >> 10)
 156
 157
 158 /*
 159  ***************************************************************
 160  * Build Configuration Registers, with encoded hardware config
 161  */
 162 struct bcr_identity {
 163 #ifdef CONFIG_CPU_BIG_ENDIAN
 164         unsigned int chip_id:16, cpu_id:8, family:8;
 165 #else
 166         unsigned int family:8, cpu_id:8, chip_id:16;
 167 #endif
 168 };
 169
 170 struct bcr_isa_arcv2 {
 171 #ifdef CONFIG_CPU_BIG_ENDIAN
 172         unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
 173                      pad1:12, ver:8;
 174 #else
 175         unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
 176                      ldd:1, pad2:4, div_rem:4;
 177 #endif
 178 };
 179
 180 struct bcr_uarch_build {
 181 #ifdef CONFIG_CPU_BIG_ENDIAN
 182         unsigned int pad:8, prod:8, maj:8, min:8;
 183 #else
 184         unsigned int min:8, maj:8, prod:8, pad:8;
 185 #endif
 186 };
 187
 188 struct bcr_mmu_3 {
 189 #ifdef CONFIG_CPU_BIG_ENDIAN
 190         unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
 191                      u_itlb:4, u_dtlb:4;
 192 #else
 193         unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
 194                      ways:4, ver:8;
 195 #endif
 196 };
 197
 198 struct bcr_mmu_4 {
 199 #ifdef CONFIG_CPU_BIG_ENDIAN
 200         unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
 201                      n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
 202 #else
 203         /*           DTLB      ITLB      JES        JE         JA      */
 204         unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
 205                      pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
 206 #endif
 207 };
 208
 209 struct bcr_cache {
 210 #ifdef CONFIG_CPU_BIG_ENDIAN
 211         unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
 212 #else
 213         unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
 214 #endif
 215 };
 216
 217 struct bcr_slc_cfg {
 218 #ifdef CONFIG_CPU_BIG_ENDIAN
 219         unsigned int pad:24, way:2, lsz:2, sz:4;
 220 #else
 221         unsigned int sz:4, lsz:2, way:2, pad:24;
 222 #endif
 223 };
 224
 225 struct bcr_clust_cfg {
 226 #ifdef CONFIG_CPU_BIG_ENDIAN
 227         unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
 228 #else
 229         unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
 230 #endif
 231 };
 232
 233 struct bcr_volatile {
 234 #ifdef CONFIG_CPU_BIG_ENDIAN
 235         unsigned int start:4, limit:4, pad:22, order:1, disable:1;
 236 #else
 237         unsigned int disable:1, order:1, pad:22, limit:4, start:4;
 238 #endif
 239 };
 240
 241 struct bcr_mpy {
 242 #ifdef CONFIG_CPU_BIG_ENDIAN
 243         unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
 244 #else
 245         unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
 246 #endif
 247 };
 248
 249 struct bcr_iccm_arcompact {
 250 #ifdef CONFIG_CPU_BIG_ENDIAN
 251         unsigned int base:16, pad:5, sz:3, ver:8;
 252 #else
 253         unsigned int ver:8, sz:3, pad:5, base:16;
 254 #endif
 255 };
 256
 257 struct bcr_iccm_arcv2 {
 258 #ifdef CONFIG_CPU_BIG_ENDIAN
 259         unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
 260 #else
 261         unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
 262 #endif
 263 };
 264
 265 struct bcr_dccm_arcompact {
 266 #ifdef CONFIG_CPU_BIG_ENDIAN
 267         unsigned int res:21, sz:3, ver:8;
 268 #else
 269         unsigned int ver:8, sz:3, res:21;
 270 #endif
 271 };
 272
 273 struct bcr_dccm_arcv2 {
 274 #ifdef CONFIG_CPU_BIG_ENDIAN
 275         unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
 276 #else
 277         unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
 278 #endif
 279 };
 280
 281 /* ARCompact: Both SP and DP FPU BCRs have same format */
 282 struct bcr_fp_arcompact {
 283 #ifdef CONFIG_CPU_BIG_ENDIAN
 284         unsigned int fast:1, ver:8;
 285 #else
 286         unsigned int ver:8, fast:1;
 287 #endif
 288 };
 289
 290 struct bcr_fp_arcv2 {
 291 #ifdef CONFIG_CPU_BIG_ENDIAN
 292         unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
 293 #else
 294         unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
 295 #endif
 296 };
 297
 298 struct bcr_actionpoint {
 299 #ifdef CONFIG_CPU_BIG_ENDIAN
 300         unsigned int pad:21, min:1, num:2, ver:8;
 301 #else
 302         unsigned int ver:8, num:2, min:1, pad:21;
 303 #endif
 304 };
 305
 306 #include <soc/arc/timers.h>
 307
 308 struct bcr_bpu_arcompact {
 309 #ifdef CONFIG_CPU_BIG_ENDIAN
 310         unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
 311 #else
 312         unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
 313 #endif
 314 };
 315
 316 struct bcr_bpu_arcv2 {
 317 #ifdef CONFIG_CPU_BIG_ENDIAN
 318         unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
 319 #else
 320         unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
 321 #endif
 322 };
 323
 324 /* Error Protection Build: ECC/Parity */
 325 struct bcr_erp {
 326 #ifdef CONFIG_CPU_BIG_ENDIAN
 327         unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
 328 #else
 329         unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
 330 #endif
 331 };
 332
 333 /* Error Protection Control */
 334 struct ctl_erp {
 335 #ifdef CONFIG_CPU_BIG_ENDIAN
 336         unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
 337 #else
 338         unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
 339 #endif
 340 };
 341
 342 struct bcr_lpb {
 343 #ifdef CONFIG_CPU_BIG_ENDIAN
 344         unsigned int pad:16, entries:8, ver:8;
 345 #else
 346         unsigned int ver:8, entries:8, pad:16;
 347 #endif
 348 };
 349
 350 struct bcr_generic {
 351 #ifdef CONFIG_CPU_BIG_ENDIAN
 352         unsigned int info:24, ver:8;
 353 #else
 354         unsigned int ver:8, info:24;
 355 #endif
 356 };
 357
 358 static inline int is_isa_arcv2(void)
 359 {
 360         return IS_ENABLED(CONFIG_ISA_ARCV2);
 361 }
 362
 363 static inline int is_isa_arcompact(void)
 364 {
 365         return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
 366 }
 367
 368 #endif /* __ASEMBLY__ */
 369
 370 #endif /* _ASM_ARC_ARCREGS_H */