arch/arc/include/asm/io.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4  */
   5
   6 #ifndef _ASM_ARC_IO_H
   7 #define _ASM_ARC_IO_H
   8
   9 #include <linux/types.h>
  10 #include <asm/byteorder.h>
  11 #include <asm/page.h>
  12 #include <linux/unaligned.h>
  13
  14 #ifdef CONFIG_ISA_ARCV2
  15 #include <asm/barrier.h>
  16 #define __iormb()               rmb()
  17 #define __iowmb()               wmb()
  18 #else
  19 #define __iormb()               do { } while (0)
  20 #define __iowmb()               do { } while (0)
  21 #endif
  22
  23 extern void __iomem *ioremap(phys_addr_t paddr, unsigned long size);
  24 #define ioremap ioremap
  25 #define ioremap_prot ioremap_prot
  26 #define iounmap iounmap
  27 static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
  28 {
  29         return (void __iomem *)port;
  30 }
  31
  32 static inline void ioport_unmap(void __iomem *addr)
  33 {
  34 }
  35
  36 /*
  37  * io{read,write}{16,32}be() macros
  38  */
  39 #define ioread16be(p)           ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
  40 #define ioread32be(p)           ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
  41
  42 #define iowrite16be(v,p)        ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
  43 #define iowrite32be(v,p)        ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
  44
  45 #define __raw_readb __raw_readb
  46 static inline u8 __raw_readb(const volatile void __iomem *addr)
  47 {
  48         u8 b;
  49
  50         __asm__ __volatile__(
  51         "       ldb%U1 %0, %1   \n"
  52         : "=r" (b)
  53         : "m" (*(volatile u8 __force *)addr)
  54         : "memory");
  55
  56         return b;
  57 }
  58
  59 #define __raw_readw __raw_readw
  60 static inline u16 __raw_readw(const volatile void __iomem *addr)
  61 {
  62         u16 s;
  63
  64         __asm__ __volatile__(
  65         "       ldw%U1 %0, %1   \n"
  66         : "=r" (s)
  67         : "m" (*(volatile u16 __force *)addr)
  68         : "memory");
  69
  70         return s;
  71 }
  72
  73 #define __raw_readl __raw_readl
  74 static inline u32 __raw_readl(const volatile void __iomem *addr)
  75 {
  76         u32 w;
  77
  78         __asm__ __volatile__(
  79         "       ld%U1 %0, %1    \n"
  80         : "=r" (w)
  81         : "m" (*(volatile u32 __force *)addr)
  82         : "memory");
  83
  84         return w;
  85 }
  86
  87 /*
  88  * {read,write}s{b,w,l}() repeatedly access the same IO address in
  89  * native endianness in 8-, 16-, 32-bit chunks {into,from} memory,
  90  * @count times
  91  */
  92 #define __raw_readsx(t,f) \
  93 static inline void __raw_reads##f(const volatile void __iomem *addr,    \
  94                                   void *ptr, unsigned int count)        \
  95 {                                                                       \
  96         bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0;        \
  97         u##t *buf = ptr;                                                \
  98                                                                         \
  99         if (!count)                                                     \
 100                 return;                                                 \
 101                                                                         \
 102         /* Some ARC CPU's don't support unaligned accesses */           \
 103         if (is_aligned) {                                               \
 104                 do {                                                    \
 105                         u##t x = __raw_read##f(addr);                   \
 106                         *buf++ = x;                                     \
 107                 } while (--count);                                      \
 108         } else {                                                        \
 109                 do {                                                    \
 110                         u##t x = __raw_read##f(addr);                   \
 111                         put_unaligned(x, buf++);                        \
 112                 } while (--count);                                      \
 113         }                                                               \
 114 }
 115
 116 #define __raw_readsb __raw_readsb
 117 __raw_readsx(8, b)
 118 #define __raw_readsw __raw_readsw
 119 __raw_readsx(16, w)
 120 #define __raw_readsl __raw_readsl
 121 __raw_readsx(32, l)
 122
 123 #define __raw_writeb __raw_writeb
 124 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
 125 {
 126         __asm__ __volatile__(
 127         "       stb%U1 %0, %1   \n"
 128         :
 129         : "r" (b), "m" (*(volatile u8 __force *)addr)
 130         : "memory");
 131 }
 132
 133 #define __raw_writew __raw_writew
 134 static inline void __raw_writew(u16 s, volatile void __iomem *addr)
 135 {
 136         __asm__ __volatile__(
 137         "       stw%U1 %0, %1   \n"
 138         :
 139         : "r" (s), "m" (*(volatile u16 __force *)addr)
 140         : "memory");
 141
 142 }
 143
 144 #define __raw_writel __raw_writel
 145 static inline void __raw_writel(u32 w, volatile void __iomem *addr)
 146 {
 147         __asm__ __volatile__(
 148         "       st%U1 %0, %1    \n"
 149         :
 150         : "r" (w), "m" (*(volatile u32 __force *)addr)
 151         : "memory");
 152
 153 }
 154
 155 #define __raw_writesx(t,f)                                              \
 156 static inline void __raw_writes##f(volatile void __iomem *addr,         \
 157                                    const void *ptr, unsigned int count) \
 158 {                                                                       \
 159         bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0;        \
 160         const u##t *buf = ptr;                                          \
 161                                                                         \
 162         if (!count)                                                     \
 163                 return;                                                 \
 164                                                                         \
 165         /* Some ARC CPU's don't support unaligned accesses */           \
 166         if (is_aligned) {                                               \
 167                 do {                                                    \
 168                         __raw_write##f(*buf++, addr);                   \
 169                 } while (--count);                                      \
 170         } else {                                                        \
 171                 do {                                                    \
 172                         __raw_write##f(get_unaligned(buf++), addr);     \
 173                 } while (--count);                                      \
 174         }                                                               \
 175 }
 176
 177 #define __raw_writesb __raw_writesb
 178 __raw_writesx(8, b)
 179 #define __raw_writesw __raw_writesw
 180 __raw_writesx(16, w)
 181 #define __raw_writesl __raw_writesl
 182 __raw_writesx(32, l)
 183
 184 /*
 185  * MMIO can also get buffered/optimized in micro-arch, so barriers needed
 186  * Based on ARM model for the typical use case
 187  *
 188  *      <ST [DMA buffer]>
 189  *      <writel MMIO "go" reg>
 190  *  or:
 191  *      <readl MMIO "status" reg>
 192  *      <LD [DMA buffer]>
 193  *
 194  * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
 195  */
 196 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 197 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 198 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 199 #define readsb(p,d,l)           ({ __raw_readsb(p,d,l); __iormb(); })
 200 #define readsw(p,d,l)           ({ __raw_readsw(p,d,l); __iormb(); })
 201 #define readsl(p,d,l)           ({ __raw_readsl(p,d,l); __iormb(); })
 202
 203 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed(v,c); })
 204 #define writew(v,c)             ({ __iowmb(); writew_relaxed(v,c); })
 205 #define writel(v,c)             ({ __iowmb(); writel_relaxed(v,c); })
 206 #define writesb(p,d,l)          ({ __iowmb(); __raw_writesb(p,d,l); })
 207 #define writesw(p,d,l)          ({ __iowmb(); __raw_writesw(p,d,l); })
 208 #define writesl(p,d,l)          ({ __iowmb(); __raw_writesl(p,d,l); })
 209
 210 /*
 211  * Relaxed API for drivers which can handle barrier ordering themselves
 212  *
 213  * Also these are defined to perform little endian accesses.
 214  * To provide the typical device register semantics of fixed endian,
 215  * swap the byte order for Big Endian
 216  *
 217  * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
 218  */
 219 #define readb_relaxed(c)        __raw_readb(c)
 220 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
 221                                         __raw_readw(c)); __r; })
 222 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
 223                                         __raw_readl(c)); __r; })
 224
 225 #define writeb_relaxed(v,c)     __raw_writeb(v,c)
 226 #define writew_relaxed(v,c)     __raw_writew((__force u16) cpu_to_le16(v),c)
 227 #define writel_relaxed(v,c)     __raw_writel((__force u32) cpu_to_le32(v),c)
 228
 229 #include <asm-generic/io.h>
 230
 231 #endif /* _ASM_ARC_IO_H */