arch/arc/include/asm/pgtable-bits-arcv2.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4  */
   5
   6 /*
   7  * page table flags for software walked/managed MMUv3 (ARC700) and MMUv4 (HS)
   8  * There correspond to the corresponding bits in the TLB
   9  */
  10
  11 #ifndef _ASM_ARC_PGTABLE_BITS_ARCV2_H
  12 #define _ASM_ARC_PGTABLE_BITS_ARCV2_H
  13
  14 #ifdef CONFIG_ARC_CACHE_PAGES
  15 #define _PAGE_CACHEABLE         (1 << 0)  /* Cached (H) */
  16 #else
  17 #define _PAGE_CACHEABLE         0
  18 #endif
  19
  20 #define _PAGE_EXECUTE           (1 << 1)  /* User Execute  (H) */
  21 #define _PAGE_WRITE             (1 << 2)  /* User Write    (H) */
  22 #define _PAGE_READ              (1 << 3)  /* User Read     (H) */
  23 #define _PAGE_ACCESSED          (1 << 4)  /* Accessed      (s) */
  24 #define _PAGE_DIRTY             (1 << 5)  /* Modified      (s) */
  25 #define _PAGE_SPECIAL           (1 << 6)
  26 #define _PAGE_GLOBAL            (1 << 8)  /* ASID agnostic (H) */
  27 #define _PAGE_PRESENT           (1 << 9)  /* PTE/TLB Valid (H) */
  28
  29 /* We borrow bit 5 to store the exclusive marker in swap PTEs. */
  30 #define _PAGE_SWP_EXCLUSIVE     _PAGE_DIRTY
  31
  32 #ifdef CONFIG_ARC_MMU_V4
  33 #define _PAGE_HW_SZ             (1 << 10)  /* Normal/super (H) */
  34 #else
  35 #define _PAGE_HW_SZ             0
  36 #endif
  37
  38 /* Defaults for every user page */
  39 #define ___DEF          (_PAGE_PRESENT | _PAGE_CACHEABLE)
  40
  41 /* Set of bits not changed in pte_modify */
  42 #define _PAGE_CHG_MASK  (PAGE_MASK_PHYS | _PAGE_ACCESSED | _PAGE_DIRTY | \
  43                                                            _PAGE_SPECIAL)
  44
  45 /* More Abbrevaited helpers */
  46 #define PAGE_U_NONE     __pgprot(___DEF)
  47 #define PAGE_U_R        __pgprot(___DEF | _PAGE_READ)
  48 #define PAGE_U_W_R      __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE)
  49 #define PAGE_U_X_R      __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE)
  50 #define PAGE_U_X_W_R    __pgprot(___DEF \
  51                                 | _PAGE_READ | _PAGE_WRITE | _PAGE_EXECUTE)
  52 #define PAGE_KERNEL     __pgprot(___DEF | _PAGE_GLOBAL \
  53                                 | _PAGE_READ | _PAGE_WRITE | _PAGE_EXECUTE)
  54
  55 #define PAGE_SHARED     PAGE_U_W_R
  56
  57 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
  58
  59 /*
  60  * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
  61  *
  62  * Certain cases have 1:1 mapping
  63  *  e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED
  64  *       which directly corresponds to  PAGE_U_X_R
  65  *
  66  * Other rules which cause the divergence from 1:1 mapping
  67  *
  68  *  1. Although ARC700 can do exclusive execute/write protection (meaning R
  69  *     can be tracked independently of X/W unlike some other CPUs), still to
  70  *     keep things consistent with other archs:
  71  *      -Write implies Read:   W => R
  72  *      -Execute implies Read: X => R
  73  *
  74  *  2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
  75  *     This is to enable COW mechanism
  76  */
  77         /* xwr */
  78 #ifndef __ASSEMBLY__
  79
  80 #define pte_write(pte)          (pte_val(pte) & _PAGE_WRITE)
  81 #define pte_dirty(pte)          (pte_val(pte) & _PAGE_DIRTY)
  82 #define pte_young(pte)          (pte_val(pte) & _PAGE_ACCESSED)
  83 #define pte_special(pte)        (pte_val(pte) & _PAGE_SPECIAL)
  84
  85 #define PTE_BIT_FUNC(fn, op) \
  86         static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
  87
  88 PTE_BIT_FUNC(mknotpresent,     &= ~(_PAGE_PRESENT));
  89 PTE_BIT_FUNC(wrprotect, &= ~(_PAGE_WRITE));
  90 PTE_BIT_FUNC(mkwrite_novma,     |= (_PAGE_WRITE));
  91 PTE_BIT_FUNC(mkclean,   &= ~(_PAGE_DIRTY));
  92 PTE_BIT_FUNC(mkdirty,   |= (_PAGE_DIRTY));
  93 PTE_BIT_FUNC(mkold,     &= ~(_PAGE_ACCESSED));
  94 PTE_BIT_FUNC(mkyoung,   |= (_PAGE_ACCESSED));
  95 PTE_BIT_FUNC(mkspecial, |= (_PAGE_SPECIAL));
  96 PTE_BIT_FUNC(mkhuge,    |= (_PAGE_HW_SZ));
  97
  98 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
  99 {
 100         return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 101 }
 102
 103 struct vm_fault;
 104 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
 105                 unsigned long address, pte_t *ptep, unsigned int nr);
 106
 107 #define update_mmu_cache(vma, addr, ptep) \
 108         update_mmu_cache_range(NULL, vma, addr, ptep, 1)
 109
 110 /*
 111  * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
 112  * are !pte_none() && !pte_present().
 113  *
 114  * Format of swap PTEs:
 115  *
 116  *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 117  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 118  *   <-------------- offset -------------> <--- zero --> E < type ->
 119  *
 120  *   E is the exclusive marker that is not stored in swap entries.
 121  *   The zero'ed bits include _PAGE_PRESENT.
 122  */
 123 #define __swp_entry(type, off)          ((swp_entry_t) \
 124                                         { ((type) & 0x1f) | ((off) << 13) })
 125
 126 /* Decode a PTE containing swap "identifier "into constituents */
 127 #define __swp_type(pte_lookalike)       (((pte_lookalike).val) & 0x1f)
 128 #define __swp_offset(pte_lookalike)     ((pte_lookalike).val >> 13)
 129
 130 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 131 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 132
 133 static inline int pte_swp_exclusive(pte_t pte)
 134 {
 135         return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
 136 }
 137
 138 PTE_BIT_FUNC(swp_mkexclusive, |= (_PAGE_SWP_EXCLUSIVE));
 139 PTE_BIT_FUNC(swp_clear_exclusive, &= ~(_PAGE_SWP_EXCLUSIVE));
 140
 141 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 142 #include <asm/hugepage.h>
 143 #endif
 144
 145 #endif /* __ASSEMBLY__ */
 146
 147 #endif