arch/arm/mach-davinci/da8xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Chip specific defines for DA8XX/OMAP L1XX SoC
   4  *
   5  * Author: Mark A. Greer <mgreer@mvista.com>
   6  *
   7  * 2007, 2009-2010 (c) MontaVista Software, Inc.
   8  */
   9 #ifndef __ASM_ARCH_DAVINCI_DA8XX_H
  10 #define __ASM_ARCH_DAVINCI_DA8XX_H
  11
  12 #include <linux/dma-mapping.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/videodev2.h>
  15 #include <linux/reboot.h>
  16 #include <linux/regmap.h>
  17
  18 #include "hardware.h"
  19 #include "pm.h"
  20
  21 #include <media/davinci/vpif_types.h>
  22
  23 extern void __iomem *da8xx_syscfg0_base;
  24 extern void __iomem *da8xx_syscfg1_base;
  25
  26 /*
  27  * The cp_intc interrupt controller for the da8xx isn't in the same
  28  * chunk of physical memory space as the other registers (like it is
  29  * on the davincis) so it needs to be mapped separately.  It will be
  30  * mapped early on when the I/O space is mapped and we'll put it just
  31  * before the I/O space in the processor's virtual memory space.
  32  */
  33 #define DA8XX_CP_INTC_BASE      0xfffee000
  34 #define DA8XX_CP_INTC_SIZE      SZ_8K
  35 #define DA8XX_CP_INTC_VIRT      (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
  36
  37 #define DA8XX_SYSCFG0_BASE      (IO_PHYS + 0x14000)
  38 #define DA8XX_SYSCFG0_VIRT(x)   (da8xx_syscfg0_base + (x))
  39 #define DA8XX_JTAG_ID_REG       0x18
  40 #define DA8XX_HOST1CFG_REG      0x44
  41 #define DA8XX_CHIPSIG_REG       0x174
  42 #define DA8XX_CFGCHIP0_REG      0x17c
  43 #define DA8XX_CFGCHIP1_REG      0x180
  44 #define DA8XX_CFGCHIP2_REG      0x184
  45 #define DA8XX_CFGCHIP3_REG      0x188
  46 #define DA8XX_CFGCHIP4_REG      0x18c
  47
  48 #define DA8XX_SYSCFG1_BASE      (IO_PHYS + 0x22C000)
  49 #define DA8XX_SYSCFG1_VIRT(x)   (da8xx_syscfg1_base + (x))
  50 #define DA8XX_DEEPSLEEP_REG     0x8
  51 #define DA8XX_PWRDN_REG         0x18
  52
  53 #define DA8XX_PSC0_BASE         0x01c10000
  54 #define DA8XX_PLL0_BASE         0x01c11000
  55 #define DA8XX_TIMER64P0_BASE    0x01c20000
  56 #define DA8XX_TIMER64P1_BASE    0x01c21000
  57 #define DA8XX_VPIF_BASE         0x01e17000
  58 #define DA8XX_GPIO_BASE         0x01e26000
  59 #define DA8XX_PSC1_BASE         0x01e27000
  60
  61 #define DA8XX_DSP_L2_RAM_BASE   0x11800000
  62 #define DA8XX_DSP_L1P_RAM_BASE  (DA8XX_DSP_L2_RAM_BASE + 0x600000)
  63 #define DA8XX_DSP_L1D_RAM_BASE  (DA8XX_DSP_L2_RAM_BASE + 0x700000)
  64
  65 #define DA8XX_AEMIF_CS2_BASE    0x60000000
  66 #define DA8XX_AEMIF_CS3_BASE    0x62000000
  67 #define DA8XX_AEMIF_CTL_BASE    0x68000000
  68 #define DA8XX_SHARED_RAM_BASE   0x80000000
  69 #define DA8XX_ARM_RAM_BASE      0xffff0000
  70
  71 void da830_init(void);
  72
  73 void da850_init(void);
  74
  75 int da850_register_vpif_display
  76                         (struct vpif_display_config *display_config);
  77 int da850_register_vpif_capture
  78                         (struct vpif_capture_config *capture_config);
  79 struct regmap *da8xx_get_cfgchip(void);
  80 void __iomem *da8xx_get_mem_ctlr(void);
  81
  82 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */