arch/arm/mach-omap2/cm-regbits-33xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * AM33XX Power Management register bits
   4  *
   5  * This file is automatically generated from the AM33XX hardware databases.
   6  * Vaibhav Hiremath <hvaibhav@ti.com>
   7  *
   8  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
   9  */
  10
  11
  12 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
  13 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
  14
  15 #define AM33XX_CLKOUT2DIV_SHIFT                         3
  16 #define AM33XX_CLKOUT2DIV_WIDTH                         3
  17 #define AM33XX_CLKOUT2EN_SHIFT                          7
  18 #define AM33XX_CLKOUT2SOURCE_MASK                       (0x7 << 0)
  19 #define AM33XX_CLKSEL_0_0_SHIFT                         0
  20 #define AM33XX_CLKSEL_0_0_WIDTH                         1
  21 #define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
  22 #define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
  23 #define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
  24 #define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
  25 #define AM33XX_CLKTRCTRL_SHIFT                          0
  26 #define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
  27 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
  28 #define AM33XX_DPLL_CLKOUT_DIV_WIDTH                    5
  29 #define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
  30 #define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
  31 #define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
  32 #define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
  33 #define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
  34 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
  35 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH              5
  36 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
  37 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH              5
  38 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
  39 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH              5
  40 #define AM33XX_IDLEST_SHIFT                             16
  41 #define AM33XX_IDLEST_MASK                              (0x3 << 16)
  42 #define AM33XX_MODULEMODE_SHIFT                         0
  43 #define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
  44 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
  45 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
  46 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
  47 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
  48 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
  49 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
  50 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
  51 #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH                  3
  52 #define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
  53 #define AM33XX_STM_PMD_CLKSEL_WIDTH                     2
  54 #define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
  55 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
  56 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
  57 #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH                  3
  58 #define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
  59 #define AM33XX_TRC_PMD_CLKSEL_WIDTH                     2
  60 #endif