1 // SPDX-License-Identifier: GPL-2.0-only
3 * Created by: Nicolas Pitre, October 2012
4 * Copyright: (C) 2012-2013 Linaro Limited
6 * Some portions of this file were originally written by Achin Gupta
7 * Copyright: (C) 2012 ARM Limited
10 #include <linux/delay.h>
11 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/errno.h>
17 #include <linux/irqchip/arm-gic.h>
20 #include <asm/proc-fns.h>
21 #include <asm/cacheflush.h>
22 #include <asm/cputype.h>
25 #include <linux/arm-cci.h>
29 /* SCC conf registers */
30 #define RESET_CTRL 0x018
31 #define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu)))
32 #define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu)))
34 #define A15_CONF 0x400
36 #define SYS_INFO 0x700
37 #define SPC_BASE 0xb00
39 static void __iomem
*scc
;
41 #define TC2_CLUSTERS 2
42 #define TC2_MAX_CPUS_PER_CLUSTER 3
44 static unsigned int tc2_nr_cpus
[TC2_CLUSTERS
];
46 static int tc2_pm_cpu_powerup(unsigned int cpu
, unsigned int cluster
)
48 pr_debug("%s: cpu %u cluster %u\n", __func__
, cpu
, cluster
);
49 if (cluster
>= TC2_CLUSTERS
|| cpu
>= tc2_nr_cpus
[cluster
])
51 ve_spc_set_resume_addr(cluster
, cpu
,
52 __pa_symbol(mcpm_entry_point
));
53 ve_spc_cpu_wakeup_irq(cluster
, cpu
, true);
57 static int tc2_pm_cluster_powerup(unsigned int cluster
)
59 pr_debug("%s: cluster %u\n", __func__
, cluster
);
60 if (cluster
>= TC2_CLUSTERS
)
62 ve_spc_powerdown(cluster
, false);
66 static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu
, unsigned int cluster
)
68 pr_debug("%s: cpu %u cluster %u\n", __func__
, cpu
, cluster
);
69 BUG_ON(cluster
>= TC2_CLUSTERS
|| cpu
>= TC2_MAX_CPUS_PER_CLUSTER
);
70 ve_spc_cpu_wakeup_irq(cluster
, cpu
, true);
72 * If the CPU is committed to power down, make sure
73 * the power controller will be in charge of waking it
74 * up upon IRQ, ie IRQ lines are cut from GIC CPU IF
75 * to the CPU by disabling the GIC CPU IF to prevent wfi
76 * from completing execution behind power controller back
81 static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster
)
83 pr_debug("%s: cluster %u\n", __func__
, cluster
);
84 BUG_ON(cluster
>= TC2_CLUSTERS
);
85 ve_spc_powerdown(cluster
, true);
86 ve_spc_global_wakeup_irq(true);
89 static void tc2_pm_cpu_cache_disable(void)
91 v7_exit_coherency_flush(louis
);
94 static void tc2_pm_cluster_cache_disable(void)
96 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15
) {
98 * On the Cortex-A15 we need to disable
99 * L2 prefetching before flushing the cache.
102 "mcr p15, 1, %0, c15, c0, 3 \n\t"
108 v7_exit_coherency_flush(all
);
109 cci_disable_port_by_cpu(read_cpuid_mpidr());
112 static int tc2_core_in_reset(unsigned int cpu
, unsigned int cluster
)
115 RESET_A7_NCORERESET(cpu
)
116 : RESET_A15_NCORERESET(cpu
);
118 return !(readl_relaxed(scc
+ RESET_CTRL
) & mask
);
122 #define TIMEOUT_MSEC 1000
124 static int tc2_pm_wait_for_powerdown(unsigned int cpu
, unsigned int cluster
)
128 pr_debug("%s: cpu %u cluster %u\n", __func__
, cpu
, cluster
);
129 BUG_ON(cluster
>= TC2_CLUSTERS
|| cpu
>= TC2_MAX_CPUS_PER_CLUSTER
);
131 for (tries
= 0; tries
< TIMEOUT_MSEC
/ POLL_MSEC
; ++tries
) {
132 pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
133 __func__
, cpu
, cluster
,
134 readl_relaxed(scc
+ RESET_CTRL
));
137 * We need the CPU to reach WFI, but the power
138 * controller may put the cluster in reset and
139 * power it off as soon as that happens, before
140 * we have a chance to see STANDBYWFI.
142 * So we need to check for both conditions:
144 if (tc2_core_in_reset(cpu
, cluster
) ||
145 ve_spc_cpu_in_wfi(cpu
, cluster
))
146 return 0; /* success: the CPU is halted */
148 /* Otherwise, wait and retry: */
152 return -ETIMEDOUT
; /* timeout */
155 static void tc2_pm_cpu_suspend_prepare(unsigned int cpu
, unsigned int cluster
)
157 ve_spc_set_resume_addr(cluster
, cpu
, __pa_symbol(mcpm_entry_point
));
160 static void tc2_pm_cpu_is_up(unsigned int cpu
, unsigned int cluster
)
162 pr_debug("%s: cpu %u cluster %u\n", __func__
, cpu
, cluster
);
163 BUG_ON(cluster
>= TC2_CLUSTERS
|| cpu
>= TC2_MAX_CPUS_PER_CLUSTER
);
164 ve_spc_cpu_wakeup_irq(cluster
, cpu
, false);
165 ve_spc_set_resume_addr(cluster
, cpu
, 0);
168 static void tc2_pm_cluster_is_up(unsigned int cluster
)
170 pr_debug("%s: cluster %u\n", __func__
, cluster
);
171 BUG_ON(cluster
>= TC2_CLUSTERS
);
172 ve_spc_powerdown(cluster
, false);
173 ve_spc_global_wakeup_irq(false);
176 static const struct mcpm_platform_ops tc2_pm_power_ops
= {
177 .cpu_powerup
= tc2_pm_cpu_powerup
,
178 .cluster_powerup
= tc2_pm_cluster_powerup
,
179 .cpu_suspend_prepare
= tc2_pm_cpu_suspend_prepare
,
180 .cpu_powerdown_prepare
= tc2_pm_cpu_powerdown_prepare
,
181 .cluster_powerdown_prepare
= tc2_pm_cluster_powerdown_prepare
,
182 .cpu_cache_disable
= tc2_pm_cpu_cache_disable
,
183 .cluster_cache_disable
= tc2_pm_cluster_cache_disable
,
184 .wait_for_powerdown
= tc2_pm_wait_for_powerdown
,
185 .cpu_is_up
= tc2_pm_cpu_is_up
,
186 .cluster_is_up
= tc2_pm_cluster_is_up
,
190 * Enable cluster-level coherency, in preparation for turning on the MMU.
192 static void __naked
tc2_pm_power_up_setup(unsigned int affinity_level
)
197 " b cci_enable_port_for_self ");
200 static int __init
tc2_pm_init(void)
202 unsigned int mpidr
, cpu
, cluster
;
204 u32 a15_cluster_id
, a7_cluster_id
, sys_info
;
205 struct device_node
*np
;
208 * The power management-related features are hidden behind
209 * SCC registers. We need to extract runtime information like
210 * cluster ids and number of CPUs really available in clusters.
212 np
= of_find_compatible_node(NULL
, NULL
,
213 "arm,vexpress-scc,v2p-ca15_a7");
214 scc
= of_iomap(np
, 0);
218 a15_cluster_id
= readl_relaxed(scc
+ A15_CONF
) & 0xf;
219 a7_cluster_id
= readl_relaxed(scc
+ A7_CONF
) & 0xf;
220 if (a15_cluster_id
>= TC2_CLUSTERS
|| a7_cluster_id
>= TC2_CLUSTERS
)
223 sys_info
= readl_relaxed(scc
+ SYS_INFO
);
224 tc2_nr_cpus
[a15_cluster_id
] = (sys_info
>> 16) & 0xf;
225 tc2_nr_cpus
[a7_cluster_id
] = (sys_info
>> 20) & 0xf;
227 irq
= irq_of_parse_and_map(np
, 0);
230 * A subset of the SCC registers is also used to communicate
231 * with the SPC (power controller). We need to be able to
232 * drive it very early in the boot process to power up
233 * processors, so we initialize the SPC driver here.
235 ret
= ve_spc_init(scc
+ SPC_BASE
, a15_cluster_id
, irq
);
242 mpidr
= read_cpuid_mpidr();
243 cpu
= MPIDR_AFFINITY_LEVEL(mpidr
, 0);
244 cluster
= MPIDR_AFFINITY_LEVEL(mpidr
, 1);
245 pr_debug("%s: cpu %u cluster %u\n", __func__
, cpu
, cluster
);
246 if (cluster
>= TC2_CLUSTERS
|| cpu
>= tc2_nr_cpus
[cluster
]) {
247 pr_err("%s: boot CPU is out of bound!\n", __func__
);
251 ret
= mcpm_platform_register(&tc2_pm_power_ops
);
253 mcpm_sync_init(tc2_pm_power_up_setup
);
254 /* test if we can (re)enable the CCI on our own */
255 BUG_ON(mcpm_loopback(tc2_pm_cluster_cache_disable
) != 0);
256 pr_info("TC2 power management initialized\n");
261 early_initcall(tc2_pm_init
);