arch/arm/mm/cache-tauros2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
   4  *
   5  * Copyright (C) 2008 Marvell Semiconductor
   6  *
   7  * References:
   8  * - PJ1 CPU Core Datasheet,
   9  *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
  10  * - PJ4 CPU Core Datasheet,
  11  *   Document ID MV-S105190-00, Rev 0.7, March 14 2008.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <asm/cacheflush.h>
  18 #include <asm/cp15.h>
  19 #include <asm/cputype.h>
  20 #include <asm/hardware/cache-tauros2.h>
  21
  22 /* CP15 PJ4 Control configuration register */
  23 #define CCR_L2C_PREFETCH_DISABLE        BIT(24)
  24 #define CCR_L2C_ECC_ENABLE              BIT(23)
  25 #define CCR_L2C_WAY7_4_DISABLE          BIT(21)
  26 #define CCR_L2C_BURST8_ENABLE           BIT(20)
  27
  28 /*
  29  * When Tauros2 is used on a CPU that supports the v7 hierarchical
  30  * cache operations, the cache handling code in proc-v7.S takes care
  31  * of everything, including handling DMA coherency.
  32  *
  33  * So, we only need to register outer cache operations here if we're
  34  * being used on a pre-v7 CPU, and we only need to build support for
  35  * outer cache operations into the kernel image if the kernel has been
  36  * configured to support a pre-v7 CPU.
  37  */
  38 #ifdef CONFIG_CPU_32v5
  39 /*
  40  * Low-level cache maintenance operations.
  41  */
  42 static inline void tauros2_clean_pa(unsigned long addr)
  43 {
  44         __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
  45 }
  46
  47 static inline void tauros2_clean_inv_pa(unsigned long addr)
  48 {
  49         __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
  50 }
  51
  52 static inline void tauros2_inv_pa(unsigned long addr)
  53 {
  54         __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
  55 }
  56
  57
  58 /*
  59  * Linux primitives.
  60  *
  61  * Note that the end addresses passed to Linux primitives are
  62  * noninclusive.
  63  */
  64 #define CACHE_LINE_SIZE         32
  65
  66 static void tauros2_inv_range(unsigned long start, unsigned long end)
  67 {
  68         /*
  69          * Clean and invalidate partial first cache line.
  70          */
  71         if (start & (CACHE_LINE_SIZE - 1)) {
  72                 tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
  73                 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
  74         }
  75
  76         /*
  77          * Clean and invalidate partial last cache line.
  78          */
  79         if (end & (CACHE_LINE_SIZE - 1)) {
  80                 tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
  81                 end &= ~(CACHE_LINE_SIZE - 1);
  82         }
  83
  84         /*
  85          * Invalidate all full cache lines between 'start' and 'end'.
  86          */
  87         while (start < end) {
  88                 tauros2_inv_pa(start);
  89                 start += CACHE_LINE_SIZE;
  90         }
  91
  92         dsb();
  93 }
  94
  95 static void tauros2_clean_range(unsigned long start, unsigned long end)
  96 {
  97         start &= ~(CACHE_LINE_SIZE - 1);
  98         while (start < end) {
  99                 tauros2_clean_pa(start);
 100                 start += CACHE_LINE_SIZE;
 101         }
 102
 103         dsb();
 104 }
 105
 106 static void tauros2_flush_range(unsigned long start, unsigned long end)
 107 {
 108         start &= ~(CACHE_LINE_SIZE - 1);
 109         while (start < end) {
 110                 tauros2_clean_inv_pa(start);
 111                 start += CACHE_LINE_SIZE;
 112         }
 113
 114         dsb();
 115 }
 116
 117 static void tauros2_disable(void)
 118 {
 119         __asm__ __volatile__ (
 120         "mcr    p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t"
 121         "mrc    p15, 0, %0, c1, c0, 0\n\t"
 122         "bic    %0, %0, #(1 << 26)\n\t"
 123         "mcr    p15, 0, %0, c1, c0, 0  @Disable L2 Cache\n\t"
 124         : : "r" (0x0));
 125 }
 126
 127 static void tauros2_resume(void)
 128 {
 129         __asm__ __volatile__ (
 130         "mcr    p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t"
 131         "mrc    p15, 0, %0, c1, c0, 0\n\t"
 132         "orr    %0, %0, #(1 << 26)\n\t"
 133         "mcr    p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t"
 134         : : "r" (0x0));
 135 }
 136 #endif
 137
 138 static inline u32 __init read_extra_features(void)
 139 {
 140         u32 u;
 141
 142         __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
 143
 144         return u;
 145 }
 146
 147 static inline void __init write_extra_features(u32 u)
 148 {
 149         __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
 150 }
 151
 152 static inline int __init cpuid_scheme(void)
 153 {
 154         return !!((processor_id & 0x000f0000) == 0x000f0000);
 155 }
 156
 157 static inline u32 __init read_mmfr3(void)
 158 {
 159         u32 mmfr3;
 160
 161         __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));
 162
 163         return mmfr3;
 164 }
 165
 166 static inline u32 __init read_actlr(void)
 167 {
 168         u32 actlr;
 169
 170         __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
 171
 172         return actlr;
 173 }
 174
 175 static inline void __init write_actlr(u32 actlr)
 176 {
 177         __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
 178 }
 179
 180 static void enable_extra_feature(unsigned int features)
 181 {
 182         u32 u;
 183
 184         u = read_extra_features();
 185
 186         if (features & CACHE_TAUROS2_PREFETCH_ON)
 187                 u &= ~CCR_L2C_PREFETCH_DISABLE;
 188         else
 189                 u |= CCR_L2C_PREFETCH_DISABLE;
 190         pr_info("Tauros2: %s L2 prefetch.\n",
 191                         (features & CACHE_TAUROS2_PREFETCH_ON)
 192                         ? "Enabling" : "Disabling");
 193
 194         if (features & CACHE_TAUROS2_LINEFILL_BURST8)
 195                 u |= CCR_L2C_BURST8_ENABLE;
 196         else
 197                 u &= ~CCR_L2C_BURST8_ENABLE;
 198         pr_info("Tauros2: %s burst8 line fill.\n",
 199                         (features & CACHE_TAUROS2_LINEFILL_BURST8)
 200                         ? "Enabling" : "Disabling");
 201
 202         write_extra_features(u);
 203 }
 204
 205 static void __init tauros2_internal_init(unsigned int features)
 206 {
 207         char *mode = NULL;
 208
 209         enable_extra_feature(features);
 210
 211 #ifdef CONFIG_CPU_32v5
 212         if ((processor_id & 0xff0f0000) == 0x56050000) {
 213                 u32 feat;
 214
 215                 /*
 216                  * v5 CPUs with Tauros2 have the L2 cache enable bit
 217                  * located in the CPU Extra Features register.
 218                  */
 219                 feat = read_extra_features();
 220                 if (!(feat & 0x00400000)) {
 221                         pr_info("Tauros2: Enabling L2 cache.\n");
 222                         write_extra_features(feat | 0x00400000);
 223                 }
 224
 225                 mode = "ARMv5";
 226                 outer_cache.inv_range = tauros2_inv_range;
 227                 outer_cache.clean_range = tauros2_clean_range;
 228                 outer_cache.flush_range = tauros2_flush_range;
 229                 outer_cache.disable = tauros2_disable;
 230                 outer_cache.resume = tauros2_resume;
 231         }
 232 #endif
 233
 234 #ifdef CONFIG_CPU_32v7
 235         /*
 236          * Check whether this CPU has support for the v7 hierarchical
 237          * cache ops.  (PJ4 is in its v7 personality mode if the MMFR3
 238          * register indicates support for the v7 hierarchical cache
 239          * ops.)
 240          *
 241          * (Although strictly speaking there may exist CPUs that
 242          * implement the v7 cache ops but are only ARMv6 CPUs (due to
 243          * not complying with all of the other ARMv7 requirements),
 244          * there are no real-life examples of Tauros2 being used on
 245          * such CPUs as of yet.)
 246          */
 247         if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
 248                 u32 actlr;
 249
 250                 /*
 251                  * When Tauros2 is used in an ARMv7 system, the L2
 252                  * enable bit is located in the Auxiliary System Control
 253                  * Register (which is the only register allowed by the
 254                  * ARMv7 spec to contain fine-grained cache control bits).
 255                  */
 256                 actlr = read_actlr();
 257                 if (!(actlr & 0x00000002)) {
 258                         pr_info("Tauros2: Enabling L2 cache.\n");
 259                         write_actlr(actlr | 0x00000002);
 260                 }
 261
 262                 mode = "ARMv7";
 263         }
 264 #endif
 265
 266         if (mode == NULL) {
 267                 pr_crit("Tauros2: Unable to detect CPU mode.\n");
 268                 return;
 269         }
 270
 271         pr_info("Tauros2: L2 cache support initialised "
 272                          "in %s mode.\n", mode);
 273 }
 274
 275 #ifdef CONFIG_OF
 276 static const struct of_device_id tauros2_ids[] __initconst = {
 277         { .compatible = "marvell,tauros2-cache"},
 278         {}
 279 };
 280 #endif
 281
 282 void __init tauros2_init(unsigned int features)
 283 {
 284 #ifdef CONFIG_OF
 285         struct device_node *node;
 286         int ret;
 287         unsigned int f;
 288
 289         node = of_find_matching_node(NULL, tauros2_ids);
 290         if (!node) {
 291                 pr_info("Not found marvell,tauros2-cache, disable it\n");
 292         } else {
 293                 ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f);
 294                 if (ret) {
 295                         pr_info("Not found marvell,tauros-cache-features property, "
 296                                 "disable extra features\n");
 297                         features = 0;
 298                 } else
 299                         features = f;
 300         }
 301 #endif
 302         tauros2_internal_init(features);
 303 }