arch/arm64/include/asm/cache.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012 ARM Ltd.
   4  */
   5 #ifndef __ASM_CACHE_H
   6 #define __ASM_CACHE_H
   7
   8 #define L1_CACHE_SHIFT          (6)
   9 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
  10
  11 #define CLIDR_LOUU_SHIFT        27
  12 #define CLIDR_LOC_SHIFT         24
  13 #define CLIDR_LOUIS_SHIFT       21
  14
  15 #define CLIDR_LOUU(clidr)       (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
  16 #define CLIDR_LOC(clidr)        (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
  17 #define CLIDR_LOUIS(clidr)      (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
  18
  19 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
  20 #define CLIDR_CTYPE_SHIFT(level)        (3 * (level - 1))
  21 #define CLIDR_CTYPE_MASK(level)         (7 << CLIDR_CTYPE_SHIFT(level))
  22 #define CLIDR_CTYPE(clidr, level)       \
  23         (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
  24
  25 /* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */
  26 #define CLIDR_TTYPE_SHIFT(level)        (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT)
  27
  28 /*
  29  * Memory returned by kmalloc() may be used for DMA, so we must make
  30  * sure that all such allocations are cache aligned. Otherwise,
  31  * unrelated code may cause parts of the buffer to be read into the
  32  * cache before the transfer is done, causing old data to be seen by
  33  * the CPU.
  34  */
  35 #define ARCH_DMA_MINALIGN       (128)
  36 #define ARCH_KMALLOC_MINALIGN   (8)
  37
  38 #ifndef __ASSEMBLY__
  39
  40 #include <linux/bitops.h>
  41 #include <linux/kasan-enabled.h>
  42
  43 #include <asm/cputype.h>
  44 #include <asm/mte-def.h>
  45 #include <asm/sysreg.h>
  46
  47 #ifdef CONFIG_KASAN_SW_TAGS
  48 #define ARCH_SLAB_MINALIGN      (1ULL << KASAN_SHADOW_SCALE_SHIFT)
  49 #elif defined(CONFIG_KASAN_HW_TAGS)
  50 static inline unsigned int arch_slab_minalign(void)
  51 {
  52         return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE :
  53                                          __alignof__(unsigned long long);
  54 }
  55 #define arch_slab_minalign() arch_slab_minalign()
  56 #endif
  57
  58 #define CTR_L1IP(ctr)           SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
  59
  60 #define ICACHEF_ALIASING        0
  61 extern unsigned long __icache_flags;
  62
  63 /*
  64  * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
  65  * permitted in the I-cache.
  66  */
  67 static inline int icache_is_aliasing(void)
  68 {
  69         return test_bit(ICACHEF_ALIASING, &__icache_flags);
  70 }
  71
  72 static inline u32 cache_type_cwg(void)
  73 {
  74         return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());
  75 }
  76
  77 #define __read_mostly __section(".data..read_mostly")
  78
  79 static inline int cache_line_size_of_cpu(void)
  80 {
  81         u32 cwg = cache_type_cwg();
  82
  83         return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
  84 }
  85
  86 int cache_line_size(void);
  87
  88 #define dma_get_cache_alignment cache_line_size
  89
  90 /*
  91  * Read the effective value of CTR_EL0.
  92  *
  93  * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
  94  * section D10.2.33 "CTR_EL0, Cache Type Register" :
  95  *
  96  * CTR_EL0.IDC reports the data cache clean requirements for
  97  * instruction to data coherence.
  98  *
  99  *  0 - dcache clean to PoU is required unless :
 100  *     (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
 101  *  1 - dcache clean to PoU is not required for i-to-d coherence.
 102  *
 103  * This routine provides the CTR_EL0 with the IDC field updated to the
 104  * effective state.
 105  */
 106 static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
 107 {
 108         u32 ctr = read_cpuid_cachetype();
 109
 110         if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
 111                 u64 clidr = read_sysreg(clidr_el1);
 112
 113                 if (CLIDR_LOC(clidr) == 0 ||
 114                     (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
 115                         ctr |= BIT(CTR_EL0_IDC_SHIFT);
 116         }
 117
 118         return ctr;
 119 }
 120
 121 #endif  /* __ASSEMBLY__ */
 122
 123 #endif