1 // SPDX-License-Identifier: GPL-2.0-only
3 * Atheros AR71XX/AR724X/AR913X specific setup
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
9 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
12 #include <linux/kernel.h>
13 #include <linux/init.h>
15 #include <linux/memblock.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/of_clk.h>
19 #include <linux/of_fdt.h>
20 #include <linux/irqchip.h>
22 #include <asm/bootinfo.h>
24 #include <asm/time.h> /* for mips_hpt_frequency */
25 #include <asm/reboot.h> /* for _machine_{restart,halt} */
27 #include <asm/fw/fw.h>
29 #include <asm/mach-ath79/ath79.h>
30 #include <asm/mach-ath79/ar71xx_regs.h>
33 #define ATH79_SYS_TYPE_LEN 64
35 static char ath79_sys_type
[ATH79_SYS_TYPE_LEN
];
37 static void ath79_halt(void)
43 static void __init
ath79_detect_sys_type(void)
52 id
= ath79_reset_rr(AR71XX_RESET_REG_REV_ID
);
53 major
= id
& REV_ID_MAJOR_MASK
;
56 case REV_ID_MAJOR_AR71XX
:
57 minor
= id
& AR71XX_REV_ID_MINOR_MASK
;
58 rev
= id
>> AR71XX_REV_ID_REVISION_SHIFT
;
59 rev
&= AR71XX_REV_ID_REVISION_MASK
;
61 case AR71XX_REV_ID_MINOR_AR7130
:
62 ath79_soc
= ATH79_SOC_AR7130
;
66 case AR71XX_REV_ID_MINOR_AR7141
:
67 ath79_soc
= ATH79_SOC_AR7141
;
71 case AR71XX_REV_ID_MINOR_AR7161
:
72 ath79_soc
= ATH79_SOC_AR7161
;
78 case REV_ID_MAJOR_AR7240
:
79 ath79_soc
= ATH79_SOC_AR7240
;
81 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
84 case REV_ID_MAJOR_AR7241
:
85 ath79_soc
= ATH79_SOC_AR7241
;
87 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
90 case REV_ID_MAJOR_AR7242
:
91 ath79_soc
= ATH79_SOC_AR7242
;
93 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
96 case REV_ID_MAJOR_AR913X
:
97 minor
= id
& AR913X_REV_ID_MINOR_MASK
;
98 rev
= id
>> AR913X_REV_ID_REVISION_SHIFT
;
99 rev
&= AR913X_REV_ID_REVISION_MASK
;
101 case AR913X_REV_ID_MINOR_AR9130
:
102 ath79_soc
= ATH79_SOC_AR9130
;
106 case AR913X_REV_ID_MINOR_AR9132
:
107 ath79_soc
= ATH79_SOC_AR9132
;
113 case REV_ID_MAJOR_AR9330
:
114 ath79_soc
= ATH79_SOC_AR9330
;
116 rev
= id
& AR933X_REV_ID_REVISION_MASK
;
119 case REV_ID_MAJOR_AR9331
:
120 ath79_soc
= ATH79_SOC_AR9331
;
122 rev
= id
& AR933X_REV_ID_REVISION_MASK
;
125 case REV_ID_MAJOR_AR9341
:
126 ath79_soc
= ATH79_SOC_AR9341
;
128 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
131 case REV_ID_MAJOR_AR9342
:
132 ath79_soc
= ATH79_SOC_AR9342
;
134 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
137 case REV_ID_MAJOR_AR9344
:
138 ath79_soc
= ATH79_SOC_AR9344
;
140 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
143 case REV_ID_MAJOR_QCA9533_V2
:
147 case REV_ID_MAJOR_QCA9533
:
148 ath79_soc
= ATH79_SOC_QCA9533
;
150 rev
= id
& QCA953X_REV_ID_REVISION_MASK
;
153 case REV_ID_MAJOR_QCA9556
:
154 ath79_soc
= ATH79_SOC_QCA9556
;
156 rev
= id
& QCA955X_REV_ID_REVISION_MASK
;
159 case REV_ID_MAJOR_QCA9558
:
160 ath79_soc
= ATH79_SOC_QCA9558
;
162 rev
= id
& QCA955X_REV_ID_REVISION_MASK
;
165 case REV_ID_MAJOR_QCA956X
:
166 ath79_soc
= ATH79_SOC_QCA956X
;
168 rev
= id
& QCA956X_REV_ID_REVISION_MASK
;
171 case REV_ID_MAJOR_QCN550X
:
172 ath79_soc
= ATH79_SOC_QCA956X
;
174 rev
= id
& QCA956X_REV_ID_REVISION_MASK
;
177 case REV_ID_MAJOR_TP9343
:
178 ath79_soc
= ATH79_SOC_TP9343
;
180 rev
= id
& QCA956X_REV_ID_REVISION_MASK
;
184 panic("ath79: unknown SoC, id:0x%08x", id
);
190 if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
191 sprintf(ath79_sys_type
, "Qualcomm Atheros QCA%s ver %u rev %u",
193 else if (soc_is_tp9343())
194 sprintf(ath79_sys_type
, "Qualcomm Atheros TP%s rev %u",
197 sprintf(ath79_sys_type
, "Atheros AR%s rev %u", chip
, rev
);
198 pr_info("SoC: %s\n", ath79_sys_type
);
201 const char *get_system_type(void)
203 return ath79_sys_type
;
206 unsigned int get_c0_compare_int(void)
208 return CP0_LEGACY_COMPARE_IRQ
;
211 void __init
plat_mem_setup(void)
215 set_io_port_base(KSEG1
);
217 /* Get the position of the FDT passed by the bootloader */
218 dtb
= (void *)fw_getenvl("fdt_start");
223 __dt_setup_arch((void *)KSEG0ADDR(dtb
));
225 ath79_reset_base
= ioremap(AR71XX_RESET_BASE
,
227 ath79_pll_base
= ioremap(AR71XX_PLL_BASE
,
229 ath79_detect_sys_type();
230 ath79_ddr_ctrl_init();
232 detect_memory_region(0, ATH79_MEM_SIZE_MIN
, ATH79_MEM_SIZE_MAX
);
234 _machine_halt
= ath79_halt
;
235 pm_power_off
= ath79_halt
;
238 void __init
plat_time_init(void)
240 struct device_node
*np
;
242 unsigned long cpu_clk_rate
;
246 np
= of_get_cpu_node(0, NULL
);
248 pr_err("Failed to get CPU node\n");
252 clk
= of_clk_get(np
, 0);
254 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk
));
258 cpu_clk_rate
= clk_get_rate(clk
);
260 pr_info("CPU clock: %lu.%03lu MHz\n",
261 cpu_clk_rate
/ 1000000, (cpu_clk_rate
/ 1000) % 1000);
263 mips_hpt_frequency
= cpu_clk_rate
/ 2;
268 void __init
arch_init_irq(void)