arch/mips/pci/pci-rt3883.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Ralink RT3662/RT3883 SoC PCI support
   4  *
   5  *  Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  Parts of this file are based on Ralink's 2.6.21 BSP
   8  */
   9
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/io.h>
  13 #include <linux/init.h>
  14 #include <linux/delay.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/of.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_pci.h>
  20 #include <linux/platform_device.h>
  21
  22 #include <asm/mach-ralink/rt3883.h>
  23 #include <asm/mach-ralink/ralink_regs.h>
  24
  25 #define RT3883_MEMORY_BASE              0x00000000
  26 #define RT3883_MEMORY_SIZE              0x02000000
  27
  28 #define RT3883_PCI_REG_PCICFG           0x00
  29 #define   RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
  30 #define   RT3883_PCICFG_P2P_BR_DEVNUM_S 16
  31 #define   RT3883_PCICFG_PCIRST          BIT(1)
  32 #define RT3883_PCI_REG_PCIRAW           0x04
  33 #define RT3883_PCI_REG_PCIINT           0x08
  34 #define RT3883_PCI_REG_PCIENA           0x0c
  35
  36 #define RT3883_PCI_REG_CFGADDR          0x20
  37 #define RT3883_PCI_REG_CFGDATA          0x24
  38 #define RT3883_PCI_REG_MEMBASE          0x28
  39 #define RT3883_PCI_REG_IOBASE           0x2c
  40 #define RT3883_PCI_REG_ARBCTL           0x80
  41
  42 #define RT3883_PCI_REG_BASE(_x)         (0x1000 + (_x) * 0x1000)
  43 #define RT3883_PCI_REG_BAR0SETUP(_x)    (RT3883_PCI_REG_BASE((_x)) + 0x10)
  44 #define RT3883_PCI_REG_IMBASEBAR0(_x)   (RT3883_PCI_REG_BASE((_x)) + 0x18)
  45 #define RT3883_PCI_REG_ID(_x)           (RT3883_PCI_REG_BASE((_x)) + 0x30)
  46 #define RT3883_PCI_REG_CLASS(_x)        (RT3883_PCI_REG_BASE((_x)) + 0x34)
  47 #define RT3883_PCI_REG_SUBID(_x)        (RT3883_PCI_REG_BASE((_x)) + 0x38)
  48 #define RT3883_PCI_REG_STATUS(_x)       (RT3883_PCI_REG_BASE((_x)) + 0x50)
  49
  50 #define RT3883_PCI_MODE_NONE    0
  51 #define RT3883_PCI_MODE_PCI     BIT(0)
  52 #define RT3883_PCI_MODE_PCIE    BIT(1)
  53 #define RT3883_PCI_MODE_BOTH    (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
  54
  55 #define RT3883_PCI_IRQ_COUNT    32
  56
  57 #define RT3883_P2P_BR_DEVNUM    1
  58
  59 struct rt3883_pci_controller {
  60         void __iomem *base;
  61
  62         struct device_node *intc_of_node;
  63         struct irq_domain *irq_domain;
  64
  65         struct pci_controller pci_controller;
  66         struct resource io_res;
  67         struct resource mem_res;
  68
  69         bool pcie_ready;
  70 };
  71
  72 static inline struct rt3883_pci_controller *
  73 pci_bus_to_rt3883_controller(struct pci_bus *bus)
  74 {
  75         struct pci_controller *hose;
  76
  77         hose = (struct pci_controller *) bus->sysdata;
  78         return container_of(hose, struct rt3883_pci_controller, pci_controller);
  79 }
  80
  81 static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
  82                                  unsigned reg)
  83 {
  84         return ioread32(rpc->base + reg);
  85 }
  86
  87 static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
  88                                   u32 val, unsigned reg)
  89 {
  90         iowrite32(val, rpc->base + reg);
  91 }
  92
  93 static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  94                                          unsigned int func, unsigned int where)
  95 {
  96         return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
  97                0x80000000;
  98 }
  99
 100 static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
 101                                unsigned bus, unsigned slot,
 102                                unsigned func, unsigned reg)
 103 {
 104         u32 address;
 105
 106         address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 107
 108         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 109
 110         return rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 111 }
 112
 113 static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
 114                                  unsigned bus, unsigned slot,
 115                                  unsigned func, unsigned reg, u32 val)
 116 {
 117         u32 address;
 118
 119         address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
 120
 121         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 122         rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
 123 }
 124
 125 static void rt3883_pci_irq_handler(struct irq_desc *desc)
 126 {
 127         struct rt3883_pci_controller *rpc;
 128         u32 pending;
 129
 130         rpc = irq_desc_get_handler_data(desc);
 131
 132         pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
 133                   rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 134
 135         if (!pending) {
 136                 spurious_interrupt();
 137                 return;
 138         }
 139
 140         while (pending) {
 141                 unsigned bit = __ffs(pending);
 142
 143                 generic_handle_domain_irq(rpc->irq_domain, bit);
 144
 145                 pending &= ~BIT(bit);
 146         }
 147 }
 148
 149 static void rt3883_pci_irq_unmask(struct irq_data *d)
 150 {
 151         struct rt3883_pci_controller *rpc;
 152         u32 t;
 153
 154         rpc = irq_data_get_irq_chip_data(d);
 155
 156         t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 157         rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 158         /* flush write */
 159         rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 160 }
 161
 162 static void rt3883_pci_irq_mask(struct irq_data *d)
 163 {
 164         struct rt3883_pci_controller *rpc;
 165         u32 t;
 166
 167         rpc = irq_data_get_irq_chip_data(d);
 168
 169         t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 170         rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
 171         /* flush write */
 172         rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
 173 }
 174
 175 static struct irq_chip rt3883_pci_irq_chip = {
 176         .name           = "RT3883 PCI",
 177         .irq_mask       = rt3883_pci_irq_mask,
 178         .irq_unmask     = rt3883_pci_irq_unmask,
 179         .irq_mask_ack   = rt3883_pci_irq_mask,
 180 };
 181
 182 static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
 183                               irq_hw_number_t hw)
 184 {
 185         irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
 186         irq_set_chip_data(irq, d->host_data);
 187
 188         return 0;
 189 }
 190
 191 static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
 192         .map = rt3883_pci_irq_map,
 193         .xlate = irq_domain_xlate_onecell,
 194 };
 195
 196 static int rt3883_pci_irq_init(struct device *dev,
 197                                struct rt3883_pci_controller *rpc)
 198 {
 199         int irq;
 200
 201         irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
 202         if (irq == 0) {
 203                 dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
 204                 return -EINVAL;
 205         }
 206
 207         /* disable all interrupts */
 208         rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
 209
 210         rpc->irq_domain =
 211                 irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
 212                                       &rt3883_pci_irq_domain_ops,
 213                                       rpc);
 214         if (!rpc->irq_domain) {
 215                 dev_err(dev, "unable to add IRQ domain\n");
 216                 return -ENODEV;
 217         }
 218
 219         irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
 220
 221         return 0;
 222 }
 223
 224 static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
 225                                   int where, int size, u32 *val)
 226 {
 227         struct rt3883_pci_controller *rpc;
 228         u32 address;
 229         u32 data;
 230
 231         rpc = pci_bus_to_rt3883_controller(bus);
 232
 233         if (!rpc->pcie_ready && bus->number == 1)
 234                 return PCIBIOS_DEVICE_NOT_FOUND;
 235
 236         address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 237                                          PCI_FUNC(devfn), where);
 238
 239         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 240         data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 241
 242         switch (size) {
 243         case 1:
 244                 *val = (data >> ((where & 3) << 3)) & 0xff;
 245                 break;
 246         case 2:
 247                 *val = (data >> ((where & 3) << 3)) & 0xffff;
 248                 break;
 249         case 4:
 250                 *val = data;
 251                 break;
 252         }
 253
 254         return PCIBIOS_SUCCESSFUL;
 255 }
 256
 257 static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 258                                    int where, int size, u32 val)
 259 {
 260         struct rt3883_pci_controller *rpc;
 261         u32 address;
 262         u32 data;
 263
 264         rpc = pci_bus_to_rt3883_controller(bus);
 265
 266         if (!rpc->pcie_ready && bus->number == 1)
 267                 return PCIBIOS_DEVICE_NOT_FOUND;
 268
 269         address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 270                                          PCI_FUNC(devfn), where);
 271
 272         rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
 273         data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
 274
 275         switch (size) {
 276         case 1:
 277                 data = (data & ~(0xff << ((where & 3) << 3))) |
 278                        (val << ((where & 3) << 3));
 279                 break;
 280         case 2:
 281                 data = (data & ~(0xffff << ((where & 3) << 3))) |
 282                        (val << ((where & 3) << 3));
 283                 break;
 284         case 4:
 285                 data = val;
 286                 break;
 287         }
 288
 289         rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
 290
 291         return PCIBIOS_SUCCESSFUL;
 292 }
 293
 294 static struct pci_ops rt3883_pci_ops = {
 295         .read   = rt3883_pci_config_read,
 296         .write  = rt3883_pci_config_write,
 297 };
 298
 299 static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
 300 {
 301         u32 syscfg1;
 302         u32 rstctrl;
 303         u32 clkcfg1;
 304         u32 t;
 305
 306         rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 307         syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
 308         clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 309
 310         if (mode & RT3883_PCI_MODE_PCIE) {
 311                 rstctrl |= RT3883_RSTCTRL_PCIE;
 312                 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 313
 314                 /* setup PCI PAD drive mode */
 315                 syscfg1 &= ~(0x30);
 316                 syscfg1 |= (2 << 4);
 317                 rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 318
 319                 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 320                 t &= ~BIT(31);
 321                 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 322
 323                 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 324                 t &= 0x80ffffff;
 325                 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 326
 327                 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
 328                 t |= 0xa << 24;
 329                 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
 330
 331                 t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 332                 t |= BIT(31);
 333                 rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 334
 335                 msleep(50);
 336
 337                 rstctrl &= ~RT3883_RSTCTRL_PCIE;
 338                 rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 339         }
 340
 341         syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
 342
 343         clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
 344
 345         if (mode & RT3883_PCI_MODE_PCI) {
 346                 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
 347                 rstctrl &= ~RT3883_RSTCTRL_PCI;
 348         }
 349
 350         if (mode & RT3883_PCI_MODE_PCIE) {
 351                 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
 352                 rstctrl &= ~RT3883_RSTCTRL_PCIE;
 353         }
 354
 355         rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
 356         rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
 357         rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
 358
 359         msleep(500);
 360
 361         /*
 362          * setup the device number of the P2P bridge
 363          * and de-assert the reset line
 364          */
 365         t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
 366         rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
 367
 368         /* flush write */
 369         rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
 370         msleep(500);
 371
 372         if (mode & RT3883_PCI_MODE_PCIE) {
 373                 msleep(500);
 374
 375                 t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
 376
 377                 rpc->pcie_ready = t & BIT(0);
 378
 379                 if (!rpc->pcie_ready) {
 380                         /* reset the PCIe block */
 381                         t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
 382                         t |= RT3883_RSTCTRL_PCIE;
 383                         rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 384                         t &= ~RT3883_RSTCTRL_PCIE;
 385                         rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
 386
 387                         /* turn off PCIe clock */
 388                         t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
 389                         t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
 390                         rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
 391
 392                         t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
 393                         t &= ~0xf000c080;
 394                         rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
 395                 }
 396         }
 397
 398         /* enable PCI arbiter */
 399         rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
 400 }
 401
 402 static int rt3883_pci_probe(struct platform_device *pdev)
 403 {
 404         struct rt3883_pci_controller *rpc;
 405         struct device *dev = &pdev->dev;
 406         struct device_node *np = dev->of_node;
 407         struct device_node *child;
 408         u32 val;
 409         int err;
 410         int mode;
 411
 412         rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
 413         if (!rpc)
 414                 return -ENOMEM;
 415
 416         rpc->base = devm_platform_ioremap_resource(pdev, 0);
 417         if (IS_ERR(rpc->base))
 418                 return PTR_ERR(rpc->base);
 419
 420         /* find the interrupt controller child node */
 421         for_each_child_of_node(np, child) {
 422                 if (of_property_read_bool(child, "interrupt-controller")) {
 423                         rpc->intc_of_node = child;
 424                         break;
 425                 }
 426         }
 427
 428         if (!rpc->intc_of_node) {
 429                 dev_err(dev, "%pOF has no %s child node",
 430                         np, "interrupt controller");
 431                 return -EINVAL;
 432         }
 433
 434         /* find the PCI host bridge child node */
 435         for_each_child_of_node(np, child) {
 436                 if (of_node_is_type(child, "pci")) {
 437                         rpc->pci_controller.of_node = child;
 438                         break;
 439                 }
 440         }
 441
 442         if (!rpc->pci_controller.of_node) {
 443                 dev_err(dev, "%pOF has no %s child node",
 444                         np, "PCI host bridge");
 445                 err = -EINVAL;
 446                 goto err_put_intc_node;
 447         }
 448
 449         mode = RT3883_PCI_MODE_NONE;
 450         for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
 451                 int devfn;
 452
 453                 if (!of_node_is_type(child, "pci"))
 454                         continue;
 455
 456                 devfn = of_pci_get_devfn(child);
 457                 if (devfn < 0)
 458                         continue;
 459
 460                 switch (PCI_SLOT(devfn)) {
 461                 case 1:
 462                         mode |= RT3883_PCI_MODE_PCIE;
 463                         break;
 464
 465                 case 17:
 466                 case 18:
 467                         mode |= RT3883_PCI_MODE_PCI;
 468                         break;
 469                 }
 470         }
 471
 472         if (mode == RT3883_PCI_MODE_NONE) {
 473                 dev_err(dev, "unable to determine PCI mode\n");
 474                 err = -EINVAL;
 475                 goto err_put_hb_node;
 476         }
 477
 478         dev_info(dev, "mode:%s%s\n",
 479                  (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
 480                  (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
 481
 482         rt3883_pci_preinit(rpc, mode);
 483
 484         rpc->pci_controller.pci_ops = &rt3883_pci_ops;
 485         rpc->pci_controller.io_resource = &rpc->io_res;
 486         rpc->pci_controller.mem_resource = &rpc->mem_res;
 487
 488         /* Load PCI I/O and memory resources from DT */
 489         pci_load_of_ranges(&rpc->pci_controller,
 490                            rpc->pci_controller.of_node);
 491
 492         rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
 493         rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
 494
 495         ioport_resource.start = rpc->io_res.start;
 496         ioport_resource.end = rpc->io_res.end;
 497
 498         /* PCI */
 499         rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
 500         rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
 501         rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
 502         rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
 503         rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
 504
 505         /* PCIe */
 506         rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
 507         rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
 508         rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
 509         rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
 510         rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
 511
 512         err = rt3883_pci_irq_init(dev, rpc);
 513         if (err)
 514                 goto err_put_hb_node;
 515
 516         /* PCIe */
 517         val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
 518         val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 519         rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
 520
 521         /* PCI */
 522         val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
 523         val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 524         rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
 525
 526         if (mode == RT3883_PCI_MODE_PCIE) {
 527                 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
 528                 rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
 529
 530                 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 531                                        PCI_BASE_ADDRESS_0,
 532                                        RT3883_MEMORY_BASE);
 533                 /* flush write */
 534                 rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 535                                       PCI_BASE_ADDRESS_0);
 536         } else {
 537                 rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
 538                                        PCI_IO_BASE, 0x00000101);
 539         }
 540
 541         register_pci_controller(&rpc->pci_controller);
 542
 543         return 0;
 544
 545 err_put_hb_node:
 546         of_node_put(rpc->pci_controller.of_node);
 547 err_put_intc_node:
 548         of_node_put(rpc->intc_of_node);
 549         return err;
 550 }
 551
 552 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 553 {
 554         return of_irq_parse_and_map_pci(dev, slot, pin);
 555 }
 556
 557 int pcibios_plat_dev_init(struct pci_dev *dev)
 558 {
 559         return 0;
 560 }
 561
 562 static const struct of_device_id rt3883_pci_ids[] = {
 563         { .compatible = "ralink,rt3883-pci" },
 564         {},
 565 };
 566
 567 static struct platform_driver rt3883_pci_driver = {
 568         .probe = rt3883_pci_probe,
 569         .driver = {
 570                 .name = "rt3883-pci",
 571                 .of_match_table = of_match_ptr(rt3883_pci_ids),
 572         },
 573 };
 574
 575 static int __init rt3883_pci_init(void)
 576 {
 577         return platform_driver_register(&rt3883_pci_driver);
 578 }
 579
 580 postcore_initcall(rt3883_pci_init);