arch/mips/rb532/gpio.c

   1 /*
   2  *  Miscellaneous functions for IDT EB434 board
   3  *
   4  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   5  *  Copyright 2006 Phil Sutter <n0-1@freewrt.org>
   6  *  Copyright 2007 Florian Fainelli <florian@openwrt.org>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  14  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  15  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  16  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  17  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  18  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  19  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  21  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  22  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  *
  24  *  You should have received a copy of the  GNU General Public License along
  25  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  26  *  675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28
  29 #include <linux/kernel.h>
  30 #include <linux/init.h>
  31 #include <linux/types.h>
  32 #include <linux/export.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/gpio/driver.h>
  36
  37 #include <asm/mach-rc32434/rb.h>
  38 #include <asm/mach-rc32434/gpio.h>
  39
  40 #define GPIOBASE        0x050000
  41 /* Offsets relative to GPIOBASE */
  42 #define GPIOFUNC        0x00
  43 #define GPIOCFG         0x04
  44 #define GPIOD           0x08
  45 #define GPIOILEVEL      0x0C
  46 #define GPIOISTAT       0x10
  47 #define GPIONMIEN       0x14
  48 #define IMASK6          0x38
  49
  50 struct rb532_gpio_chip {
  51         struct gpio_chip chip;
  52         void __iomem     *regbase;
  53 };
  54
  55 static struct resource rb532_gpio_reg0_res[] = {
  56         {
  57                 .name   = "gpio_reg0",
  58                 .start  = REGBASE + GPIOBASE,
  59                 .end    = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
  60                 .flags  = IORESOURCE_MEM,
  61         }
  62 };
  63
  64 /* rb532_set_bit - sanely set a bit
  65  *
  66  * bitval: new value for the bit
  67  * offset: bit index in the 4 byte address range
  68  * ioaddr: 4 byte aligned address being altered
  69  */
  70 static inline void rb532_set_bit(unsigned bitval,
  71                 unsigned offset, void __iomem *ioaddr)
  72 {
  73         unsigned long flags;
  74         u32 val;
  75
  76         local_irq_save(flags);
  77
  78         val = readl(ioaddr);
  79         val &= ~(!bitval << offset);   /* unset bit if bitval == 0 */
  80         val |= (!!bitval << offset);   /* set bit if bitval == 1 */
  81         writel(val, ioaddr);
  82
  83         local_irq_restore(flags);
  84 }
  85
  86 /* rb532_get_bit - read a bit
  87  *
  88  * returns the boolean state of the bit, which may be > 1
  89  */
  90 static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
  91 {
  92         return readl(ioaddr) & (1 << offset);
  93 }
  94
  95 /*
  96  * Return GPIO level */
  97 static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
  98 {
  99         struct rb532_gpio_chip  *gpch;
 100
 101         gpch = gpiochip_get_data(chip);
 102         return !!rb532_get_bit(offset, gpch->regbase + GPIOD);
 103 }
 104
 105 /*
 106  * Set output GPIO level
 107  */
 108 static void rb532_gpio_set(struct gpio_chip *chip,
 109                                 unsigned offset, int value)
 110 {
 111         struct rb532_gpio_chip  *gpch;
 112
 113         gpch = gpiochip_get_data(chip);
 114         rb532_set_bit(value, offset, gpch->regbase + GPIOD);
 115 }
 116
 117 /*
 118  * Set GPIO direction to input
 119  */
 120 static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 121 {
 122         struct rb532_gpio_chip  *gpch;
 123
 124         gpch = gpiochip_get_data(chip);
 125
 126         /* disable alternate function in case it's set */
 127         rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
 128
 129         rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
 130         return 0;
 131 }
 132
 133 /*
 134  * Set GPIO direction to output
 135  */
 136 static int rb532_gpio_direction_output(struct gpio_chip *chip,
 137                                         unsigned offset, int value)
 138 {
 139         struct rb532_gpio_chip  *gpch;
 140
 141         gpch = gpiochip_get_data(chip);
 142
 143         /* disable alternate function in case it's set */
 144         rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
 145
 146         /* set the initial output value */
 147         rb532_set_bit(value, offset, gpch->regbase + GPIOD);
 148
 149         rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
 150         return 0;
 151 }
 152
 153 static int rb532_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
 154 {
 155         return 8 + 4 * 32 + gpio;
 156 }
 157
 158 static struct rb532_gpio_chip rb532_gpio_chip[] = {
 159         [0] = {
 160                 .chip = {
 161                         .label                  = "gpio0",
 162                         .direction_input        = rb532_gpio_direction_input,
 163                         .direction_output       = rb532_gpio_direction_output,
 164                         .get                    = rb532_gpio_get,
 165                         .set                    = rb532_gpio_set,
 166                         .to_irq                 = rb532_gpio_to_irq,
 167                         .base                   = 0,
 168                         .ngpio                  = 32,
 169                 },
 170         },
 171 };
 172
 173 /*
 174  * Set GPIO interrupt level
 175  */
 176 void rb532_gpio_set_ilevel(int bit, unsigned gpio)
 177 {
 178         rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
 179 }
 180 EXPORT_SYMBOL(rb532_gpio_set_ilevel);
 181
 182 /*
 183  * Set GPIO interrupt status
 184  */
 185 void rb532_gpio_set_istat(int bit, unsigned gpio)
 186 {
 187         rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
 188 }
 189 EXPORT_SYMBOL(rb532_gpio_set_istat);
 190
 191 /*
 192  * Configure GPIO alternate function
 193  */
 194 void rb532_gpio_set_func(unsigned gpio)
 195 {
 196        rb532_set_bit(1, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
 197 }
 198 EXPORT_SYMBOL(rb532_gpio_set_func);
 199
 200 static int __init rb532_gpio_init(void)
 201 {
 202         struct resource *r;
 203
 204         r = rb532_gpio_reg0_res;
 205         rb532_gpio_chip->regbase = ioremap(r->start, resource_size(r));
 206
 207         if (!rb532_gpio_chip->regbase) {
 208                 printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
 209                 return -ENXIO;
 210         }
 211
 212         /* Register our GPIO chip */
 213         gpiochip_add_data(&rb532_gpio_chip->chip, rb532_gpio_chip);
 214
 215         return 0;
 216 }
 217 arch_initcall(rb532_gpio_init);