1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Kernel execution entry point code.
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
6 * Initial PowerPC version.
7 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
10 * Low-level exception handers, MMU support, and rewrite.
11 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
12 * PowerPC 8xx modifications.
13 * Copyright (c) 1998-1999 TiVo, Inc.
14 * PowerPC 403GCX modifications.
15 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
16 * PowerPC 403GCX/405GP modifications.
17 * Copyright 2000 MontaVista Software Inc.
18 * PPC405 modifications
19 * PowerPC 403GCX/405GP modifications.
20 * Author: MontaVista Software, Inc.
21 * frank_rowand@mvista.com or source@mvista.com
22 * debbie_chu@mvista.com
23 * Copyright 2002-2004 MontaVista Software, Inc.
24 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
25 * Copyright 2004 Freescale Semiconductor, Inc
26 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
29 #include <linux/init.h>
30 #include <linux/threads.h>
31 #include <linux/pgtable.h>
32 #include <linux/linkage.h>
34 #include <asm/processor.h>
37 #include <asm/cputable.h>
38 #include <asm/thread_info.h>
39 #include <asm/ppc_asm.h>
40 #include <asm/asm-offsets.h>
41 #include <asm/cache.h>
42 #include <asm/ptrace.h>
43 #include <asm/feature-fixups.h>
44 #include "head_booke.h"
46 /* As with the other PowerPC ports, it is expected that when code
47 * execution begins here, the following registers contain valid, yet
48 * optional, information:
50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
51 * r4 - Starting address of the init RAM disk
52 * r5 - Ending address of the init RAM disk
53 * r6 - Start of kernel command line string (e.g. "mem=128")
54 * r7 - End of kernel command line string
61 * Reserve a word at a fixed location to store the address
66 /* Translate device tree address to physical, save in r30/r31 */
71 li r25,0 /* phys kernel start (low) */
72 li r24,0 /* CPU number */
73 li r23,0 /* phys kernel start (high) */
75 #ifdef CONFIG_RELOCATABLE
76 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
78 /* Translate _stext address to physical, save in r23/r25 */
85 addis r3,r8,(is_second_reloc - 0b)@ha
86 lwz r19,(is_second_reloc - 0b)@l(r3)
88 /* Check if this is the second relocation. */
93 * For the second relocation, we already get the real memstart_addr
94 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
95 * then the virtual address of start kernel should be:
96 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
97 * Since the offset between kernstart_addr and memstart_addr should
98 * never be beyond 1G, so we can just use the lower 32bit of them
99 * for the calculation.
103 addis r4,r8,(kernstart_addr - 0b)@ha
104 addi r4,r4,(kernstart_addr - 0b)@l
107 addis r6,r8,(memstart_addr - 0b)@ha
108 addi r6,r6,(memstart_addr - 0b)@l
117 * We have the runtime (virtual) address of our base.
118 * We calculate our shift of offset from a 64M page.
119 * We could map the 64M page we belong to at PAGE_OFFSET and
120 * get going from there.
123 ori r4,r4,KERNELBASE@l
124 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
125 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
126 subf r3,r5,r6 /* r3 = r6 - r5 */
127 add r3,r4,r3 /* Required Virtual Address */
132 * For the second relocation, we already set the right tlb entries
133 * for the kernel space, so skip the code in 85xx_entry_mapping.S
139 /* We try to not make any assumptions about how the boot loader
140 * setup or used the TLBs. We invalidate all mappings from the
141 * boot loader and load a single entry in TLB1[0] to map the
142 * first 64M of kernel memory. Any boot info passed from the
143 * bootloader needs to live in this first 64M.
145 * Requirement on bootloader:
146 * - The page we're executing in needs to reside in TLB1 and
147 * have IPROT=1. If not an invalidate broadcast could
148 * evict the entry we're currently executing in.
150 * r3 = Index of TLB1 were executing in
151 * r4 = Current MSR[IS]
152 * r5 = Index of TLB1 temp mapping
154 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
158 _GLOBAL(__early_start)
159 LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr)
162 #define ENTRY_MAPPING_BOOT_SETUP
163 #include "85xx_entry_mapping.S"
164 #undef ENTRY_MAPPING_BOOT_SETUP
167 /* Establish the interrupt vector offsets */
168 SET_IVOR(0, CriticalInput);
169 SET_IVOR(1, MachineCheck);
170 SET_IVOR(2, DataStorage);
171 SET_IVOR(3, InstructionStorage);
172 SET_IVOR(4, ExternalInput);
173 SET_IVOR(5, Alignment);
174 SET_IVOR(6, Program);
175 SET_IVOR(7, FloatingPointUnavailable);
176 SET_IVOR(8, SystemCall);
177 SET_IVOR(9, AuxillaryProcessorUnavailable);
178 SET_IVOR(10, Decrementer);
179 SET_IVOR(11, FixedIntervalTimer);
180 SET_IVOR(12, WatchdogTimer);
181 SET_IVOR(13, DataTLBError);
182 SET_IVOR(14, InstructionTLBError);
183 SET_IVOR(15, DebugCrit);
185 /* Establish the interrupt vector base */
186 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
189 /* Setup the defaults for TLB entries */
190 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
193 #if !defined(CONFIG_BDI_SWITCH)
195 * The Abatron BDI JTAG debugger does not tolerate others
196 * mucking with the debug registers.
201 /* clear any residual debug events */
207 /* Check to see if we're the second processor, and jump
208 * to the secondary_start code if so
210 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
214 bne __secondary_start
218 * This is where the main kernel code starts.
223 ori r2,r2,init_task@l
225 /* ptr to current thread */
226 addi r4,r2,THREAD /* init task's THREAD */
227 mtspr SPRN_SPRG_THREAD,r4
230 lis r1,init_thread_union@h
231 ori r1,r1,init_thread_union@l
233 stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1)
236 stw r24, TASK_CPU(r2)
244 #ifdef CONFIG_RELOCATABLE
247 #ifdef CONFIG_PHYS_64BIT
256 #ifdef CONFIG_DYNAMIC_MEMSTART
257 lis r3,kernstart_addr@ha
258 la r3,kernstart_addr@l(r3)
259 #ifdef CONFIG_PHYS_64BIT
268 * Decide what sort of machine this is and initialize the MMU.
275 /* Setup PTE pointers for the Abatron bdiGDB */
276 lis r6, swapper_pg_dir@h
277 ori r6, r6, swapper_pg_dir@l
278 lis r5, abatron_pteptrs@h
279 ori r5, r5, abatron_pteptrs@l
280 lis r3, kernstart_virt_addr@ha
281 lwz r4, kernstart_virt_addr@l(r3)
282 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
286 lis r4,start_kernel@h
287 ori r4,r4,start_kernel@l
289 ori r3,r3,MSR_KERNEL@l
292 rfi /* change context and jump to start_kernel */
294 /* Macros to hide the PTE size differences
296 * FIND_PTE -- walks the page tables given EA & pgdir pointer
298 * r11 -- PGDIR pointer
301 * label 2: is the bailout case
303 * if we find the pte (fall through):
304 * r11 is low pte word
305 * r12 is pointer to the pte
306 * r10 is the pshift from the PGD, if we're a hugepage
308 #ifdef CONFIG_PTE_64BIT
309 #ifdef CONFIG_HUGETLB_PAGE
311 rlwinm r12, r13, 14, 18, 28; /* Compute pgdir/pmd offset */ \
313 lwz r11, 4(r12); /* Get pgd/pmd entry */ \
314 rlwinm. r10, r11, 32 - _PAGE_PSIZE_SHIFT, 0x1e; /* get tsize*/ \
315 bne 1000f; /* Huge page (leaf entry) */ \
316 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
317 beq 2f; /* Bail if no table */ \
318 rlwimi r12, r13, 23, 20, 28; /* Compute pte address */ \
319 li r10, 0; /* clear r10 */ \
320 lwz r11, 4(r12); /* Get pte entry */ \
324 rlwinm r12, r13, 14, 18, 28; /* Compute pgdir/pmd offset */ \
326 lwz r11, 4(r12); /* Get pgd/pmd entry */ \
327 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
328 beq 2f; /* Bail if no table */ \
329 rlwimi r12, r13, 23, 20, 28; /* Compute pte address */ \
330 lwz r11, 4(r12); /* Get pte entry */
331 #endif /* HUGEPAGE */
332 #else /* !PTE_64BIT */
334 rlwimi r11, r13, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
335 lwz r11, 0(r11); /* Get L1 entry */ \
336 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
337 beq 2f; /* Bail if no table */ \
338 rlwimi r12, r13, 22, 20, 29; /* Compute PTE address */ \
339 lwz r11, 0(r12); /* Get Linux PTE */
343 * Interrupt vector entry code
345 * The Book E MMUs are always on so we don't need to handle
346 * interrupts in real mode as with previous PPC processors. In
347 * this case we handle interrupts in the kernel virtual address
350 * Interrupt vectors are dynamically placed relative to the
351 * interrupt prefix as determined by the address of interrupt_base.
352 * The interrupt vectors offsets are programmed using the labels
353 * for each interrupt vector entry.
355 * Interrupt vectors must be aligned on a 16 byte boundary.
356 * We align on a 32 byte cache line boundary for good measure.
360 /* Critical Input Interrupt */
361 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
363 /* Machine Check Interrupt */
364 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
366 /* Data Storage Interrupt */
367 START_EXCEPTION(DataStorage)
368 NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE)
369 mfspr r5,SPRN_ESR /* Grab the ESR, save it */
371 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it */
373 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
375 prepare_transfer_to_handler
379 prepare_transfer_to_handler
380 bl CacheLockingException
383 /* Instruction Storage Interrupt */
384 INSTRUCTION_STORAGE_EXCEPTION
386 /* External Input Interrupt */
387 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ)
389 /* Alignment Interrupt */
392 /* Program Interrupt */
395 /* Floating Point Unavailable Interrupt */
396 #ifdef CONFIG_PPC_FPU
397 FP_UNAVAILABLE_EXCEPTION
399 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, emulation_assist_interrupt)
402 /* System Call Interrupt */
403 START_EXCEPTION(SystemCall)
404 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1
406 /* Auxiliary Processor Unavailable Interrupt */
407 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, unknown_exception)
409 /* Decrementer Interrupt */
410 DECREMENTER_EXCEPTION
412 /* Fixed Internal Timer Interrupt */
413 /* TODO: Add FIT support */
414 EXCEPTION(0x3100, FIT, FixedIntervalTimer, unknown_exception)
416 /* Watchdog Timer Interrupt */
417 #ifdef CONFIG_BOOKE_WDT
418 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
420 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
423 /* Data TLB Error Interrupt */
424 START_EXCEPTION(DataTLBError)
425 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
426 mfspr r10, SPRN_SPRG_THREAD
427 stw r11, THREAD_NORMSAVE(0)(r10)
428 #ifdef CONFIG_KVM_BOOKE_HV
431 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
433 stw r12, THREAD_NORMSAVE(1)(r10)
434 stw r13, THREAD_NORMSAVE(2)(r10)
436 stw r13, THREAD_NORMSAVE(3)(r10)
437 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
438 START_BTB_FLUSH_SECTION
444 END_BTB_FLUSH_SECTION
445 mfspr r13, SPRN_DEAR /* Get faulting address */
447 /* If we are faulting a kernel address, we have to use the
448 * kernel page tables.
450 lis r11, PAGE_OFFSET@h
453 lis r11, swapper_pg_dir@h
454 ori r11, r11, swapper_pg_dir@l
456 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
457 rlwinm r12,r12,0,16,1
462 /* Get the PGD for the current thread */
464 mfspr r11,SPRN_SPRG_THREAD
467 #ifdef CONFIG_PPC_KUAP
469 rlwinm. r12,r12,0,0x3fff0000
470 beq 2f /* KUAP fault */
476 #ifdef CONFIG_PTE_64BIT
477 li r13,_PAGE_PRESENT|_PAGE_BAP_SR
478 oris r13,r13,_PAGE_ACCESSED@h
480 li r13,_PAGE_PRESENT|_PAGE_READ|_PAGE_ACCESSED
482 andc. r13,r13,r11 /* Check permission */
484 #ifdef CONFIG_PTE_64BIT
486 subf r13,r11,r12 /* create false data dep */
487 lwzx r13,r11,r13 /* Get upper pte bits */
489 lwz r13,0(r12) /* Get upper pte bits */
493 bne 2f /* Bail if permission/valid mismatch */
495 /* Jump to common tlb load */
498 /* The bailout. Restore registers to pre-exception conditions
499 * and call the heavyweights to help us out.
501 mfspr r10, SPRN_SPRG_THREAD
502 lwz r11, THREAD_NORMSAVE(3)(r10)
504 lwz r13, THREAD_NORMSAVE(2)(r10)
505 lwz r12, THREAD_NORMSAVE(1)(r10)
506 lwz r11, THREAD_NORMSAVE(0)(r10)
507 mfspr r10, SPRN_SPRG_RSCRATCH0
510 /* Instruction TLB Error Interrupt */
512 * Nearly the same as above, except we get our
513 * information from different registers and bailout
514 * to a different point.
516 START_EXCEPTION(InstructionTLBError)
517 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
518 mfspr r10, SPRN_SPRG_THREAD
519 stw r11, THREAD_NORMSAVE(0)(r10)
520 #ifdef CONFIG_KVM_BOOKE_HV
523 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
525 stw r12, THREAD_NORMSAVE(1)(r10)
526 stw r13, THREAD_NORMSAVE(2)(r10)
528 stw r13, THREAD_NORMSAVE(3)(r10)
529 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
530 START_BTB_FLUSH_SECTION
536 END_BTB_FLUSH_SECTION
538 mfspr r13, SPRN_SRR0 /* Get faulting address */
540 /* If we are faulting a kernel address, we have to use the
541 * kernel page tables.
543 lis r11, PAGE_OFFSET@h
546 lis r11, swapper_pg_dir@h
547 ori r11, r11, swapper_pg_dir@l
549 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
550 rlwinm r12,r12,0,16,1
554 /* Make up the required permissions for kernel code */
555 #ifdef CONFIG_PTE_64BIT
556 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
557 oris r13,r13,_PAGE_ACCESSED@h
559 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
563 /* Get the PGD for the current thread */
565 mfspr r11,SPRN_SPRG_THREAD
568 #ifdef CONFIG_PPC_KUAP
570 rlwinm. r12,r12,0,0x3fff0000
571 beq 2f /* KUAP fault */
575 /* Make up the required permissions for user code */
576 #ifdef CONFIG_PTE_64BIT
577 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
578 oris r13,r13,_PAGE_ACCESSED@h
580 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
584 andc. r13,r13,r11 /* Check permission */
586 #ifdef CONFIG_PTE_64BIT
588 subf r13,r11,r12 /* create false data dep */
589 lwzx r13,r11,r13 /* Get upper pte bits */
591 lwz r13,0(r12) /* Get upper pte bits */
595 bne 2f /* Bail if permission mismatch */
597 /* Jump to common TLB load point */
601 /* The bailout. Restore registers to pre-exception conditions
602 * and call the heavyweights to help us out.
604 mfspr r10, SPRN_SPRG_THREAD
605 lwz r11, THREAD_NORMSAVE(3)(r10)
607 lwz r13, THREAD_NORMSAVE(2)(r10)
608 lwz r12, THREAD_NORMSAVE(1)(r10)
609 lwz r11, THREAD_NORMSAVE(0)(r10)
610 mfspr r10, SPRN_SPRG_RSCRATCH0
613 /* Define SPE handlers for e500v2 */
615 /* SPE Unavailable */
616 START_EXCEPTION(SPEUnavailable)
617 NORMAL_EXCEPTION_PROLOG(0x2010, SPE_UNAVAIL)
620 b fast_exception_return
621 1: prepare_transfer_to_handler
624 #elif defined(CONFIG_SPE_POSSIBLE)
625 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, unknown_exception)
626 #endif /* CONFIG_SPE_POSSIBLE */
628 /* SPE Floating Point Data */
630 START_EXCEPTION(SPEFloatingPointData)
631 NORMAL_EXCEPTION_PROLOG(0x2030, SPE_FP_DATA)
632 prepare_transfer_to_handler
633 bl SPEFloatingPointException
637 /* SPE Floating Point Round */
638 START_EXCEPTION(SPEFloatingPointRound)
639 NORMAL_EXCEPTION_PROLOG(0x2050, SPE_FP_ROUND)
640 prepare_transfer_to_handler
641 bl SPEFloatingPointRoundException
644 #elif defined(CONFIG_SPE_POSSIBLE)
645 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, unknown_exception)
646 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, unknown_exception)
647 #endif /* CONFIG_SPE_POSSIBLE */
650 /* Performance Monitor */
651 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
652 performance_monitor_exception)
654 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception)
656 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
657 CriticalDoorbell, unknown_exception)
659 /* Debug Interrupt */
660 DEBUG_DEBUG_EXCEPTION
663 GUEST_DOORBELL_EXCEPTION
665 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
669 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception)
671 /* Embedded Hypervisor Privilege */
672 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception)
681 * Both the instruction and data TLB miss get to this
682 * point to load the TLB.
683 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
684 * r11 - TLB (info from Linux PTE)
685 * r12 - available to use
686 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
687 * CR5 - results of addr >= PAGE_OFFSET
688 * MAS0, MAS1 - loaded with proper value when we get here
689 * MAS2, MAS3 - will need additional info from Linux PTE
690 * Upon exit, we reload everything and RFI.
693 #ifdef CONFIG_HUGETLB_PAGE
694 cmpwi 6, r10, 0 /* check for huge page */
695 beq 6, finish_tlb_load_cont /* !huge */
697 /* Alas, we need more scratch registers for hugepages */
698 mfspr r12, SPRN_SPRG_THREAD
699 stw r14, THREAD_NORMSAVE(4)(r12)
700 stw r15, THREAD_NORMSAVE(5)(r12)
701 stw r16, THREAD_NORMSAVE(6)(r12)
702 stw r17, THREAD_NORMSAVE(7)(r12)
704 /* Get the next_tlbcam_idx percpu var */
706 lwz r15, TASK_CPU-THREAD(r12)
707 lis r14, __per_cpu_offset@h
708 ori r14, r14, __per_cpu_offset@l
709 rlwinm r15, r15, 2, 0, 29
714 lis r17, next_tlbcam_idx@h
715 ori r17, r17, next_tlbcam_idx@l
716 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
717 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
719 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
720 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
723 /* Extract TLB1CFG(NENTRY) */
724 mfspr r16, SPRN_TLB1CFG
725 andi. r16, r16, 0xfff
727 /* Update next_tlbcam_idx, wrapping when necessary */
731 lis r14, tlbcam_index@h
732 ori r14, r14, tlbcam_index@l
737 rlwimi r16, r10, MAS1_TSIZE_SHIFT, MAS1_TSIZE_MASK
740 /* copy the pshift for use later */
741 addi r14, r10, _PAGE_PSIZE_SHIFT_OFFSET
745 #endif /* CONFIG_HUGETLB_PAGE */
748 * We set execute, because we don't have the granularity to
749 * properly set this at the page level (Linux problem).
750 * Many of these bits are software only. Bits we don't set
751 * here we (properly should) assume have the appropriate value.
753 finish_tlb_load_cont:
754 #ifdef CONFIG_PTE_64BIT
755 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
756 andi. r10, r11, _PAGE_DIRTY
758 li r10, MAS3_SW | MAS3_UW
760 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
761 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
762 2: mtspr SPRN_MAS3, r12
763 BEGIN_MMU_FTR_SECTION
764 srwi r10, r13, 12 /* grab RPN[12:31] */
766 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
768 li r10, (_PAGE_EXEC | _PAGE_READ)
770 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
772 mcrf cr0, cr5 /* Test for user page */
775 rlwinm r10, r10, 0, ~_PAGE_EXEC /* Clear SX on user pages */
777 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
782 #ifdef CONFIG_PTE_64BIT
783 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
785 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
787 #ifdef CONFIG_HUGETLB_PAGE
788 beq 6, 3f /* don't mask if page isn't huge */
792 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
793 andc r12, r12, r13 /* mask off ea bits within the page */
795 3: mtspr SPRN_MAS2, r12
800 /* Done...restore registers and get out of here. */
801 mfspr r10, SPRN_SPRG_THREAD
802 #ifdef CONFIG_HUGETLB_PAGE
803 beq 6, 8f /* skip restore for 4k page faults */
804 lwz r14, THREAD_NORMSAVE(4)(r10)
805 lwz r15, THREAD_NORMSAVE(5)(r10)
806 lwz r16, THREAD_NORMSAVE(6)(r10)
807 lwz r17, THREAD_NORMSAVE(7)(r10)
809 8: lwz r11, THREAD_NORMSAVE(3)(r10)
811 lwz r13, THREAD_NORMSAVE(2)(r10)
812 lwz r12, THREAD_NORMSAVE(1)(r10)
813 lwz r11, THREAD_NORMSAVE(0)(r10)
814 mfspr r10, SPRN_SPRG_RSCRATCH0
815 rfi /* Force context change */
818 /* Note that the SPE support is closely modeled after the AltiVec
819 * support. Changes to one are likely to be applicable to the
823 * Disable SPE for the task which had SPE previously,
824 * and save its SPE registers in its thread_struct.
825 * Enables SPE for use in the kernel on return.
826 * On SMP we know the SPE units are free, since we give it up every
831 mtmsr r5 /* enable use of SPE now */
833 /* enable use of SPE after return */
835 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
838 stw r4,THREAD_USED_SPE(r5)
841 REST_32EVRS(0,r10,r5,THREAD_EVR0)
845 * SPE unavailable trap from kernel - print a message, but let
846 * the task use SPE in the kernel until it returns to user mode.
848 SYM_FUNC_START_LOCAL(KernelSPE)
851 stw r3,_MSR(r1) /* enable use of SPE after return */
855 mr r4,r2 /* current */
861 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
865 SYM_FUNC_END(KernelSPE)
866 #endif /* CONFIG_SPE */
869 * Translate the effec addr in r3 to phys addr. The phys addr will be put
870 * into r3(higher 32bit) and r4(lower 32bit)
872 SYM_FUNC_START_LOCAL(get_phys_addr)
875 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
876 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
879 tlbsx 0,r3 /* must succeed */
883 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
885 slw r10,r10,r9 /* r10 = page size */
887 and r11,r3,r10 /* r11 = page offset */
888 andc r4,r12,r10 /* r4 = page base */
889 or r4,r4,r11 /* r4 = devtree phys addr */
890 #ifdef CONFIG_PHYS_64BIT
894 SYM_FUNC_END(get_phys_addr)
900 #ifdef CONFIG_PPC_E500
901 #ifndef CONFIG_PPC_E500MC
902 /* Adjust or setup IVORs for e500v1/v2 */
903 _GLOBAL(__setup_e500_ivors)
906 li r3,SPEUnavailable@l
908 li r3,SPEFloatingPointData@l
910 li r3,SPEFloatingPointRound@l
912 li r3,PerformanceMonitor@l
917 /* Adjust or setup IVORs for e500mc */
918 _GLOBAL(__setup_e500mc_ivors)
921 li r3,PerformanceMonitor@l
925 li r3,CriticalDoorbell@l
930 /* setup ehv ivors for */
931 _GLOBAL(__setup_ehv_ivors)
932 li r3,GuestDoorbell@l
934 li r3,CriticalGuestDoorbell@l
942 #endif /* CONFIG_PPC_E500MC */
943 #endif /* CONFIG_PPC_E500 */
947 * extern void __giveup_spe(struct task_struct *prev)
950 _GLOBAL(__giveup_spe)
951 addi r3,r3,THREAD /* want THREAD of task */
954 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
955 evxor evr6, evr6, evr6 /* clear out evr6 */
956 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
958 evstddx evr6, r4, r3 /* save off accumulator */
960 lwz r4,_MSR-STACK_INT_FRAME_REGS(r5)
962 andc r4,r4,r3 /* disable SPE for previous task */
963 stw r4,_MSR-STACK_INT_FRAME_REGS(r5)
966 #endif /* CONFIG_SPE */
969 * extern void abort(void)
971 * At present, this routine just applies a system reset.
975 mtspr SPRN_DBCR0,r13 /* disable all debug events */
978 ori r13,r13,MSR_DE@l /* Enable Debug Events */
982 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
987 /* When we get here, r24 needs to hold the CPU # */
988 .globl __secondary_start
990 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
993 li r26,0 /* r26 safe? */
996 mr r27,r3 /* tlb entry */
997 /* Load each CAM entry */
1002 mr r3,r27 /* tlb entry */
1003 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1005 mr r5,r25 /* phys kernel start */
1006 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1007 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1009 ori r7,r7,KERNELBASE@l
1010 cmpw r20,r7 /* if kernstart_virt_addr != KERNELBASE, randomized */
1013 2: li r5,0 /* no device tree */
1014 li r6,0 /* not boot cpu */
1018 lis r3,__secondary_hold_acknowledge@h
1019 ori r3,r3,__secondary_hold_acknowledge@l
1023 mr r4,r24 /* Why? */
1026 /* get current's stack and current */
1027 lis r2,secondary_current@ha
1028 lwz r2,secondary_current@l(r2)
1029 lwz r1,TASK_STACK(r2)
1032 addi r1,r1,THREAD_SIZE-STACK_FRAME_MIN_SIZE
1036 /* ptr to current thread */
1037 addi r4,r2,THREAD /* address of our thread_struct */
1038 mtspr SPRN_SPRG_THREAD,r4
1040 /* Setup the defaults for TLB entries */
1041 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1044 /* Jump to start_secondary */
1046 ori r4,r4,MSR_KERNEL@l
1047 lis r3,start_secondary@h
1048 ori r3,r3,start_secondary@l
1055 .globl __secondary_hold_acknowledge
1056 __secondary_hold_acknowledge:
1061 * Create a 64M tlb by address and entry
1063 * r4 - virtual address
1064 * r5/r6 - physical address
1066 _GLOBAL(create_kaslr_tlb_entry)
1067 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
1068 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
1069 mtspr SPRN_MAS0,r7 /* Write MAS0 */
1071 lis r3,(MAS1_VALID|MAS1_IPROT)@h
1072 ori r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
1073 mtspr SPRN_MAS1,r3 /* Write MAS1 */
1075 lis r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h
1076 ori r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l
1078 ori r3,r3,MAS2_M_IF_NEEDED@l
1079 mtspr SPRN_MAS2,r3 /* Write MAS2(EPN) */
1081 #ifdef CONFIG_PHYS_64BIT
1082 ori r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX)
1083 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
1086 ori r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX)
1087 mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */
1090 tlbwe /* Write TLB */
1096 * Return to the start of the relocated kernel and run again
1097 * r3 - virtual address of fdt
1098 * r4 - entry of the kernel
1100 _GLOBAL(reloc_kernel_entry)
1102 rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS)
1109 * Create a tlb entry with the same effective and physical address as
1110 * the tlb entry used by the current running code. But set the TS to 1.
1111 * Then switch to the address space 1. It will return with the r3 set to
1112 * the ESEL of the new created tlb.
1114 _GLOBAL(switch_to_as1)
1117 /* Find a entry not used */
1118 mfspr r3,SPRN_TLB1CFG
1121 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1123 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1125 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1129 andis. r4,r4,MAS1_VALID@h
1132 /* Get the tlb entry used by the current running code */
1138 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1142 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1143 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1150 ori r4,r4,MSR_IS | MSR_DS
1157 * Restore to the address space 0 and also invalidate the tlb entry created
1159 * r3 - the tlb entry which should be invalidated
1160 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1161 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1164 _GLOBAL(restore_to_as0)
1172 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1173 * so we need calculate the right jump and device tree address based
1174 * on the offset passed by r4.
1181 li r8,(MSR_IS | MSR_DS)
1189 /* Invalidate the temporary tlb entry for AS1 */
1190 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1191 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1195 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1203 bne 3f /* offset != 0 && is_boot_cpu */
1208 * The PAGE_OFFSET will map to a different physical address,
1209 * jump to _start to do another relocation again.