arch/powerpc/platforms/cell/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  linux/arch/powerpc/platforms/cell/cell_setup.c
   4  *
   5  *  Copyright (C) 1995  Linus Torvalds
   6  *  Adapted from 'alpha' version by Gary Thomas
   7  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   8  *  Modified by PPC64 Team, IBM Corp
   9  *  Modified by Cell Team, IBM Deutschland Entwicklung GmbH
  10  */
  11 #undef DEBUG
  12
  13 #include <linux/sched.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mm.h>
  16 #include <linux/stddef.h>
  17 #include <linux/export.h>
  18 #include <linux/unistd.h>
  19 #include <linux/user.h>
  20 #include <linux/reboot.h>
  21 #include <linux/init.h>
  22 #include <linux/delay.h>
  23 #include <linux/irq.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/root_dev.h>
  26 #include <linux/console.h>
  27 #include <linux/mutex.h>
  28 #include <linux/memory_hotplug.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/platform_device.h>
  31
  32 #include <asm/mmu.h>
  33 #include <asm/processor.h>
  34 #include <asm/io.h>
  35 #include <asm/rtas.h>
  36 #include <asm/pci-bridge.h>
  37 #include <asm/iommu.h>
  38 #include <asm/dma.h>
  39 #include <asm/machdep.h>
  40 #include <asm/time.h>
  41 #include <asm/nvram.h>
  42 #include <asm/cputable.h>
  43 #include <asm/ppc-pci.h>
  44 #include <asm/irq.h>
  45 #include <asm/spu.h>
  46 #include <asm/spu_priv1.h>
  47 #include <asm/udbg.h>
  48 #include <asm/mpic.h>
  49 #include <asm/cell-regs.h>
  50 #include <asm/io-workarounds.h>
  51
  52 #include "cell.h"
  53 #include "interrupt.h"
  54 #include "pervasive.h"
  55 #include "ras.h"
  56
  57 #ifdef DEBUG
  58 #define DBG(fmt...) udbg_printf(fmt)
  59 #else
  60 #define DBG(fmt...)
  61 #endif
  62
  63 static void cell_show_cpuinfo(struct seq_file *m)
  64 {
  65         struct device_node *root;
  66         const char *model = "";
  67
  68         root = of_find_node_by_path("/");
  69         if (root)
  70                 model = of_get_property(root, "model", NULL);
  71         seq_printf(m, "machine\t\t: CHRP %s\n", model);
  72         of_node_put(root);
  73 }
  74
  75 static void cell_progress(char *s, unsigned short hex)
  76 {
  77         printk("*** %04x : %s\n", hex, s ? s : "");
  78 }
  79
  80 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
  81 {
  82         struct pci_controller *hose;
  83         const char *s;
  84         int i;
  85
  86         if (!machine_is(cell))
  87                 return;
  88
  89         /* We're searching for a direct child of the PHB */
  90         if (dev->bus->self != NULL || dev->devfn != 0)
  91                 return;
  92
  93         hose = pci_bus_to_host(dev->bus);
  94         if (hose == NULL)
  95                 return;
  96
  97         /* Only on PCIE */
  98         if (!of_device_is_compatible(hose->dn, "pciex"))
  99                 return;
 100
 101         /* And only on axon */
 102         s = of_get_property(hose->dn, "model", NULL);
 103         if (!s || strcmp(s, "Axon") != 0)
 104                 return;
 105
 106         for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
 107                 dev->resource[i].start = dev->resource[i].end = 0;
 108                 dev->resource[i].flags = 0;
 109         }
 110
 111         printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
 112                pci_name(dev));
 113 }
 114 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
 115
 116 static int cell_setup_phb(struct pci_controller *phb)
 117 {
 118         const char *model;
 119         struct device_node *np;
 120
 121         int rc = rtas_setup_phb(phb);
 122         if (rc)
 123                 return rc;
 124
 125         phb->controller_ops = cell_pci_controller_ops;
 126
 127         np = phb->dn;
 128         model = of_get_property(np, "model", NULL);
 129         if (model == NULL || !of_node_name_eq(np, "pci"))
 130                 return 0;
 131
 132         /* Setup workarounds for spider */
 133         if (strcmp(model, "Spider"))
 134                 return 0;
 135
 136         iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
 137                                   (void *)SPIDER_PCI_REG_BASE);
 138         return 0;
 139 }
 140
 141 static const struct of_device_id cell_bus_ids[] __initconst = {
 142         { .type = "soc", },
 143         { .compatible = "soc", },
 144         { .type = "spider", },
 145         { .type = "axon", },
 146         { .type = "plb5", },
 147         { .type = "plb4", },
 148         { .type = "opb", },
 149         { .type = "ebc", },
 150         {},
 151 };
 152
 153 static int __init cell_publish_devices(void)
 154 {
 155         struct device_node *root = of_find_node_by_path("/");
 156         struct device_node *np;
 157         int node;
 158
 159         /* Publish OF platform devices for southbridge IOs */
 160         of_platform_bus_probe(NULL, cell_bus_ids, NULL);
 161
 162         /* On spider based blades, we need to manually create the OF
 163          * platform devices for the PCI host bridges
 164          */
 165         for_each_child_of_node(root, np) {
 166                 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex"))
 167                         continue;
 168                 of_platform_device_create(np, NULL, NULL);
 169         }
 170
 171         of_node_put(root);
 172
 173         /* There is no device for the MIC memory controller, thus we create
 174          * a platform device for it to attach the EDAC driver to.
 175          */
 176         for_each_online_node(node) {
 177                 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
 178                         continue;
 179                 platform_device_register_simple("cbe-mic", node, NULL, 0);
 180         }
 181
 182         return 0;
 183 }
 184 machine_subsys_initcall(cell, cell_publish_devices);
 185
 186 static void __init mpic_init_IRQ(void)
 187 {
 188         struct device_node *dn;
 189         struct mpic *mpic;
 190
 191         for_each_node_by_name(dn, "interrupt-controller") {
 192                 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
 193                         continue;
 194
 195                 /* The MPIC driver will get everything it needs from the
 196                  * device-tree, just pass 0 to all arguments
 197                  */
 198                 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
 199                                 0, 0, " MPIC     ");
 200                 if (mpic == NULL)
 201                         continue;
 202                 mpic_init(mpic);
 203         }
 204 }
 205
 206
 207 static void __init cell_init_irq(void)
 208 {
 209         iic_init_IRQ();
 210         spider_init_IRQ();
 211         mpic_init_IRQ();
 212 }
 213
 214 static void __init cell_set_dabrx(void)
 215 {
 216         mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
 217 }
 218
 219 static void __init cell_setup_arch(void)
 220 {
 221 #ifdef CONFIG_SPU_BASE
 222         spu_priv1_ops = &spu_priv1_mmio_ops;
 223         spu_management_ops = &spu_management_of_ops;
 224 #endif
 225
 226         cbe_regs_init();
 227
 228         cell_set_dabrx();
 229
 230 #ifdef CONFIG_CBE_RAS
 231         cbe_ras_init();
 232 #endif
 233
 234 #ifdef CONFIG_SMP
 235         smp_init_cell();
 236 #endif
 237         /* init to some ~sane value until calibrate_delay() runs */
 238         loops_per_jiffy = 50000000;
 239
 240         /* Find and initialize PCI host bridges */
 241         init_pci_config_tokens();
 242
 243         cbe_pervasive_init();
 244
 245         mmio_nvram_init();
 246 }
 247
 248 static int __init cell_probe(void)
 249 {
 250         if (!of_machine_is_compatible("IBM,CBEA") &&
 251             !of_machine_is_compatible("IBM,CPBW-1.0"))
 252                 return 0;
 253
 254         pm_power_off = rtas_power_off;
 255
 256         return 1;
 257 }
 258
 259 define_machine(cell) {
 260         .name                   = "Cell",
 261         .probe                  = cell_probe,
 262         .setup_arch             = cell_setup_arch,
 263         .show_cpuinfo           = cell_show_cpuinfo,
 264         .restart                = rtas_restart,
 265         .halt                   = rtas_halt,
 266         .get_boot_time          = rtas_get_boot_time,
 267         .get_rtc_time           = rtas_get_rtc_time,
 268         .set_rtc_time           = rtas_set_rtc_time,
 269         .progress               = cell_progress,
 270         .init_IRQ               = cell_init_irq,
 271         .pci_setup_phb          = cell_setup_phb,
 272 };
 273
 274 struct pci_controller_ops cell_pci_controller_ops;