drivers/accel/ivpu/vpu_boot_api.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright (c) 2020-2024, Intel Corporation.
   4  */
   5
   6 #ifndef VPU_BOOT_API_H
   7 #define VPU_BOOT_API_H
   8
   9 /*
  10  *  The below values will be used to construct the version info this way:
  11  *  fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
  12  *  VPU_BOOT_API_VER_MINOR;
  13  *  VPU_BOOT_API_VER_PATCH will be ignored. KMD and compatibility is not affected if this changes
  14  *  This information is collected by using vpuip_2/application/vpuFirmware/make_std_fw_image.py
  15  *  If a header is missing this info we ignore the header, if a header is missing or contains
  16  *  partial info a build error will be generated.
  17  */
  18
  19 /*
  20  * Major version changes that break backward compatibility.
  21  * Major version must start from 1 and can only be incremented.
  22  */
  23 #define VPU_BOOT_API_VER_MAJOR 3
  24
  25 /*
  26  * Minor version changes when API backward compatibility is preserved.
  27  * Resets to 0 if Major version is incremented.
  28  */
  29 #define VPU_BOOT_API_VER_MINOR 26
  30
  31 /*
  32  * API header changed (field names, documentation, formatting) but API itself has not been changed
  33  */
  34 #define VPU_BOOT_API_VER_PATCH 3
  35
  36 /*
  37  * Index in the API version table
  38  * Must be unique for each API
  39  */
  40 #define VPU_BOOT_API_VER_INDEX 0
  41
  42 #pragma pack(push, 4)
  43
  44 /*
  45  * Firmware image header format
  46  */
  47 #define VPU_FW_HEADER_SIZE    4096
  48 #define VPU_FW_HEADER_VERSION 0x1
  49 #define VPU_FW_VERSION_SIZE   32
  50 #define VPU_FW_API_VER_NUM    16
  51
  52 struct vpu_firmware_header {
  53         u32 header_version;
  54         u32 image_format;
  55         u64 image_load_address;
  56         u32 image_size;
  57         u64 entry_point;
  58         u8 vpu_version[VPU_FW_VERSION_SIZE];
  59         u32 compression_type;
  60         u64 firmware_version_load_address;
  61         u32 firmware_version_size;
  62         u64 boot_params_load_address;
  63         u32 api_version[VPU_FW_API_VER_NUM];
  64         /* Size of memory require for firmware execution */
  65         u32 runtime_size;
  66         u32 shave_nn_fw_size;
  67         /*
  68          * Size of primary preemption buffer, assuming a 2-job submission queue.
  69          * NOTE: host driver is expected to adapt size accordingly to actual
  70          * submission queue size and device capabilities.
  71          */
  72         u32 preemption_buffer_1_size;
  73         /*
  74          * Size of secondary preemption buffer, assuming a 2-job submission queue.
  75          * NOTE: host driver is expected to adapt size accordingly to actual
  76          * submission queue size and device capabilities.
  77          */
  78         u32 preemption_buffer_2_size;
  79         /* Space reserved for future preemption-related fields. */
  80         u32 preemption_reserved[6];
  81         /* FW image read only section start address, 4KB aligned */
  82         u64 ro_section_start_address;
  83         /* FW image read only section size, 4KB aligned */
  84         u32 ro_section_size;
  85         u32 reserved;
  86 };
  87
  88 /*
  89  * Firmware boot parameters format
  90  */
  91
  92 #define VPU_BOOT_PLL_COUNT     3
  93 #define VPU_BOOT_PLL_OUT_COUNT 4
  94
  95 /** Values for boot_type field */
  96 #define VPU_BOOT_TYPE_COLDBOOT 0
  97 #define VPU_BOOT_TYPE_WARMBOOT 1
  98
  99 /** Value for magic filed */
 100 #define VPU_BOOT_PARAMS_MAGIC 0x10000
 101
 102 /** VPU scheduling mode. By default, OS scheduling is used. */
 103 #define VPU_SCHEDULING_MODE_OS 0
 104 #define VPU_SCHEDULING_MODE_HW 1
 105
 106 enum VPU_BOOT_L2_CACHE_CFG_TYPE {
 107         VPU_BOOT_L2_CACHE_CFG_UPA = 0,
 108         VPU_BOOT_L2_CACHE_CFG_NN = 1,
 109         VPU_BOOT_L2_CACHE_CFG_NUM = 2
 110 };
 111
 112 /** VPU MCA ECC signalling mode. By default, no signalling is used */
 113 enum VPU_BOOT_MCA_ECC_SIGNAL_TYPE {
 114         VPU_BOOT_MCA_ECC_NONE = 0,
 115         VPU_BOOT_MCA_ECC_CORR = 1,
 116         VPU_BOOT_MCA_ECC_FATAL = 2,
 117         VPU_BOOT_MCA_ECC_BOTH = 3
 118 };
 119
 120 /**
 121  * Logging destinations.
 122  *
 123  * Logging output can be directed to different logging destinations. This enum
 124  * defines the list of logging destinations supported by the VPU firmware (NOTE:
 125  * a specific VPU FW binary may support only a subset of such output
 126  * destinations, depending on the target platform and compile options).
 127  */
 128 enum vpu_trace_destination {
 129         VPU_TRACE_DESTINATION_PIPEPRINT = 0x1,
 130         VPU_TRACE_DESTINATION_VERBOSE_TRACING = 0x2,
 131         VPU_TRACE_DESTINATION_NORTH_PEAK = 0x4,
 132 };
 133
 134 /*
 135  * Processor bit shifts (for loggable HW components).
 136  */
 137 #define VPU_TRACE_PROC_BIT_ARM       0
 138 #define VPU_TRACE_PROC_BIT_LRT       1
 139 #define VPU_TRACE_PROC_BIT_LNN       2
 140 #define VPU_TRACE_PROC_BIT_SHV_0     3
 141 #define VPU_TRACE_PROC_BIT_SHV_1     4
 142 #define VPU_TRACE_PROC_BIT_SHV_2     5
 143 #define VPU_TRACE_PROC_BIT_SHV_3     6
 144 #define VPU_TRACE_PROC_BIT_SHV_4     7
 145 #define VPU_TRACE_PROC_BIT_SHV_5     8
 146 #define VPU_TRACE_PROC_BIT_SHV_6     9
 147 #define VPU_TRACE_PROC_BIT_SHV_7     10
 148 #define VPU_TRACE_PROC_BIT_SHV_8     11
 149 #define VPU_TRACE_PROC_BIT_SHV_9     12
 150 #define VPU_TRACE_PROC_BIT_SHV_10    13
 151 #define VPU_TRACE_PROC_BIT_SHV_11    14
 152 #define VPU_TRACE_PROC_BIT_SHV_12    15
 153 #define VPU_TRACE_PROC_BIT_SHV_13    16
 154 #define VPU_TRACE_PROC_BIT_SHV_14    17
 155 #define VPU_TRACE_PROC_BIT_SHV_15    18
 156 #define VPU_TRACE_PROC_BIT_ACT_SHV_0 19
 157 #define VPU_TRACE_PROC_BIT_ACT_SHV_1 20
 158 #define VPU_TRACE_PROC_BIT_ACT_SHV_2 21
 159 #define VPU_TRACE_PROC_BIT_ACT_SHV_3 22
 160 #define VPU_TRACE_PROC_NO_OF_HW_DEVS 23
 161
 162 /* VPU 30xx HW component IDs are sequential, so define first and last IDs. */
 163 #define VPU_TRACE_PROC_BIT_30XX_FIRST VPU_TRACE_PROC_BIT_LRT
 164 #define VPU_TRACE_PROC_BIT_30XX_LAST  VPU_TRACE_PROC_BIT_SHV_15
 165
 166 struct vpu_boot_l2_cache_config {
 167         u8 use;
 168         u8 cfg;
 169 };
 170
 171 struct vpu_warm_boot_section {
 172         u32 src;
 173         u32 dst;
 174         u32 size;
 175         u32 core_id;
 176         u32 is_clear_op;
 177 };
 178
 179 /*
 180  * When HW scheduling mode is enabled, a present period is defined.
 181  * It will be used by VPU to swap between normal and focus priorities
 182  * to prevent starving of normal priority band (when implemented).
 183  * Host must provide a valid value at boot time in
 184  * `vpu_focus_present_timer_ms`. If the value provided by the host is not within the
 185  * defined range a default value will be used. Here we define the min. and max.
 186  * allowed values and the and default value of the present period. Units are milliseconds.
 187  */
 188 #define VPU_PRESENT_CALL_PERIOD_MS_DEFAULT 50
 189 #define VPU_PRESENT_CALL_PERIOD_MS_MIN     16
 190 #define VPU_PRESENT_CALL_PERIOD_MS_MAX     10000
 191
 192 /**
 193  * Macros to enable various power profiles within the NPU.
 194  * To be defined as part of 32 bit mask.
 195  */
 196 #define POWER_PROFILE_SURVIVABILITY 0x1
 197
 198 /**
 199  * Enum for dvfs_mode boot param.
 200  */
 201 enum vpu_governor {
 202         VPU_GOV_DEFAULT = 0, /* Default Governor for the system */
 203         VPU_GOV_MAX_PERFORMANCE = 1, /* Maximum performance governor */
 204         VPU_GOV_ON_DEMAND = 2, /* On Demand frequency control governor */
 205         VPU_GOV_POWER_SAVE = 3, /* Power save governor */
 206         VPU_GOV_ON_DEMAND_PRIORITY_AWARE = 4 /* On Demand priority based governor */
 207 };
 208
 209 struct vpu_boot_params {
 210         u32 magic;
 211         u32 vpu_id;
 212         u32 vpu_count;
 213         u32 pad0[5];
 214         /* Clock frequencies: 0x20 - 0xFF */
 215         u32 frequency;
 216         u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT];
 217         u32 perf_clk_frequency;
 218         u32 pad1[42];
 219         /* Memory regions: 0x100 - 0x1FF */
 220         u64 ipc_header_area_start;
 221         u32 ipc_header_area_size;
 222         u64 shared_region_base;
 223         u32 shared_region_size;
 224         u64 ipc_payload_area_start;
 225         u32 ipc_payload_area_size;
 226         u64 global_aliased_pio_base;
 227         u32 global_aliased_pio_size;
 228         u32 autoconfig;
 229         struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM];
 230         u64 global_memory_allocator_base;
 231         u32 global_memory_allocator_size;
 232         /**
 233          * ShaveNN FW section VPU base address
 234          * On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base
 235          */
 236         u64 shave_nn_fw_base;
 237         u64 save_restore_ret_address; /* stores the address of FW's restore entry point */
 238         u32 pad2[43];
 239         /* IRQ re-direct numbers: 0x200 - 0x2FF */
 240         s32 watchdog_irq_mss;
 241         s32 watchdog_irq_nce;
 242         /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
 243         u32 host_to_vpu_irq;
 244         /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
 245         u32 job_done_irq;
 246         /* VPU -> ARM IRQ line to use to request MMU update. */
 247         u32 mmu_update_request_irq;
 248         /* ARM -> VPU IRQ line to use to notify of MMU update completion. */
 249         u32 mmu_update_done_irq;
 250         /* ARM -> VPU IRQ line to use to request power level change. */
 251         u32 set_power_level_irq;
 252         /* VPU -> ARM IRQ line to use to notify of power level change completion. */
 253         u32 set_power_level_done_irq;
 254         /* VPU -> ARM IRQ line to use to notify of VPU idle state change */
 255         u32 set_vpu_idle_update_irq;
 256         /* VPU -> ARM IRQ line to use to request counter reset. */
 257         u32 metric_query_event_irq;
 258         /* ARM -> VPU IRQ line to use to notify of counter reset completion. */
 259         u32 metric_query_event_done_irq;
 260         /* VPU -> ARM IRQ line to use to notify of preemption completion. */
 261         u32 preemption_done_irq;
 262         /* Padding. */
 263         u32 pad3[52];
 264         /* Silicon information: 0x300 - 0x3FF */
 265         u32 host_version_id;
 266         u32 si_stepping;
 267         u64 device_id;
 268         u64 feature_exclusion;
 269         u64 sku;
 270         /** PLL ratio for minimum clock frequency */
 271         u32 min_freq_pll_ratio;
 272         /** PLL ratio for maximum clock frequency */
 273         u32 max_freq_pll_ratio;
 274         /**
 275          * Initial log level threshold (messages with log level severity less than
 276          * the threshold will not be logged); applies to every enabled logging
 277          * destination and loggable HW component. See 'mvLog_t' enum for acceptable
 278          * values.
 279          * TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
 280          */
 281         u32 default_trace_level;
 282         u32 boot_type;
 283         u64 punit_telemetry_sram_base;
 284         u64 punit_telemetry_sram_size;
 285         u32 vpu_telemetry_enable;
 286         u64 crit_tracing_buff_addr;
 287         u32 crit_tracing_buff_size;
 288         u64 verbose_tracing_buff_addr;
 289         u32 verbose_tracing_buff_size;
 290         u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */
 291         /**
 292          * Mask of destinations to which logging messages are delivered; bitwise OR
 293          * of values defined in vpu_trace_destination enum.
 294          */
 295         u32 trace_destination_mask;
 296         /**
 297          * Mask of hardware components for which logging is enabled; bitwise OR of
 298          * bits defined by the VPU_TRACE_PROC_BIT_* macros.
 299          */
 300         u64 trace_hw_component_mask;
 301         /** Mask of trace message formats supported by the driver */
 302         u64 tracing_buff_message_format_mask;
 303         u64 trace_reserved_1[2];
 304         /**
 305          * Period at which the VPU reads the temp sensor values into MMIO, on
 306          * platforms where that is necessary (in ms). 0 to disable reads.
 307          */
 308         u32 temp_sensor_period_ms;
 309         /** PLL ratio for efficient clock frequency */
 310         u32 pn_freq_pll_ratio;
 311         /**
 312          * DVFS Mode:
 313          * 0 - Default, DVFS mode selected by the firmware
 314          * 1 - Max Performance
 315          * 2 - On Demand
 316          * 3 - Power Save
 317          * 4 - On Demand Priority Aware
 318          */
 319         u32 dvfs_mode;
 320         /**
 321          * Depending on DVFS Mode:
 322          * On-demand: Default if 0.
 323          *    Bit 0-7   - uint8_t: Highest residency percent
 324          *    Bit 8-15  - uint8_t: High residency percent
 325          *    Bit 16-23 - uint8_t: Low residency percent
 326          *    Bit 24-31 - uint8_t: Lowest residency percent
 327          *    Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
 328          *    Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
 329          *    Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
 330          *    Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
 331          *    Bit 48-55 - uint8_t: Period (ms) for residency decisions
 332          *    Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
 333          * Power Save/Max Performance: Unused
 334          */
 335         u64 dvfs_param;
 336         /**
 337          * D0i3 delayed entry
 338          * Bit0: Disable CPU state save on D0i2 entry flow.
 339          *       0: Every D0i2 entry saves state. Save state IPC message ignored.
 340          *       1: IPC message required to save state on D0i3 entry flow.
 341          */
 342         u32 d0i3_delayed_entry;
 343         /* Time spent by VPU in D0i3 state */
 344         u64 d0i3_residency_time_us;
 345         /* Value of VPU perf counter at the time of entering D0i3 state . */
 346         u64 d0i3_entry_vpu_ts;
 347         /*
 348          * The system time of the host operating system in microseconds.
 349          * E.g the number of microseconds since 1st of January 1970, or whatever
 350          * date the host operating system uses to maintain system time.
 351          * This value will be used to track system time on the VPU.
 352          * The KMD is required to update this value on every VPU reset.
 353          */
 354         u64 system_time_us;
 355         u32 pad4[2];
 356         /*
 357          * The delta between device monotonic time and the current value of the
 358          * HW timestamp register, in ticks. Written by the firmware during boot.
 359          * Can be used by the KMD to calculate device time.
 360          */
 361         u64 device_time_delta_ticks;
 362         u32 pad7[14];
 363         /* Warm boot information: 0x400 - 0x43F */
 364         u32 warm_boot_sections_count;
 365         u32 warm_boot_start_address_reference;
 366         u32 warm_boot_section_info_address_offset;
 367         u32 pad5[13];
 368         /* Power States transitions timestamps: 0x440 - 0x46F*/
 369         struct {
 370                 /* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
 371                 u64 vpu_active_state_requested;
 372                 /* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
 373                 u64 vpu_active_state_achieved;
 374                 /* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
 375                 u64 vpu_idle_state_requested;
 376                 /* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
 377                 u64 vpu_idle_state_achieved;
 378                 /* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
 379                 u64 vpu_standby_state_requested;
 380                 /* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
 381                 u64 vpu_standby_state_achieved;
 382         } power_states_timestamps;
 383         /* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */
 384         u32 vpu_scheduling_mode;
 385         /* Present call period in milliseconds. */
 386         u32 vpu_focus_present_timer_ms;
 387         /* VPU ECC Signaling */
 388         u32 vpu_uses_ecc_mca_signal;
 389         /* Values defined by POWER_PROFILE* macros */
 390         u32 power_profile;
 391         /* Microsecond value for DCT active cycle */
 392         u32 dct_active_us;
 393         /* Microsecond value for DCT inactive cycle */
 394         u32 dct_inactive_us;
 395         /* Unused/reserved: 0x488 - 0xFFF */
 396         u32 pad6[734];
 397 };
 398
 399 /* Magic numbers set between host and vpu to detect corruption of tracing init */
 400 #define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE)
 401
 402 /* Tracing buffer message format definitions */
 403 #define VPU_TRACING_FORMAT_STRING 0
 404 #define VPU_TRACING_FORMAT_MIPI   2
 405 /*
 406  * Header of the tracing buffer.
 407  * The below defined header will be stored at the beginning of
 408  * each allocated tracing buffer, followed by a series of 256b
 409  * of ASCII trace message entries.
 410  */
 411 struct vpu_tracing_buffer_header {
 412         /**
 413          * Magic number set by host to detect corruption
 414          * @see VPU_TRACING_BUFFER_CANARY
 415          */
 416         u32 host_canary_start;
 417         /* offset from start of buffer for trace entries */
 418         u32 read_index;
 419         /* keeps track of wrapping on the reader side */
 420         u32 read_wrap_count;
 421         u32 pad_to_cache_line_size_0[13];
 422         /* End of first cache line */
 423
 424         /**
 425          * Magic number set by host to detect corruption
 426          * @see VPU_TRACING_BUFFER_CANARY
 427          */
 428         u32 vpu_canary_start;
 429         /* offset from start of buffer from write start */
 430         u32 write_index;
 431         /* counter for buffer wrapping */
 432         u32 wrap_count;
 433         /* legacy field - do not use */
 434         u32 reserved_0;
 435         /**
 436          * Size of the log buffer include this header (@header_size) and space
 437          * reserved for all messages. If @alignment` is greater that 0 the @Size
 438          * must be multiple of @Alignment.
 439          */
 440         u32 size;
 441         /* Header version */
 442         u16 header_version;
 443         /* Header size */
 444         u16 header_size;
 445         /*
 446          * Format of the messages in the trace buffer
 447          * 0 - null terminated string
 448          * 1 - size + null terminated string
 449          * 2 - MIPI-SysT encoding
 450          */
 451         u32 format;
 452         /*
 453          * Message alignment
 454          * 0 - messages are place 1 after another
 455          * n - every message starts and multiple on offset
 456          */
 457         u32 alignment; /* 64, 128, 256 */
 458         /* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */
 459         char name[16];
 460         u32 pad_to_cache_line_size_1[4];
 461         /* End of second cache line */
 462 };
 463
 464 #pragma pack(pop)
 465
 466 #endif