drivers/clk/imx/clk-fracn-gppll.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2021 NXP
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/export.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/slab.h>
  13 #include <asm/div64.h>
  14
  15 #include "clk.h"
  16
  17 #define PLL_CTRL                0x0
  18 #define HW_CTRL_SEL             BIT(16)
  19 #define CLKMUX_BYPASS           BIT(2)
  20 #define CLKMUX_EN               BIT(1)
  21 #define POWERUP_MASK            BIT(0)
  22
  23 #define PLL_ANA_PRG             0x10
  24 #define PLL_SPREAD_SPECTRUM     0x30
  25
  26 #define PLL_NUMERATOR           0x40
  27 #define PLL_MFN_MASK            GENMASK(31, 2)
  28
  29 #define PLL_DENOMINATOR         0x50
  30 #define PLL_MFD_MASK            GENMASK(29, 0)
  31
  32 #define PLL_DIV                 0x60
  33 #define PLL_MFI_MASK            GENMASK(24, 16)
  34 #define PLL_RDIV_MASK           GENMASK(15, 13)
  35 #define PLL_ODIV_MASK           GENMASK(7, 0)
  36
  37 #define PLL_DFS_CTRL(x)         (0x70 + (x) * 0x10)
  38
  39 #define PLL_STATUS              0xF0
  40 #define LOCK_STATUS             BIT(0)
  41
  42 #define DFS_STATUS              0xF4
  43
  44 #define LOCK_TIMEOUT_US         200
  45
  46 #define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv)     \
  47         {                                                       \
  48                 .rate   =       (_rate),                        \
  49                 .mfi    =       (_mfi),                         \
  50                 .mfn    =       (_mfn),                         \
  51                 .mfd    =       (_mfd),                         \
  52                 .rdiv   =       (_rdiv),                        \
  53                 .odiv   =       (_odiv),                        \
  54         }
  55
  56 #define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv)         \
  57         {                                                       \
  58                 .rate   =       (_rate),                        \
  59                 .mfi    =       (_mfi),                         \
  60                 .mfn    =       0,                              \
  61                 .mfd    =       0,                              \
  62                 .rdiv   =       (_rdiv),                        \
  63                 .odiv   =       (_odiv),                        \
  64         }
  65
  66 struct clk_fracn_gppll {
  67         struct clk_hw                   hw;
  68         void __iomem                    *base;
  69         const struct imx_fracn_gppll_rate_table *rate_table;
  70         int rate_count;
  71         u32 flags;
  72 };
  73
  74 /*
  75  * Fvco = (Fref / rdiv) * (MFI + MFN / MFD)
  76  * Fout = Fvco / odiv
  77  * The (Fref / rdiv) should be in range 20MHz to 40MHz
  78  * The Fvco should be in range 2.5Ghz to 5Ghz
  79  */
  80 static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
  81         PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
  82         PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
  83         PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
  84         PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
  85         PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
  86         PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
  87         PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
  88         PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
  89         PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
  90         PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
  91         PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
  92 };
  93
  94 struct imx_fracn_gppll_clk imx_fracn_gppll = {
  95         .rate_table = fracn_tbl,
  96         .rate_count = ARRAY_SIZE(fracn_tbl),
  97 };
  98 EXPORT_SYMBOL_GPL(imx_fracn_gppll);
  99
 100 /*
 101  * Fvco = (Fref / rdiv) * MFI
 102  * Fout = Fvco / odiv
 103  * The (Fref / rdiv) should be in range 20MHz to 40MHz
 104  * The Fvco should be in range 2.5Ghz to 5Ghz
 105  */
 106 static const struct imx_fracn_gppll_rate_table int_tbl[] = {
 107         PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2),
 108         PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3),
 109         PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4),
 110         PLL_FRACN_GP_INTEGER(800000000U, 200, 1, 6),
 111 };
 112
 113 struct imx_fracn_gppll_clk imx_fracn_gppll_integer = {
 114         .rate_table = int_tbl,
 115         .rate_count = ARRAY_SIZE(int_tbl),
 116 };
 117 EXPORT_SYMBOL_GPL(imx_fracn_gppll_integer);
 118
 119 static inline struct clk_fracn_gppll *to_clk_fracn_gppll(struct clk_hw *hw)
 120 {
 121         return container_of(hw, struct clk_fracn_gppll, hw);
 122 }
 123
 124 static const struct imx_fracn_gppll_rate_table *
 125 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate)
 126 {
 127         const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
 128         int i;
 129
 130         for (i = 0; i < pll->rate_count; i++)
 131                 if (rate == rate_table[i].rate)
 132                         return &rate_table[i];
 133
 134         return NULL;
 135 }
 136
 137 static long clk_fracn_gppll_round_rate(struct clk_hw *hw, unsigned long rate,
 138                                        unsigned long *prate)
 139 {
 140         struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
 141         const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
 142         int i;
 143
 144         /* Assuming rate_table is in descending order */
 145         for (i = 0; i < pll->rate_count; i++)
 146                 if (rate >= rate_table[i].rate)
 147                         return rate_table[i].rate;
 148
 149         /* return minimum supported value */
 150         return rate_table[pll->rate_count - 1].rate;
 151 }
 152
 153 static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 154 {
 155         struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
 156         const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table;
 157         u32 pll_numerator, pll_denominator, pll_div;
 158         u32 mfi, mfn, mfd, rdiv, odiv;
 159         u64 fvco = parent_rate;
 160         long rate = 0;
 161         int i;
 162
 163         pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
 164         mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
 165
 166         pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
 167         mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
 168
 169         pll_div = readl_relaxed(pll->base + PLL_DIV);
 170         mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
 171
 172         rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
 173         odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
 174
 175         /*
 176          * Sometimes, the recalculated rate has deviation due to
 177          * the frac part. So find the accurate pll rate from the table
 178          * first, if no match rate in the table, use the rate calculated
 179          * from the equation below.
 180          */
 181         for (i = 0; i < pll->rate_count; i++) {
 182                 if (rate_table[i].mfn == mfn && rate_table[i].mfi == mfi &&
 183                     rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv &&
 184                     rate_table[i].odiv == odiv)
 185                         rate = rate_table[i].rate;
 186         }
 187
 188         if (rate)
 189                 return (unsigned long)rate;
 190
 191         if (!rdiv)
 192                 rdiv = rdiv + 1;
 193
 194         switch (odiv) {
 195         case 0:
 196                 odiv = 2;
 197                 break;
 198         case 1:
 199                 odiv = 3;
 200                 break;
 201         default:
 202                 break;
 203         }
 204
 205         if (pll->flags & CLK_FRACN_GPPLL_INTEGER) {
 206                 /* Fvco = (Fref / rdiv) * MFI */
 207                 fvco = fvco * mfi;
 208                 do_div(fvco, rdiv * odiv);
 209         } else {
 210                 /* Fvco = (Fref / rdiv) * (MFI + MFN / MFD) */
 211                 fvco = fvco * mfi * mfd + fvco * mfn;
 212                 do_div(fvco, mfd * rdiv * odiv);
 213         }
 214
 215         return (unsigned long)fvco;
 216 }
 217
 218 static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)
 219 {
 220         u32 val;
 221
 222         return readl_poll_timeout(pll->base + PLL_STATUS, val,
 223                                   val & LOCK_STATUS, 0, LOCK_TIMEOUT_US);
 224 }
 225
 226 static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate,
 227                                     unsigned long prate)
 228 {
 229         struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
 230         const struct imx_fracn_gppll_rate_table *rate;
 231         u32 tmp, pll_div, ana_mfn;
 232         int ret;
 233
 234         rate = imx_get_pll_settings(pll, drate);
 235
 236         /* Hardware control select disable. PLL is control by register */
 237         tmp = readl_relaxed(pll->base + PLL_CTRL);
 238         tmp &= ~HW_CTRL_SEL;
 239         writel_relaxed(tmp, pll->base + PLL_CTRL);
 240
 241         /* Disable output */
 242         tmp = readl_relaxed(pll->base + PLL_CTRL);
 243         tmp &= ~CLKMUX_EN;
 244         writel_relaxed(tmp, pll->base + PLL_CTRL);
 245
 246         /* Power Down */
 247         tmp &= ~POWERUP_MASK;
 248         writel_relaxed(tmp, pll->base + PLL_CTRL);
 249
 250         /* Disable BYPASS */
 251         tmp &= ~CLKMUX_BYPASS;
 252         writel_relaxed(tmp, pll->base + PLL_CTRL);
 253
 254         pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv |
 255                 FIELD_PREP(PLL_MFI_MASK, rate->mfi);
 256         writel_relaxed(pll_div, pll->base + PLL_DIV);
 257         readl(pll->base + PLL_DIV);
 258         if (pll->flags & CLK_FRACN_GPPLL_FRACN) {
 259                 writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR);
 260                 writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR);
 261                 readl(pll->base + PLL_NUMERATOR);
 262         }
 263
 264         /* Wait for 5us according to fracn mode pll doc */
 265         udelay(5);
 266
 267         /* Enable Powerup */
 268         tmp |= POWERUP_MASK;
 269         writel_relaxed(tmp, pll->base + PLL_CTRL);
 270         readl(pll->base + PLL_CTRL);
 271
 272         /* Wait Lock */
 273         ret = clk_fracn_gppll_wait_lock(pll);
 274         if (ret)
 275                 return ret;
 276
 277         /* Enable output */
 278         tmp |= CLKMUX_EN;
 279         writel_relaxed(tmp, pll->base + PLL_CTRL);
 280
 281         ana_mfn = readl_relaxed(pll->base + PLL_STATUS);
 282         ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn);
 283
 284         WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n");
 285
 286         return 0;
 287 }
 288
 289 static int clk_fracn_gppll_prepare(struct clk_hw *hw)
 290 {
 291         struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
 292         u32 val;
 293         int ret;
 294
 295         val = readl_relaxed(pll->base + PLL_CTRL);
 296         if (val & POWERUP_MASK)
 297                 return 0;
 298
 299         if (pll->flags & CLK_FRACN_GPPLL_FRACN)
 300                 writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
 301                                pll->base + PLL_NUMERATOR);
 302
 303         val |= CLKMUX_BYPASS;
 304         writel_relaxed(val, pll->base + PLL_CTRL);
 305
 306         val |= POWERUP_MASK;
 307         writel_relaxed(val, pll->base + PLL_CTRL);
 308         readl(pll->base + PLL_CTRL);
 309
 310         ret = clk_fracn_gppll_wait_lock(pll);
 311         if (ret)
 312                 return ret;
 313
 314         val |= CLKMUX_EN;
 315         writel_relaxed(val, pll->base + PLL_CTRL);
 316
 317         val &= ~CLKMUX_BYPASS;
 318         writel_relaxed(val, pll->base + PLL_CTRL);
 319
 320         return 0;
 321 }
 322
 323 static int clk_fracn_gppll_is_prepared(struct clk_hw *hw)
 324 {
 325         struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
 326         u32 val;
 327
 328         val = readl_relaxed(pll->base + PLL_CTRL);
 329
 330         return (val & POWERUP_MASK) ? 1 : 0;
 331 }
 332
 333 static void clk_fracn_gppll_unprepare(struct clk_hw *hw)
 334 {
 335         struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw);
 336         u32 val;
 337
 338         val = readl_relaxed(pll->base + PLL_CTRL);
 339         val &= ~POWERUP_MASK;
 340         writel_relaxed(val, pll->base + PLL_CTRL);
 341 }
 342
 343 static const struct clk_ops clk_fracn_gppll_ops = {
 344         .prepare        = clk_fracn_gppll_prepare,
 345         .unprepare      = clk_fracn_gppll_unprepare,
 346         .is_prepared    = clk_fracn_gppll_is_prepared,
 347         .recalc_rate    = clk_fracn_gppll_recalc_rate,
 348         .round_rate     = clk_fracn_gppll_round_rate,
 349         .set_rate       = clk_fracn_gppll_set_rate,
 350 };
 351
 352 static struct clk_hw *_imx_clk_fracn_gppll(const char *name, const char *parent_name,
 353                                            void __iomem *base,
 354                                            const struct imx_fracn_gppll_clk *pll_clk,
 355                                            u32 pll_flags)
 356 {
 357         struct clk_fracn_gppll *pll;
 358         struct clk_hw *hw;
 359         struct clk_init_data init;
 360         int ret;
 361
 362         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 363         if (!pll)
 364                 return ERR_PTR(-ENOMEM);
 365
 366         init.name = name;
 367         init.flags = pll_clk->flags;
 368         init.parent_names = &parent_name;
 369         init.num_parents = 1;
 370         init.ops = &clk_fracn_gppll_ops;
 371
 372         pll->base = base;
 373         pll->hw.init = &init;
 374         pll->rate_table = pll_clk->rate_table;
 375         pll->rate_count = pll_clk->rate_count;
 376         pll->flags = pll_flags;
 377
 378         hw = &pll->hw;
 379
 380         ret = clk_hw_register(NULL, hw);
 381         if (ret) {
 382                 pr_err("%s: failed to register pll %s %d\n", __func__, name, ret);
 383                 kfree(pll);
 384                 return ERR_PTR(ret);
 385         }
 386
 387         return hw;
 388 }
 389
 390 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
 391                                    const struct imx_fracn_gppll_clk *pll_clk)
 392 {
 393         return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN);
 394 }
 395 EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll);
 396
 397 struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
 398                                            void __iomem *base,
 399                                            const struct imx_fracn_gppll_clk *pll_clk)
 400 {
 401         return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER);
 402 }
 403 EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll_integer);