drivers/clk/mediatek/clk-mt6735-infracfg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/platform_device.h>
   8
   9 #include "clk-gate.h"
  10 #include "clk-mtk.h"
  11
  12 #include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
  13 #include <dt-bindings/reset/mediatek,mt6735-infracfg.h>
  14
  15 #define INFRA_RST0                      0x30
  16 #define INFRA_GLOBALCON_PDN0            0x40
  17 #define INFRA_PDN1                      0x44
  18 #define INFRA_PDN_STA                   0x48
  19
  20 #define RST_NR_PER_BANK                 32
  21
  22 static struct mtk_gate_regs infra_cg_regs = {
  23         .set_ofs = INFRA_GLOBALCON_PDN0,
  24         .clr_ofs = INFRA_PDN1,
  25         .sta_ofs = INFRA_PDN_STA,
  26 };
  27
  28 static const struct mtk_gate infracfg_gates[] = {
  29         GATE_MTK(CLK_INFRA_DBG, "dbg", "axi_sel", &infra_cg_regs, 0, &mtk_clk_gate_ops_setclr),
  30         GATE_MTK(CLK_INFRA_GCE, "gce", "axi_sel", &infra_cg_regs, 1, &mtk_clk_gate_ops_setclr),
  31         GATE_MTK(CLK_INFRA_TRBG, "trbg", "axi_sel", &infra_cg_regs, 2, &mtk_clk_gate_ops_setclr),
  32         GATE_MTK(CLK_INFRA_CPUM, "cpum", "axi_sel", &infra_cg_regs, 3, &mtk_clk_gate_ops_setclr),
  33         GATE_MTK(CLK_INFRA_DEVAPC, "devapc", "axi_sel", &infra_cg_regs, 4, &mtk_clk_gate_ops_setclr),
  34         GATE_MTK(CLK_INFRA_AUDIO, "audio", "aud_intbus_sel", &infra_cg_regs, 5, &mtk_clk_gate_ops_setclr),
  35         GATE_MTK(CLK_INFRA_GCPU, "gcpu", "axi_sel", &infra_cg_regs, 6, &mtk_clk_gate_ops_setclr),
  36         GATE_MTK(CLK_INFRA_L2C_SRAM, "l2csram", "axi_sel", &infra_cg_regs, 7, &mtk_clk_gate_ops_setclr),
  37         GATE_MTK(CLK_INFRA_M4U, "m4u", "axi_sel", &infra_cg_regs, 8, &mtk_clk_gate_ops_setclr),
  38         GATE_MTK(CLK_INFRA_CLDMA, "cldma", "axi_sel", &infra_cg_regs, 12, &mtk_clk_gate_ops_setclr),
  39         GATE_MTK(CLK_INFRA_CONNMCU_BUS, "connmcu_bus", "axi_sel", &infra_cg_regs, 15, &mtk_clk_gate_ops_setclr),
  40         GATE_MTK(CLK_INFRA_KP, "kp", "axi_sel", &infra_cg_regs, 16, &mtk_clk_gate_ops_setclr),
  41         GATE_MTK_FLAGS(CLK_INFRA_APXGPT, "apxgpt", "axi_sel", &infra_cg_regs, 18, &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL),
  42         GATE_MTK(CLK_INFRA_SEJ, "sej", "axi_sel", &infra_cg_regs, 19, &mtk_clk_gate_ops_setclr),
  43         GATE_MTK(CLK_INFRA_CCIF0_AP, "ccif0ap", "axi_sel", &infra_cg_regs, 20, &mtk_clk_gate_ops_setclr),
  44         GATE_MTK(CLK_INFRA_CCIF1_AP, "ccif1ap", "axi_sel", &infra_cg_regs, 21, &mtk_clk_gate_ops_setclr),
  45         GATE_MTK(CLK_INFRA_PMIC_SPI, "pmicspi", "pmicspi_sel", &infra_cg_regs, 22, &mtk_clk_gate_ops_setclr),
  46         GATE_MTK(CLK_INFRA_PMIC_WRAP, "pmicwrap", "axi_sel", &infra_cg_regs, 23, &mtk_clk_gate_ops_setclr)
  47 };
  48
  49 static u16 infracfg_rst_bank_ofs[] = { INFRA_RST0 };
  50
  51 static u16 infracfg_rst_idx_map[] = {
  52         [MT6735_INFRA_RST0_EMI_REG]             = 0 * RST_NR_PER_BANK + 0,
  53         [MT6735_INFRA_RST0_DRAMC0_AO]           = 0 * RST_NR_PER_BANK + 1,
  54         [MT6735_INFRA_RST0_AP_CIRQ_EINT]        = 0 * RST_NR_PER_BANK + 3,
  55         [MT6735_INFRA_RST0_APXGPT]              = 0 * RST_NR_PER_BANK + 4,
  56         [MT6735_INFRA_RST0_SCPSYS]              = 0 * RST_NR_PER_BANK + 5,
  57         [MT6735_INFRA_RST0_KP]                  = 0 * RST_NR_PER_BANK + 6,
  58         [MT6735_INFRA_RST0_PMIC_WRAP]           = 0 * RST_NR_PER_BANK + 7,
  59         [MT6735_INFRA_RST0_CLDMA_AO_TOP]        = 0 * RST_NR_PER_BANK + 8,
  60         [MT6735_INFRA_RST0_USBSIF_TOP]          = 0 * RST_NR_PER_BANK + 9,
  61         [MT6735_INFRA_RST0_EMI]                 = 0 * RST_NR_PER_BANK + 16,
  62         [MT6735_INFRA_RST0_CCIF]                = 0 * RST_NR_PER_BANK + 17,
  63         [MT6735_INFRA_RST0_DRAMC0]              = 0 * RST_NR_PER_BANK + 18,
  64         [MT6735_INFRA_RST0_EMI_AO_REG]          = 0 * RST_NR_PER_BANK + 19,
  65         [MT6735_INFRA_RST0_CCIF_AO]             = 0 * RST_NR_PER_BANK + 20,
  66         [MT6735_INFRA_RST0_TRNG]                = 0 * RST_NR_PER_BANK + 21,
  67         [MT6735_INFRA_RST0_SYS_CIRQ]            = 0 * RST_NR_PER_BANK + 22,
  68         [MT6735_INFRA_RST0_GCE]                 = 0 * RST_NR_PER_BANK + 23,
  69         [MT6735_INFRA_RST0_M4U]                 = 0 * RST_NR_PER_BANK + 24,
  70         [MT6735_INFRA_RST0_CCIF1]               = 0 * RST_NR_PER_BANK + 25,
  71         [MT6735_INFRA_RST0_CLDMA_TOP_PD]        = 0 * RST_NR_PER_BANK + 26
  72 };
  73
  74 static const struct mtk_clk_rst_desc infracfg_resets = {
  75         .version = MTK_RST_SIMPLE,
  76         .rst_bank_ofs = infracfg_rst_bank_ofs,
  77         .rst_bank_nr = ARRAY_SIZE(infracfg_rst_bank_ofs),
  78         .rst_idx_map = infracfg_rst_idx_map,
  79         .rst_idx_map_nr = ARRAY_SIZE(infracfg_rst_idx_map)
  80 };
  81
  82 static const struct mtk_clk_desc infracfg_clks = {
  83         .clks = infracfg_gates,
  84         .num_clks = ARRAY_SIZE(infracfg_gates),
  85
  86         .rst_desc = &infracfg_resets
  87 };
  88
  89 static const struct of_device_id of_match_mt6735_infracfg[] = {
  90         { .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
  91         { /* sentinel */ }
  92 };
  93 MODULE_DEVICE_TABLE(of, of_match_mt6735_infracfg);
  94
  95 static struct platform_driver clk_mt6735_infracfg = {
  96         .probe = mtk_clk_simple_probe,
  97         .remove = mtk_clk_simple_remove,
  98         .driver = {
  99                 .name = "clk-mt6735-infracfg",
 100                 .of_match_table = of_match_mt6735_infracfg,
 101         },
 102 };
 103 module_platform_driver(clk_mt6735_infracfg);
 104
 105 MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
 106 MODULE_DESCRIPTION("MediaTek MT6735 infracfg clock and reset driver");
 107 MODULE_LICENSE("GPL");