drivers/clk/mediatek/clk-mt8188-img.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  * Author: Garmin Chang <garmin.chang@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/platform_device.h>
  10
  11 #include "clk-gate.h"
  12 #include "clk-mtk.h"
  13
  14 static const struct mtk_gate_regs imgsys_cg_regs = {
  15         .set_ofs = 0x4,
  16         .clr_ofs = 0x8,
  17         .sta_ofs = 0x0,
  18 };
  19
  20 #define GATE_IMGSYS(_id, _name, _parent, _shift)                        \
  21         GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  22
  23 static const struct mtk_gate imgsys_main_clks[] = {
  24         GATE_IMGSYS(CLK_IMGSYS_MAIN_LARB9, "imgsys_main_larb9", "top_img", 0),
  25         GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW0, "imgsys_main_traw0", "top_img", 1),
  26         GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW1, "imgsys_main_traw1", "top_img", 2),
  27         GATE_IMGSYS(CLK_IMGSYS_MAIN_VCORE_GALS, "imgsys_main_vcore_gals", "top_img", 3),
  28         GATE_IMGSYS(CLK_IMGSYS_MAIN_DIP0, "imgsys_main_dip0", "top_img", 8),
  29         GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE0, "imgsys_main_wpe0", "top_img", 9),
  30         GATE_IMGSYS(CLK_IMGSYS_MAIN_IPE, "imgsys_main_ipe", "top_img", 10),
  31         GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE1, "imgsys_main_wpe1", "top_img", 12),
  32         GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE2, "imgsys_main_wpe2", "top_img", 13),
  33         GATE_IMGSYS(CLK_IMGSYS_MAIN_GALS, "imgsys_main_gals", "top_img", 31),
  34 };
  35
  36 static const struct mtk_gate imgsys_wpe1_clks[] = {
  37         GATE_IMGSYS(CLK_IMGSYS_WPE1_LARB11, "imgsys_wpe1_larb11", "top_img", 0),
  38         GATE_IMGSYS(CLK_IMGSYS_WPE1, "imgsys_wpe1", "top_img", 1),
  39 };
  40
  41 static const struct mtk_gate imgsys_wpe2_clks[] = {
  42         GATE_IMGSYS(CLK_IMGSYS_WPE2_LARB11, "imgsys_wpe2_larb11", "top_img", 0),
  43         GATE_IMGSYS(CLK_IMGSYS_WPE2, "imgsys_wpe2", "top_img", 1),
  44 };
  45
  46 static const struct mtk_gate imgsys_wpe3_clks[] = {
  47         GATE_IMGSYS(CLK_IMGSYS_WPE3_LARB11, "imgsys_wpe3_larb11", "top_img", 0),
  48         GATE_IMGSYS(CLK_IMGSYS_WPE3, "imgsys_wpe3", "top_img", 1),
  49 };
  50
  51 static const struct mtk_gate imgsys1_dip_top_clks[] = {
  52         GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_LARB10, "imgsys1_dip_larb10", "top_img", 0),
  53         GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_DIP_TOP, "imgsys1_dip_dip_top", "top_img", 1),
  54 };
  55
  56 static const struct mtk_gate imgsys1_dip_nr_clks[] = {
  57         GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_LARB15, "imgsys1_dip_nr_larb15", "top_img", 0),
  58         GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_DIP_NR, "imgsys1_dip_nr_dip_nr", "top_img", 1),
  59 };
  60
  61 static const struct mtk_clk_desc imgsys_main_desc = {
  62         .clks = imgsys_main_clks,
  63         .num_clks = ARRAY_SIZE(imgsys_main_clks),
  64 };
  65
  66 static const struct mtk_clk_desc imgsys_wpe1_desc = {
  67         .clks = imgsys_wpe1_clks,
  68         .num_clks = ARRAY_SIZE(imgsys_wpe1_clks),
  69 };
  70
  71 static const struct mtk_clk_desc imgsys_wpe2_desc = {
  72         .clks = imgsys_wpe2_clks,
  73         .num_clks = ARRAY_SIZE(imgsys_wpe2_clks),
  74 };
  75
  76 static const struct mtk_clk_desc imgsys_wpe3_desc = {
  77         .clks = imgsys_wpe3_clks,
  78         .num_clks = ARRAY_SIZE(imgsys_wpe3_clks),
  79 };
  80
  81 static const struct mtk_clk_desc imgsys1_dip_top_desc = {
  82         .clks = imgsys1_dip_top_clks,
  83         .num_clks = ARRAY_SIZE(imgsys1_dip_top_clks),
  84 };
  85
  86 static const struct mtk_clk_desc imgsys1_dip_nr_desc = {
  87         .clks = imgsys1_dip_nr_clks,
  88         .num_clks = ARRAY_SIZE(imgsys1_dip_nr_clks),
  89 };
  90
  91 static const struct of_device_id of_match_clk_mt8188_imgsys_main[] = {
  92         { .compatible = "mediatek,mt8188-imgsys", .data = &imgsys_main_desc },
  93         { .compatible = "mediatek,mt8188-imgsys-wpe1", .data = &imgsys_wpe1_desc },
  94         { .compatible = "mediatek,mt8188-imgsys-wpe2", .data = &imgsys_wpe2_desc },
  95         { .compatible = "mediatek,mt8188-imgsys-wpe3", .data = &imgsys_wpe3_desc },
  96         { .compatible = "mediatek,mt8188-imgsys1-dip-top", .data = &imgsys1_dip_top_desc },
  97         { .compatible = "mediatek,mt8188-imgsys1-dip-nr", .data = &imgsys1_dip_nr_desc },
  98         { /* sentinel */ }
  99 };
 100 MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_imgsys_main);
 101
 102 static struct platform_driver clk_mt8188_imgsys_main_drv = {
 103         .probe = mtk_clk_simple_probe,
 104         .remove = mtk_clk_simple_remove,
 105         .driver = {
 106                 .name = "clk-mt8188-imgsys_main",
 107                 .of_match_table = of_match_clk_mt8188_imgsys_main,
 108         },
 109 };
 110 module_platform_driver(clk_mt8188_imgsys_main_drv);
 111
 112 MODULE_DESCRIPTION("MediaTek MT8188 imgsys clocks driver");
 113 MODULE_LICENSE("GPL");