drivers/clk/mediatek/clk-mt8192-mm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Copyright (c) 2021 MediaTek Inc.
   4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/platform_device.h>
   8
   9 #include "clk-mtk.h"
  10 #include "clk-gate.h"
  11
  12 #include <dt-bindings/clock/mt8192-clk.h>
  13
  14 static const struct mtk_gate_regs mm0_cg_regs = {
  15         .set_ofs = 0x104,
  16         .clr_ofs = 0x108,
  17         .sta_ofs = 0x100,
  18 };
  19
  20 static const struct mtk_gate_regs mm1_cg_regs = {
  21         .set_ofs = 0x114,
  22         .clr_ofs = 0x118,
  23         .sta_ofs = 0x110,
  24 };
  25
  26 static const struct mtk_gate_regs mm2_cg_regs = {
  27         .set_ofs = 0x1a4,
  28         .clr_ofs = 0x1a8,
  29         .sta_ofs = 0x1a0,
  30 };
  31
  32 #define GATE_MM0(_id, _name, _parent, _shift)   \
  33         GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  34
  35 #define GATE_MM1(_id, _name, _parent, _shift)   \
  36         GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  37
  38 #define GATE_MM2(_id, _name, _parent, _shift)   \
  39         GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
  40
  41 static const struct mtk_gate mm_clks[] = {
  42         /* MM0 */
  43         GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
  44         GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
  45         GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
  46         GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
  47         GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
  48         GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
  49         GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
  50         GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
  51         GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
  52         GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
  53         GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
  54         GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
  55         GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
  56         GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
  57         GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
  58         GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
  59         GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
  60         GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
  61         GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
  62         GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
  63         GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
  64         GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
  65         GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
  66         GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
  67         GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
  68         GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
  69         GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
  70         GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
  71         GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
  72         GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
  73         GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
  74         /* MM1 */
  75         GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
  76         /* MM2 */
  77         GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
  78         GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
  79         GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
  80         GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
  81 };
  82
  83 static const struct mtk_clk_desc mm_desc = {
  84         .clks = mm_clks,
  85         .num_clks = ARRAY_SIZE(mm_clks),
  86 };
  87
  88 static const struct platform_device_id clk_mt8192_mm_id_table[] = {
  89         { .name = "clk-mt8192-mm", .driver_data = (kernel_ulong_t)&mm_desc },
  90         { /* sentinel */ }
  91 };
  92 MODULE_DEVICE_TABLE(platform, clk_mt8192_mm_id_table);
  93
  94 static struct platform_driver clk_mt8192_mm_drv = {
  95         .probe = mtk_clk_pdev_probe,
  96         .remove = mtk_clk_pdev_remove,
  97         .driver = {
  98                 .name = "clk-mt8192-mm",
  99         },
 100         .id_table = clk_mt8192_mm_id_table,
 101 };
 102 module_platform_driver(clk_mt8192_mm_drv);
 103
 104 MODULE_DESCRIPTION("MediaTek MT8192 MultiMedia clocks driver");
 105 MODULE_LICENSE("GPL");