drivers/clk/mediatek/clk-mt8192.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 //
   3 // Copyright (c) 2021 MediaTek Inc.
   4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/mfd/syscon.h>
   9 #include <linux/mod_devicetable.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/slab.h>
  12
  13 #include "clk-gate.h"
  14 #include "clk-mtk.h"
  15 #include "clk-mux.h"
  16
  17 #include <dt-bindings/clock/mt8192-clk.h>
  18 #include <dt-bindings/reset/mt8192-resets.h>
  19
  20 static DEFINE_SPINLOCK(mt8192_clk_lock);
  21
  22 static const struct mtk_fixed_clk top_fixed_clks[] = {
  23         FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000),
  24 };
  25
  26 static const struct mtk_fixed_factor top_divs[] = {
  27         FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
  28         FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
  29         FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
  30         FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
  31         FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
  32         FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
  33         FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
  34         FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
  35         FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
  36         FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
  37         FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
  38         FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
  39         FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
  40         FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
  41         FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
  42         FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
  43         FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
  44         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
  45         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
  46         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
  47         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
  48         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
  49         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
  50         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
  51         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
  52         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
  53         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
  54         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
  55         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
  56         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
  57         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
  58         FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
  59         FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
  60         FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
  61         FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
  62         FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
  63         FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
  64         FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
  65         FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
  66         FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
  67         FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
  68         FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
  69         FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
  70         FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
  71         FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
  72         FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
  73         FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
  74         FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
  75         FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2),
  76         FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1),
  77         FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
  78         FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
  79         FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
  80         FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
  81         FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
  82         FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
  83         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
  84         FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
  85         FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
  86         FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
  87         FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
  88         FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
  89         FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
  90         FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
  91         FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
  92         FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
  93         FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
  94         FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0),
  95         FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
  96         FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
  97         FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
  98         FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
  99 };
 100
 101 static const char * const axi_parents[] = {
 102         "clk26m",
 103         "mainpll_d4_d4",
 104         "mainpll_d7_d2",
 105         "mainpll_d4_d2",
 106         "mainpll_d5_d2",
 107         "mainpll_d6_d2",
 108         "osc_d4"
 109 };
 110
 111 static const char * const spm_parents[] = {
 112         "clk26m",
 113         "osc_d10",
 114         "mainpll_d7_d4",
 115         "clk32k"
 116 };
 117
 118 static const char * const scp_parents[] = {
 119         "clk26m",
 120         "univpll_d5",
 121         "mainpll_d6_d2",
 122         "mainpll_d6",
 123         "univpll_d6",
 124         "mainpll_d4_d2",
 125         "mainpll_d5_d2",
 126         "univpll_d4_d2"
 127 };
 128
 129 static const char * const bus_aximem_parents[] = {
 130         "clk26m",
 131         "mainpll_d7_d2",
 132         "mainpll_d4_d2",
 133         "mainpll_d5_d2",
 134         "mainpll_d6"
 135 };
 136
 137 static const char * const disp_parents[] = {
 138         "clk26m",
 139         "univpll_d6_d2",
 140         "mainpll_d5_d2",
 141         "mmpll_d6_d2",
 142         "univpll_d5_d2",
 143         "univpll_d4_d2",
 144         "mmpll_d7",
 145         "univpll_d6",
 146         "mainpll_d4",
 147         "mmpll_d5_d2"
 148 };
 149
 150 static const char * const mdp_parents[] = {
 151         "clk26m",
 152         "mainpll_d5_d2",
 153         "mmpll_d6_d2",
 154         "mainpll_d4_d2",
 155         "mmpll_d4_d2",
 156         "mainpll_d6",
 157         "univpll_d6",
 158         "mainpll_d4",
 159         "tvdpll_ck",
 160         "univpll_d4",
 161         "mmpll_d5_d2"
 162 };
 163
 164 static const char * const img_parents[] = {
 165         "clk26m",
 166         "univpll_d4",
 167         "tvdpll_ck",
 168         "mainpll_d4",
 169         "univpll_d5",
 170         "mmpll_d6",
 171         "univpll_d6",
 172         "mainpll_d6",
 173         "mmpll_d4_d2",
 174         "mainpll_d4_d2",
 175         "mmpll_d6_d2",
 176         "mmpll_d5_d2"
 177 };
 178
 179 static const char * const ipe_parents[] = {
 180         "clk26m",
 181         "mainpll_d4",
 182         "mmpll_d6",
 183         "univpll_d6",
 184         "mainpll_d6",
 185         "univpll_d4_d2",
 186         "mainpll_d4_d2",
 187         "mmpll_d6_d2",
 188         "mmpll_d5_d2"
 189 };
 190
 191 static const char * const dpe_parents[] = {
 192         "clk26m",
 193         "mainpll_d4",
 194         "mmpll_d6",
 195         "univpll_d6",
 196         "mainpll_d6",
 197         "univpll_d4_d2",
 198         "univpll_d5_d2",
 199         "mmpll_d6_d2"
 200 };
 201
 202 static const char * const cam_parents[] = {
 203         "clk26m",
 204         "mainpll_d4",
 205         "mmpll_d6",
 206         "univpll_d4",
 207         "univpll_d5",
 208         "univpll_d6",
 209         "mmpll_d7",
 210         "univpll_d4_d2",
 211         "mainpll_d4_d2",
 212         "univpll_d6_d2"
 213 };
 214
 215 static const char * const ccu_parents[] = {
 216         "clk26m",
 217         "mainpll_d4",
 218         "mmpll_d6",
 219         "mainpll_d6",
 220         "mmpll_d7",
 221         "univpll_d4_d2",
 222         "mmpll_d6_d2",
 223         "mmpll_d5_d2",
 224         "univpll_d5",
 225         "univpll_d6_d2"
 226 };
 227
 228 static const char * const dsp7_parents[] = {
 229         "clk26m",
 230         "mainpll_d4_d2",
 231         "mainpll_d6",
 232         "mmpll_d6",
 233         "univpll_d5",
 234         "mmpll_d5",
 235         "univpll_d4",
 236         "mmpll_d4"
 237 };
 238
 239 static const char * const mfg_ref_parents[] = {
 240         "clk26m",
 241         "clk26m",
 242         "univpll_d6",
 243         "mainpll_d5_d2"
 244 };
 245
 246 static const char * const mfg_pll_parents[] = {
 247         "mfg_ref_sel",
 248         "mfgpll"
 249 };
 250
 251 static const char * const camtg_parents[] = {
 252         "clk26m",
 253         "univpll_192m_d8",
 254         "univpll_d6_d8",
 255         "univpll_192m_d4",
 256         "univpll_d6_d16",
 257         "csw_f26m_d2",
 258         "univpll_192m_d16",
 259         "univpll_192m_d32"
 260 };
 261
 262 static const char * const uart_parents[] = {
 263         "clk26m",
 264         "univpll_d6_d8"
 265 };
 266
 267 static const char * const spi_parents[] = {
 268         "clk26m",
 269         "mainpll_d5_d4",
 270         "mainpll_d6_d4",
 271         "msdcpll_d4"
 272 };
 273
 274 static const char * const msdc50_0_h_parents[] = {
 275         "clk26m",
 276         "mainpll_d4_d2",
 277         "mainpll_d6_d2"
 278 };
 279
 280 static const char * const msdc50_0_parents[] = {
 281         "clk26m",
 282         "msdcpll_ck",
 283         "msdcpll_d2",
 284         "univpll_d4_d4",
 285         "mainpll_d6_d2",
 286         "univpll_d4_d2"
 287 };
 288
 289 static const char * const msdc30_parents[] = {
 290         "clk26m",
 291         "univpll_d6_d2",
 292         "mainpll_d6_d2",
 293         "mainpll_d7_d2",
 294         "msdcpll_d2"
 295 };
 296
 297 static const char * const audio_parents[] = {
 298         "clk26m",
 299         "mainpll_d5_d8",
 300         "mainpll_d7_d8",
 301         "mainpll_d4_d16"
 302 };
 303
 304 static const char * const aud_intbus_parents[] = {
 305         "clk26m",
 306         "mainpll_d4_d4",
 307         "mainpll_d7_d4"
 308 };
 309
 310 static const char * const pwrap_ulposc_parents[] = {
 311         "osc_d10",
 312         "clk26m",
 313         "osc_d4",
 314         "osc_d8",
 315         "osc_d16"
 316 };
 317
 318 static const char * const atb_parents[] = {
 319         "clk26m",
 320         "mainpll_d4_d2",
 321         "mainpll_d5_d2"
 322 };
 323
 324 static const char * const dpi_parents[] = {
 325         "clk26m",
 326         "tvdpll_d2",
 327         "tvdpll_d4",
 328         "tvdpll_d8",
 329         "tvdpll_d16"
 330 };
 331
 332 static const char * const scam_parents[] = {
 333         "clk26m",
 334         "mainpll_d5_d4"
 335 };
 336
 337 static const char * const disp_pwm_parents[] = {
 338         "clk26m",
 339         "univpll_d6_d4",
 340         "osc_d2",
 341         "osc_d4",
 342         "osc_d16"
 343 };
 344
 345 static const char * const usb_top_parents[] = {
 346         "clk26m",
 347         "univpll_d5_d4",
 348         "univpll_d6_d4",
 349         "univpll_d5_d2"
 350 };
 351
 352 static const char * const ssusb_xhci_parents[] = {
 353         "clk26m",
 354         "univpll_d5_d4",
 355         "univpll_d6_d4",
 356         "univpll_d5_d2"
 357 };
 358
 359 static const char * const i2c_parents[] = {
 360         "clk26m",
 361         "mainpll_d4_d8",
 362         "univpll_d5_d4"
 363 };
 364
 365 static const char * const seninf_parents[] = {
 366         "clk26m",
 367         "univpll_d4_d4",
 368         "univpll_d6_d2",
 369         "univpll_d4_d2",
 370         "univpll_d7",
 371         "univpll_d6",
 372         "mmpll_d6",
 373         "univpll_d5"
 374 };
 375
 376 static const char * const tl_parents[] = {
 377         "clk26m",
 378         "univpll_192m_d2",
 379         "mainpll_d6_d4"
 380 };
 381
 382 static const char * const dxcc_parents[] = {
 383         "clk26m",
 384         "mainpll_d4_d2",
 385         "mainpll_d4_d4",
 386         "mainpll_d4_d8"
 387 };
 388
 389 static const char * const aud_engen1_parents[] = {
 390         "clk26m",
 391         "apll1_d2",
 392         "apll1_d4",
 393         "apll1_d8"
 394 };
 395
 396 static const char * const aud_engen2_parents[] = {
 397         "clk26m",
 398         "apll2_d2",
 399         "apll2_d4",
 400         "apll2_d8"
 401 };
 402
 403 static const char * const aes_ufsfde_parents[] = {
 404         "clk26m",
 405         "mainpll_d4",
 406         "mainpll_d4_d2",
 407         "mainpll_d6",
 408         "mainpll_d4_d4",
 409         "univpll_d4_d2",
 410         "univpll_d6"
 411 };
 412
 413 static const char * const ufs_parents[] = {
 414         "clk26m",
 415         "mainpll_d4_d4",
 416         "mainpll_d4_d8",
 417         "univpll_d4_d4",
 418         "mainpll_d6_d2",
 419         "mainpll_d5_d2",
 420         "msdcpll_d2"
 421 };
 422
 423 static const char * const aud_1_parents[] = {
 424         "clk26m",
 425         "apll1_ck"
 426 };
 427
 428 static const char * const aud_2_parents[] = {
 429         "clk26m",
 430         "apll2_ck"
 431 };
 432
 433 static const char * const adsp_parents[] = {
 434         "clk26m",
 435         "mainpll_d6",
 436         "mainpll_d5_d2",
 437         "univpll_d4_d4",
 438         "univpll_d4",
 439         "univpll_d6",
 440         "ulposc",
 441         "adsppll_ck"
 442 };
 443
 444 static const char * const dpmaif_main_parents[] = {
 445         "clk26m",
 446         "univpll_d4_d4",
 447         "mainpll_d6",
 448         "mainpll_d4_d2",
 449         "univpll_d4_d2"
 450 };
 451
 452 static const char * const venc_parents[] = {
 453         "clk26m",
 454         "mmpll_d7",
 455         "mainpll_d6",
 456         "univpll_d4_d2",
 457         "mainpll_d4_d2",
 458         "univpll_d6",
 459         "mmpll_d6",
 460         "mainpll_d5_d2",
 461         "mainpll_d6_d2",
 462         "mmpll_d9",
 463         "univpll_d4_d4",
 464         "mainpll_d4",
 465         "univpll_d4",
 466         "univpll_d5",
 467         "univpll_d5_d2",
 468         "mainpll_d5"
 469 };
 470
 471 static const char * const vdec_parents[] = {
 472         "clk26m",
 473         "univpll_192m_d2",
 474         "univpll_d5_d4",
 475         "mainpll_d5",
 476         "mainpll_d5_d2",
 477         "mmpll_d6_d2",
 478         "univpll_d5_d2",
 479         "mainpll_d4_d2",
 480         "univpll_d4_d2",
 481         "univpll_d7",
 482         "mmpll_d7",
 483         "mmpll_d6",
 484         "univpll_d5",
 485         "mainpll_d4",
 486         "univpll_d4",
 487         "univpll_d6"
 488 };
 489
 490 static const char * const camtm_parents[] = {
 491         "clk26m",
 492         "univpll_d7",
 493         "univpll_d6_d2",
 494         "univpll_d4_d2"
 495 };
 496
 497 static const char * const pwm_parents[] = {
 498         "clk26m",
 499         "univpll_d4_d8"
 500 };
 501
 502 static const char * const audio_h_parents[] = {
 503         "clk26m",
 504         "univpll_d7",
 505         "apll1_ck",
 506         "apll2_ck"
 507 };
 508
 509 static const char * const spmi_mst_parents[] = {
 510         "clk26m",
 511         "csw_f26m_d2",
 512         "osc_d8",
 513         "osc_d10",
 514         "osc_d16",
 515         "osc_d20",
 516         "clk32k"
 517 };
 518
 519 static const char * const aes_msdcfde_parents[] = {
 520         "clk26m",
 521         "mainpll_d4_d2",
 522         "mainpll_d6",
 523         "mainpll_d4_d4",
 524         "univpll_d4_d2",
 525         "univpll_d6"
 526 };
 527
 528 static const char * const sflash_parents[] = {
 529         "clk26m",
 530         "mainpll_d7_d8",
 531         "univpll_d6_d8",
 532         "univpll_d5_d8"
 533 };
 534
 535 static const char * const apll_i2s_m_parents[] = {
 536         "aud_1_sel",
 537         "aud_2_sel"
 538 };
 539
 540 /*
 541  * CRITICAL CLOCK:
 542  * axi_sel is the main bus clock of whole SOC.
 543  * spm_sel is the clock of the always-on co-processor.
 544  * bus_aximem_sel is clock of the bus that access emi.
 545  */
 546 static const struct mtk_mux top_mtk_muxes[] = {
 547         /* CLK_CFG_0 */
 548         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
 549                                    axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0,
 550                                    CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 551         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
 552                                    spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1,
 553                                    CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 554         MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
 555                              scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2),
 556         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
 557                                    bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3,
 558                                    CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 559         /* CLK_CFG_1 */
 560         MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
 561                              disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),
 562         MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
 563                              mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5),
 564         MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
 565                              img_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
 566         MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
 567                              img_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
 568         /* CLK_CFG_2 */
 569         MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
 570                              ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8),
 571         MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
 572                              dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9),
 573         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
 574                              cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10),
 575         MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
 576                              ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11),
 577         /* CLK_CFG_4 */
 578         MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
 579                              dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
 580         MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
 581                              mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
 582         MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
 583                         mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
 584         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
 585                              camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
 586         /* CLK_CFG_5 */
 587         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
 588                              camtg_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20),
 589         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
 590                              camtg_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21),
 591         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
 592                              camtg_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22),
 593         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
 594                              camtg_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23),
 595         /* CLK_CFG_6 */
 596         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel",
 597                              camtg_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24),
 598         MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
 599                              uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
 600         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
 601                              spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
 602         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
 603                                    msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2,
 604                                    31, 0x004, 27, 0),
 605         /* CLK_CFG_7 */
 606         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
 607                                    msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28, 0),
 608         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
 609                                    msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29, 0),
 610         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
 611                                    msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30, 0),
 612         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
 613                              audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
 614         /* CLK_CFG_8 */
 615         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
 616                              aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1),
 617         MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel",
 618                              pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2),
 619         MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
 620                              atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3),
 621         /* CLK_CFG_9 */
 622         MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
 623                              dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5),
 624         MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel",
 625                              scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6),
 626         MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
 627                              disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7),
 628         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
 629                              usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8),
 630         /* CLK_CFG_10 */
 631         MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
 632                              ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9),
 633         MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
 634                              i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10),
 635         MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
 636                              seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11),
 637         MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
 638                              seninf_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12),
 639         /* CLK_CFG_11 */
 640         MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
 641                              seninf_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13),
 642         MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
 643                              seninf_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14),
 644         MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel",
 645                              tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15),
 646         MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
 647                              dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16),
 648         /* CLK_CFG_12 */
 649         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
 650                              aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17),
 651         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
 652                              aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18),
 653         MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
 654                              aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19),
 655         MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
 656                              ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20),
 657         /* CLK_CFG_13 */
 658         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
 659                              aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21),
 660         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
 661                              aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22),
 662         MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel",
 663                              adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23),
 664         MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel",
 665                              dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24),
 666         /* CLK_CFG_14 */
 667         MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
 668                              venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25),
 669         MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
 670                              vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26),
 671         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
 672                              camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27),
 673         MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
 674                              pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
 675         /* CLK_CFG_15 */
 676         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
 677                              audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29),
 678         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel",
 679                              spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30),
 680         MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
 681                              aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
 682         /* CLK_CFG_16 */
 683         MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
 684                              sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
 685 };
 686
 687 static struct mtk_composite top_muxes[] = {
 688         /* CLK_AUDDIV_0 */
 689         MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s_m_parents, 0x320, 16, 1),
 690         MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s_m_parents, 0x320, 17, 1),
 691         MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s_m_parents, 0x320, 18, 1),
 692         MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s_m_parents, 0x320, 19, 1),
 693         MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s_m_parents, 0x320, 20, 1),
 694         MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s_m_parents, 0x320, 21, 1),
 695         MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s_m_parents, 0x320, 22, 1),
 696         MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320, 23, 1),
 697         MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320, 24, 1),
 698         MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320, 25, 1),
 699         /* APLL_DIV */
 700         DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0),
 701         DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8),
 702         DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16),
 703         DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24),
 704         DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0),
 705         DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8),
 706         DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),
 707         DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24),
 708         DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0),
 709         DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8),
 710         DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16),
 711 };
 712
 713 static const struct mtk_gate_regs infra0_cg_regs = {
 714         .set_ofs = 0x80,
 715         .clr_ofs = 0x84,
 716         .sta_ofs = 0x90,
 717 };
 718
 719 static const struct mtk_gate_regs infra1_cg_regs = {
 720         .set_ofs = 0x88,
 721         .clr_ofs = 0x8c,
 722         .sta_ofs = 0x94,
 723 };
 724
 725 static const struct mtk_gate_regs infra2_cg_regs = {
 726         .set_ofs = 0xa4,
 727         .clr_ofs = 0xa8,
 728         .sta_ofs = 0xac,
 729 };
 730
 731 static const struct mtk_gate_regs infra3_cg_regs = {
 732         .set_ofs = 0xc0,
 733         .clr_ofs = 0xc4,
 734         .sta_ofs = 0xc8,
 735 };
 736
 737 static const struct mtk_gate_regs infra4_cg_regs = {
 738         .set_ofs = 0xd0,
 739         .clr_ofs = 0xd4,
 740         .sta_ofs = 0xd8,
 741 };
 742
 743 static const struct mtk_gate_regs infra5_cg_regs = {
 744         .set_ofs = 0xe0,
 745         .clr_ofs = 0xe4,
 746         .sta_ofs = 0xe8,
 747 };
 748
 749 #define GATE_INFRA0(_id, _name, _parent, _shift)        \
 750         GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 751
 752 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag)           \
 753         GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift,    \
 754                 &mtk_clk_gate_ops_setclr, _flag)
 755
 756 #define GATE_INFRA1(_id, _name, _parent, _shift)        \
 757         GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
 758
 759 #define GATE_INFRA2(_id, _name, _parent, _shift)        \
 760         GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 761
 762 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag)           \
 763         GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift,    \
 764                 &mtk_clk_gate_ops_setclr, _flag)
 765
 766 #define GATE_INFRA3(_id, _name, _parent, _shift)        \
 767         GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
 768
 769 #define GATE_INFRA4(_id, _name, _parent, _shift)        \
 770         GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 771
 772 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag)           \
 773         GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift,    \
 774                 &mtk_clk_gate_ops_setclr, _flag)
 775
 776 #define GATE_INFRA5(_id, _name, _parent, _shift)        \
 777         GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
 778
 779 /*
 780  * CRITICAL CLOCK:
 781  * infra_133m and infra_66m are main peripheral bus clocks of SOC.
 782  * infra_device_apc and infra_device_apc_sync are for device access permission control module.
 783  */
 784 static const struct mtk_gate infra_clks[] = {
 785         /* INFRA0 */
 786         GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0),
 787         GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1),
 788         GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2),
 789         GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3),
 790         GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
 791         GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
 792         GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
 793         GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
 794         GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
 795         GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
 796         GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11),
 797         GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12),
 798         GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13),
 799         GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14),
 800         GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15),
 801         GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16),
 802         GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17),
 803         GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18),
 804         GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19),
 805         GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21),
 806         GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
 807         GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
 808         GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
 809         GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
 810         GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27),
 811         GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28),
 812         GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
 813         /* INFRA1 */
 814         GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1),
 815         GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2),
 816         GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4),
 817         GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5),
 818         GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6),
 819         GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
 820         GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
 821         GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
 822         GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
 823         GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12),
 824         GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13),
 825         GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14),
 826         GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15),
 827         GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16),
 828         GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17),
 829         GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18),
 830         GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19),
 831         GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL),
 832         GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
 833         GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24),
 834         GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
 835         GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
 836         GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27),
 837         GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28),
 838         GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29),
 839         GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30),
 840         GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
 841         /* INFRA2 */
 842         GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0),
 843         GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1),
 844         GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2),
 845         GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3),
 846         GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4),
 847         GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5),
 848         GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6),
 849         GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7),
 850         GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9),
 851         GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10),
 852         GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11),
 853         GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12),
 854         GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13),
 855         GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14),
 856         GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
 857         GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
 858         GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
 859         GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
 860         GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21),
 861         GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22),
 862         GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23),
 863         GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24),
 864         GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25),
 865         GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26),
 866         GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27),
 867         GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28),
 868         GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29),
 869         GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30),
 870         GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31),
 871         /* INFRA3 */
 872         GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
 873         GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
 874         GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
 875         GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
 876         GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
 877         GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7),
 878         GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8),
 879         GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9),
 880         GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10),
 881         GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11),
 882         GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14),
 883         GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15),
 884         GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16),
 885         GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17),
 886         GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18),
 887         GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19),
 888         GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20),
 889         GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21),
 890         GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22),
 891         GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23),
 892         GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24),
 893         GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25,
 894                           CLK_IS_CRITICAL),
 895         GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26),
 896         GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27),
 897         GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28),
 898         GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29),
 899         GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30),
 900         GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31),
 901         /* INFRA4 */
 902         GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31),
 903         /* INFRA5 */
 904         GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL),
 905         GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL),
 906         GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2),
 907         GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3),
 908         GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4),
 909         GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5),
 910         GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6),
 911         GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30),
 912         GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31),
 913 };
 914
 915 static const struct mtk_gate_regs peri_cg_regs = {
 916         .set_ofs = 0x20c,
 917         .clr_ofs = 0x20c,
 918         .sta_ofs = 0x20c,
 919 };
 920
 921 #define GATE_PERI(_id, _name, _parent, _shift)  \
 922         GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
 923
 924 static const struct mtk_gate peri_clks[] = {
 925         GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31),
 926 };
 927
 928 static const struct mtk_gate_regs top_cg_regs = {
 929         .set_ofs = 0x150,
 930         .clr_ofs = 0x150,
 931         .sta_ofs = 0x150,
 932 };
 933
 934 #define GATE_TOP(_id, _name, _parent, _shift)   \
 935         GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
 936
 937 static const struct mtk_gate top_clks[] = {
 938         GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24),
 939         GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
 940 };
 941
 942 static u16 infra_ao_rst_ofs[] = {
 943         INFRA_RST0_SET_OFFSET,
 944         INFRA_RST1_SET_OFFSET,
 945         INFRA_RST2_SET_OFFSET,
 946         INFRA_RST3_SET_OFFSET,
 947         INFRA_RST4_SET_OFFSET,
 948 };
 949
 950 static u16 infra_ao_idx_map[] = {
 951         [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
 952         [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
 953         [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
 954         [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
 955         [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
 956 };
 957
 958 static const struct mtk_clk_rst_desc clk_rst_desc = {
 959         .version = MTK_RST_SET_CLR,
 960         .rst_bank_ofs = infra_ao_rst_ofs,
 961         .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
 962         .rst_idx_map = infra_ao_idx_map,
 963         .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
 964 };
 965
 966 /* Register mux notifier for MFG mux */
 967 static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
 968 {
 969         struct mtk_mux_nb *mfg_mux_nb;
 970         int i;
 971
 972         mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
 973         if (!mfg_mux_nb)
 974                 return -ENOMEM;
 975
 976         for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++)
 977                 if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL)
 978                         break;
 979         if (i == ARRAY_SIZE(top_mtk_muxes))
 980                 return -EINVAL;
 981
 982         mfg_mux_nb->ops = top_mtk_muxes[i].ops;
 983         mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
 984
 985         return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
 986 }
 987
 988 static const struct mtk_clk_desc infra_desc = {
 989         .clks = infra_clks,
 990         .num_clks = ARRAY_SIZE(infra_clks),
 991         .rst_desc = &clk_rst_desc,
 992 };
 993
 994 static const struct mtk_clk_desc peri_desc = {
 995         .clks = peri_clks,
 996         .num_clks = ARRAY_SIZE(peri_clks),
 997 };
 998
 999 static const struct mtk_clk_desc topck_desc = {
1000         .fixed_clks = top_fixed_clks,
1001         .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
1002         .factor_clks = top_divs,
1003         .num_factor_clks = ARRAY_SIZE(top_divs),
1004         .mux_clks = top_mtk_muxes,
1005         .num_mux_clks = ARRAY_SIZE(top_mtk_muxes),
1006         .composite_clks = top_muxes,
1007         .num_composite_clks = ARRAY_SIZE(top_muxes),
1008         .clks = top_clks,
1009         .num_clks = ARRAY_SIZE(top_clks),
1010         .clk_lock = &mt8192_clk_lock,
1011         .clk_notifier_func = clk_mt8192_reg_mfg_mux_notifier,
1012         .mfg_clk_idx = CLK_TOP_MFG_PLL_SEL,
1013 };
1014
1015 static const struct of_device_id of_match_clk_mt8192[] = {
1016         { .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc },
1017         { .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc },
1018         { .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc },
1019         { /* sentinel */ }
1020 };
1021 MODULE_DEVICE_TABLE(of, of_match_clk_mt8192);
1022
1023 static struct platform_driver clk_mt8192_drv = {
1024         .driver = {
1025                 .name = "clk-mt8192",
1026                 .of_match_table = of_match_clk_mt8192,
1027         },
1028         .probe = mtk_clk_simple_probe,
1029         .remove = mtk_clk_simple_remove,
1030 };
1031 module_platform_driver(clk_mt8192_drv);
1032
1033 MODULE_DESCRIPTION("MediaTek MT8192 main clocks driver");
1034 MODULE_LICENSE("GPL");