1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
39 struct mtk_pllfh_data
{
40 struct fh_pll_state state
;
41 const struct fh_pll_data data
;
45 void __iomem
*reg_hp_en
;
46 void __iomem
*reg_clk_con
;
47 void __iomem
*reg_rst_con
;
48 void __iomem
*reg_slope0
;
49 void __iomem
*reg_slope1
;
50 void __iomem
*reg_cfg
;
51 void __iomem
*reg_updnlmt
;
52 void __iomem
*reg_dds
;
53 void __iomem
*reg_dvfs
;
54 void __iomem
*reg_mon
;
58 struct mtk_clk_pll clk_pll
;
59 struct fh_pll_regs regs
;
60 struct mtk_pllfh_data
*pllfh_data
;
61 const struct fh_operation
*ops
;
66 int (*hopping
)(struct mtk_fh
*fh
, unsigned int new_dds
,
67 unsigned int postdiv
);
68 int (*ssc_enable
)(struct mtk_fh
*fh
, u32 rate
);
71 int mtk_clk_register_pllfhs(struct device_node
*node
,
72 const struct mtk_pll_data
*plls
, int num_plls
,
73 struct mtk_pllfh_data
*pllfhs
, int num_pllfhs
,
74 struct clk_hw_onecell_data
*clk_data
);
76 void mtk_clk_unregister_pllfhs(const struct mtk_pll_data
*plls
, int num_plls
,
77 struct mtk_pllfh_data
*pllfhs
, int num_fhs
,
78 struct clk_hw_onecell_data
*clk_data
);
80 void fhctl_parse_dt(const u8
*compatible_node
, struct mtk_pllfh_data
*pllfhs
,
83 #endif /* __CLK_PLLFH_H */