drivers/clk/meson/a1-pll.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Amlogic A1 PLL Clock Controller internals
   4  *
   5  * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
   6  * Author: Jian Hu <jian.hu@amlogic.com>
   7  *
   8  * Copyright (c) 2023, SberDevices. All Rights Reserved.
   9  * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
  10  */
  11
  12 #ifndef __A1_PLL_H
  13 #define __A1_PLL_H
  14
  15 #include "clk-pll.h"
  16
  17 /* PLL register offset */
  18 #define ANACTRL_FIXPLL_CTRL0    0x0
  19 #define ANACTRL_FIXPLL_CTRL1    0x4
  20 #define ANACTRL_FIXPLL_STS      0x14
  21 #define ANACTRL_HIFIPLL_CTRL0   0xc0
  22 #define ANACTRL_HIFIPLL_CTRL1   0xc4
  23 #define ANACTRL_HIFIPLL_CTRL2   0xc8
  24 #define ANACTRL_HIFIPLL_CTRL3   0xcc
  25 #define ANACTRL_HIFIPLL_CTRL4   0xd0
  26 #define ANACTRL_HIFIPLL_STS     0xd4
  27
  28 #endif /* __A1_PLL_H */