drivers/clk/mmp/clk-of-pxa910.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * pxa910 clock framework source file
   4  *
   5  * Copyright (C) 2012 Marvell
   6  * Chao Xie <xiechao.mail@gmail.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/spinlock.h>
  12 #include <linux/io.h>
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/of_address.h>
  16
  17 #include <dt-bindings/clock/marvell,pxa910.h>
  18
  19 #include "clk.h"
  20 #include "reset.h"
  21
  22 #define APBC_RTC        0x28
  23 #define APBC_TWSI0      0x2c
  24 #define APBC_KPC        0x18
  25 #define APBC_UART0      0x0
  26 #define APBC_UART1      0x4
  27 #define APBC_GPIO       0x8
  28 #define APBC_PWM0       0xc
  29 #define APBC_PWM1       0x10
  30 #define APBC_PWM2       0x14
  31 #define APBC_PWM3       0x18
  32 #define APBC_SSP0       0x1c
  33 #define APBC_SSP1       0x20
  34 #define APBC_SSP2       0x4c
  35 #define APBC_TIMER0     0x30
  36 #define APBC_TIMER1     0x44
  37 #define APBCP_TWSI1     0x28
  38 #define APBCP_UART2     0x1c
  39 #define APMU_SDH0       0x54
  40 #define APMU_SDH1       0x58
  41 #define APMU_USB        0x5c
  42 #define APMU_DISP0      0x4c
  43 #define APMU_CCIC0      0x50
  44 #define APMU_DFC        0x60
  45 #define MPMU_UART_PLL   0x14
  46
  47 #define NR_CLKS         200
  48
  49 struct pxa910_clk_unit {
  50         struct mmp_clk_unit unit;
  51         void __iomem *mpmu_base;
  52         void __iomem *apmu_base;
  53         void __iomem *apbc_base;
  54         void __iomem *apbcp_base;
  55 };
  56
  57 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
  58         {PXA910_CLK_CLK32, "clk32", NULL, 0, 32768},
  59         {PXA910_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
  60         {PXA910_CLK_PLL1, "pll1", NULL, 0, 624000000},
  61         {PXA910_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
  62 };
  63
  64 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
  65         {PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
  66         {PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
  67         {PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
  68         {PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
  69         {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
  70         {PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
  71         {PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
  72         {PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
  73         {PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
  74         {PXA910_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
  75         {PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
  76         {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
  77         {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
  78         {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
  79 };
  80
  81 static struct mmp_clk_factor_masks uart_factor_masks = {
  82         .factor = 2,
  83         .num_mask = 0x1fff,
  84         .den_mask = 0x1fff,
  85         .num_shift = 16,
  86         .den_shift = 0,
  87 };
  88
  89 static struct u32_fract uart_factor_tbl[] = {
  90         { .numerator = 8125, .denominator = 1536 },     /* 14.745MHZ */
  91 };
  92
  93 static void pxa910_pll_init(struct pxa910_clk_unit *pxa_unit)
  94 {
  95         struct clk *clk;
  96         struct mmp_clk_unit *unit = &pxa_unit->unit;
  97
  98         mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
  99                                         ARRAY_SIZE(fixed_rate_clks));
 100
 101         mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
 102                                         ARRAY_SIZE(fixed_factor_clks));
 103
 104         clk = mmp_clk_register_factor("uart_pll", "pll1_4",
 105                                 CLK_SET_RATE_PARENT,
 106                                 pxa_unit->mpmu_base + MPMU_UART_PLL,
 107                                 &uart_factor_masks, uart_factor_tbl,
 108                                 ARRAY_SIZE(uart_factor_tbl), NULL);
 109         mmp_clk_add(unit, PXA910_CLK_UART_PLL, clk);
 110 }
 111
 112 static DEFINE_SPINLOCK(uart0_lock);
 113 static DEFINE_SPINLOCK(uart1_lock);
 114 static DEFINE_SPINLOCK(uart2_lock);
 115 static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"};
 116
 117 static DEFINE_SPINLOCK(ssp0_lock);
 118 static DEFINE_SPINLOCK(ssp1_lock);
 119 static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
 120
 121 static DEFINE_SPINLOCK(timer0_lock);
 122 static DEFINE_SPINLOCK(timer1_lock);
 123 static const char *timer_parent_names[] = {"pll1_48", "clk32", "pll1_96"};
 124
 125 static DEFINE_SPINLOCK(reset_lock);
 126
 127 static struct mmp_param_mux_clk apbc_mux_clks[] = {
 128         {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
 129         {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
 130         {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
 131         {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
 132         {0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER0, 4, 3, 0, &timer0_lock},
 133         {0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER1, 4, 3, 0, &timer1_lock},
 134 };
 135
 136 static struct mmp_param_mux_clk apbcp_mux_clks[] = {
 137         {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART2, 4, 3, 0, &uart2_lock},
 138 };
 139
 140 static struct mmp_param_gate_clk apbc_gate_clks[] = {
 141         {PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
 142         {PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
 143         {PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
 144         {PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
 145         {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
 146         {PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
 147         {PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
 148         {PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
 149         /* The gate clocks has mux parent. */
 150         {PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &uart0_lock},
 151         {PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &uart1_lock},
 152         {PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
 153         {PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_lock},
 154         {PXA910_CLK_TIMER0, "timer0_clk", "timer0_mux", CLK_SET_RATE_PARENT, APBC_TIMER0, 0x3, 0x3, 0x0, 0, &timer0_lock},
 155         {PXA910_CLK_TIMER1, "timer1_clk", "timer1_mux", CLK_SET_RATE_PARENT, APBC_TIMER1, 0x3, 0x3, 0x0, 0, &timer1_lock},
 156 };
 157
 158 static struct mmp_param_gate_clk apbcp_gate_clks[] = {
 159         {PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
 160         /* The gate clocks has mux parent. */
 161         {PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
 162 };
 163
 164 static void pxa910_apb_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
 165 {
 166         struct mmp_clk_unit *unit = &pxa_unit->unit;
 167
 168         mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
 169                                 ARRAY_SIZE(apbc_mux_clks));
 170
 171         mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
 172                                 ARRAY_SIZE(apbcp_mux_clks));
 173
 174         mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
 175                                 ARRAY_SIZE(apbc_gate_clks));
 176
 177         mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
 178                                 ARRAY_SIZE(apbcp_gate_clks));
 179 }
 180
 181 static DEFINE_SPINLOCK(sdh0_lock);
 182 static DEFINE_SPINLOCK(sdh1_lock);
 183 static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"};
 184
 185 static DEFINE_SPINLOCK(usb_lock);
 186
 187 static DEFINE_SPINLOCK(disp0_lock);
 188 static const char *disp_parent_names[] = {"pll1_2", "pll1_12"};
 189
 190 static DEFINE_SPINLOCK(ccic0_lock);
 191 static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"};
 192 static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"};
 193
 194 static struct mmp_param_mux_clk apmu_mux_clks[] = {
 195         {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock},
 196         {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock},
 197         {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock},
 198         {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock},
 199         {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock},
 200 };
 201
 202 static struct mmp_param_div_clk apmu_div_clks[] = {
 203         {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
 204 };
 205
 206 static struct mmp_param_gate_clk apmu_gate_clks[] = {
 207         {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
 208         {PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
 209         {PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
 210         /* The gate clocks has mux parent. */
 211         {PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},
 212         {PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh1_lock},
 213         {PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
 214         {PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
 215         {PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
 216         {PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
 217 };
 218
 219 static void pxa910_axi_periph_clk_init(struct pxa910_clk_unit *pxa_unit)
 220 {
 221         struct mmp_clk_unit *unit = &pxa_unit->unit;
 222
 223         mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
 224                                 ARRAY_SIZE(apmu_mux_clks));
 225
 226         mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
 227                                 ARRAY_SIZE(apmu_div_clks));
 228
 229         mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
 230                                 ARRAY_SIZE(apmu_gate_clks));
 231 }
 232
 233 static void pxa910_clk_reset_init(struct device_node *np,
 234                                 struct pxa910_clk_unit *pxa_unit)
 235 {
 236         struct mmp_clk_reset_cell *cells;
 237         int i, base, nr_resets_apbc, nr_resets_apbcp, nr_resets;
 238
 239         nr_resets_apbc = ARRAY_SIZE(apbc_gate_clks);
 240         nr_resets_apbcp = ARRAY_SIZE(apbcp_gate_clks);
 241         nr_resets = nr_resets_apbc + nr_resets_apbcp;
 242         cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
 243         if (!cells)
 244                 return;
 245
 246         base = 0;
 247         for (i = 0; i < nr_resets_apbc; i++) {
 248                 cells[base + i].clk_id = apbc_gate_clks[i].id;
 249                 cells[base + i].reg =
 250                         pxa_unit->apbc_base + apbc_gate_clks[i].offset;
 251                 cells[base + i].flags = 0;
 252                 cells[base + i].lock = apbc_gate_clks[i].lock;
 253                 cells[base + i].bits = 0x4;
 254         }
 255
 256         base = nr_resets_apbc;
 257         for (i = 0; i < nr_resets_apbcp; i++) {
 258                 cells[base + i].clk_id = apbcp_gate_clks[i].id;
 259                 cells[base + i].reg =
 260                         pxa_unit->apbc_base + apbc_gate_clks[i].offset;
 261                 cells[base + i].flags = 0;
 262                 cells[base + i].lock = apbc_gate_clks[i].lock;
 263                 cells[base + i].bits = 0x4;
 264         }
 265
 266         mmp_clk_reset_register(np, cells, nr_resets);
 267 }
 268
 269 static void __init pxa910_clk_init(struct device_node *np)
 270 {
 271         struct pxa910_clk_unit *pxa_unit;
 272
 273         pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
 274         if (!pxa_unit)
 275                 return;
 276
 277         pxa_unit->mpmu_base = of_iomap(np, 0);
 278         if (!pxa_unit->mpmu_base) {
 279                 pr_err("failed to map mpmu registers\n");
 280                 goto free_memory;
 281         }
 282
 283         pxa_unit->apmu_base = of_iomap(np, 1);
 284         if (!pxa_unit->apmu_base) {
 285                 pr_err("failed to map apmu registers\n");
 286                 goto unmap_mpmu_region;
 287         }
 288
 289         pxa_unit->apbc_base = of_iomap(np, 2);
 290         if (!pxa_unit->apbc_base) {
 291                 pr_err("failed to map apbc registers\n");
 292                 goto unmap_apmu_region;
 293         }
 294
 295         pxa_unit->apbcp_base = of_iomap(np, 3);
 296         if (!pxa_unit->apbcp_base) {
 297                 pr_err("failed to map apbcp registers\n");
 298                 goto unmap_apbc_region;
 299         }
 300
 301         mmp_clk_init(np, &pxa_unit->unit, NR_CLKS);
 302
 303         pxa910_pll_init(pxa_unit);
 304
 305         pxa910_apb_periph_clk_init(pxa_unit);
 306
 307         pxa910_axi_periph_clk_init(pxa_unit);
 308
 309         pxa910_clk_reset_init(np, pxa_unit);
 310
 311         return;
 312
 313 unmap_apbc_region:
 314         iounmap(pxa_unit->apbc_base);
 315 unmap_apmu_region:
 316         iounmap(pxa_unit->apmu_base);
 317 unmap_mpmu_region:
 318         iounmap(pxa_unit->mpmu_base);
 319 free_memory:
 320         kfree(pxa_unit);
 321 }
 322
 323 CLK_OF_DECLARE(pxa910_clk, "marvell,pxa910-clock", pxa910_clk_init);