drivers/clk/qcom/clk-regmap-phy-mux.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2022, Linaro Ltd.
   4  */
   5
   6 #ifndef __QCOM_CLK_REGMAP_PHY_MUX_H__
   7 #define __QCOM_CLK_REGMAP_PHY_MUX_H__
   8
   9 #include "clk-regmap.h"
  10
  11 /*
  12  * A clock implementation for PHY pipe and symbols clock muxes.
  13  *
  14  * If the clock is running off the from-PHY source, report it as enabled.
  15  * Report it as disabled otherwise (if it uses reference source).
  16  *
  17  * This way the PHY will disable the pipe clock before turning off the GDSC,
  18  * which in turn would lead to disabling corresponding pipe_clk_src (and thus
  19  * it being parked to a safe, reference clock source). And vice versa, after
  20  * enabling the GDSC the PHY will enable the pipe clock, which would cause
  21  * pipe_clk_src to be switched from a safe source to the working one.
  22  *
  23  * For some platforms this should be used for the UFS symbol_clk_src clocks
  24  * too.
  25  */
  26 struct clk_regmap_phy_mux {
  27         u32                     reg;
  28         struct clk_regmap       clkr;
  29 };
  30
  31 extern const struct clk_ops clk_regmap_phy_mux_ops;
  32
  33 #endif