drivers/clk/qcom/clk-rpmh.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/err.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/platform_device.h>
  12 #include <soc/qcom/cmd-db.h>
  13 #include <soc/qcom/rpmh.h>
  14 #include <soc/qcom/tcs.h>
  15
  16 #include <dt-bindings/clock/qcom,rpmh.h>
  17
  18 #define CLK_RPMH_ARC_EN_OFFSET          0
  19 #define CLK_RPMH_VRM_EN_OFFSET          4
  20
  21 /**
  22  * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
  23  * @unit: divisor used to convert Hz value to an RPMh msg
  24  * @width: multiplier used to convert Hz value to an RPMh msg
  25  * @vcd: virtual clock domain that this bcm belongs to
  26  * @reserved: reserved to pad the struct
  27  */
  28 struct bcm_db {
  29         __le32 unit;
  30         __le16 width;
  31         u8 vcd;
  32         u8 reserved;
  33 };
  34
  35 /**
  36  * struct clk_rpmh - individual rpmh clock data structure
  37  * @hw:                 handle between common and hardware-specific interfaces
  38  * @res_name:           resource name for the rpmh clock
  39  * @div:                clock divider to compute the clock rate
  40  * @res_addr:           base address of the rpmh resource within the RPMh
  41  * @res_on_val:         rpmh clock enable value
  42  * @state:              rpmh clock requested state
  43  * @aggr_state:         rpmh clock aggregated state
  44  * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
  45  * @valid_state_mask:   mask to determine the state of the rpmh clock
  46  * @unit:               divisor to convert rate to rpmh msg in magnitudes of Khz
  47  * @dev:                device to which it is attached
  48  * @peer:               pointer to the clock rpmh sibling
  49  */
  50 struct clk_rpmh {
  51         struct clk_hw hw;
  52         const char *res_name;
  53         u8 div;
  54         u32 res_addr;
  55         u32 res_on_val;
  56         u32 state;
  57         u32 aggr_state;
  58         u32 last_sent_aggr_state;
  59         u32 valid_state_mask;
  60         u32 unit;
  61         struct device *dev;
  62         struct clk_rpmh *peer;
  63 };
  64
  65 struct clk_rpmh_desc {
  66         struct clk_hw **clks;
  67         size_t num_clks;
  68 };
  69
  70 static DEFINE_MUTEX(rpmh_clk_lock);
  71
  72 #define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name,                  \
  73                           _res_en_offset, _res_on, _div)                \
  74         static struct clk_rpmh clk_rpmh_##_clk_name##_ao;               \
  75         static struct clk_rpmh clk_rpmh_##_clk_name = {                 \
  76                 .res_name = _res_name,                                  \
  77                 .res_addr = _res_en_offset,                             \
  78                 .res_on_val = _res_on,                                  \
  79                 .div = _div,                                            \
  80                 .peer = &clk_rpmh_##_clk_name##_ao,                     \
  81                 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |        \
  82                                       BIT(RPMH_ACTIVE_ONLY_STATE) |     \
  83                                       BIT(RPMH_SLEEP_STATE)),           \
  84                 .hw.init = &(struct clk_init_data){                     \
  85                         .ops = &clk_rpmh_ops,                           \
  86                         .name = #_name,                                 \
  87                         .parent_data =  &(const struct clk_parent_data){ \
  88                                         .fw_name = "xo",                \
  89                                         .name = "xo_board",             \
  90                         },                                              \
  91                         .num_parents = 1,                               \
  92                 },                                                      \
  93         };                                                              \
  94         static struct clk_rpmh clk_rpmh_##_clk_name##_ao= {             \
  95                 .res_name = _res_name,                                  \
  96                 .res_addr = _res_en_offset,                             \
  97                 .res_on_val = _res_on,                                  \
  98                 .div = _div,                                            \
  99                 .peer = &clk_rpmh_##_clk_name,                          \
 100                 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |        \
 101                                         BIT(RPMH_ACTIVE_ONLY_STATE)),   \
 102                 .hw.init = &(struct clk_init_data){                     \
 103                         .ops = &clk_rpmh_ops,                           \
 104                         .name = #_name "_ao",                           \
 105                         .parent_data =  &(const struct clk_parent_data){ \
 106                                         .fw_name = "xo",                \
 107                                         .name = "xo_board",             \
 108                         },                                              \
 109                         .num_parents = 1,                               \
 110                 },                                                      \
 111         }
 112
 113 #define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div)            \
 114         __DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name,        \
 115                           CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
 116
 117 #define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div)            \
 118         __DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name,             \
 119                           CLK_RPMH_VRM_EN_OFFSET, 1, _div)
 120
 121 #define DEFINE_CLK_RPMH_BCM(_name, _res_name)                           \
 122         static struct clk_rpmh clk_rpmh_##_name = {                     \
 123                 .res_name = _res_name,                                  \
 124                 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE),        \
 125                 .div = 1,                                               \
 126                 .hw.init = &(struct clk_init_data){                     \
 127                         .ops = &clk_rpmh_bcm_ops,                       \
 128                         .name = #_name,                                 \
 129                 },                                                      \
 130         }
 131
 132 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
 133 {
 134         return container_of(_hw, struct clk_rpmh, hw);
 135 }
 136
 137 static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
 138 {
 139         return (c->last_sent_aggr_state & BIT(state))
 140                 != (c->aggr_state & BIT(state));
 141 }
 142
 143 static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state,
 144                          struct tcs_cmd *cmd, bool wait)
 145 {
 146         if (wait)
 147                 return rpmh_write(c->dev, state, cmd, 1);
 148
 149         return rpmh_write_async(c->dev, state, cmd, 1);
 150 }
 151
 152 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
 153 {
 154         struct tcs_cmd cmd = { 0 };
 155         u32 cmd_state, on_val;
 156         enum rpmh_state state = RPMH_SLEEP_STATE;
 157         int ret;
 158         bool wait;
 159
 160         cmd.addr = c->res_addr;
 161         cmd_state = c->aggr_state;
 162         on_val = c->res_on_val;
 163
 164         for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
 165                 if (has_state_changed(c, state)) {
 166                         if (cmd_state & BIT(state))
 167                                 cmd.data = on_val;
 168
 169                         wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE;
 170                         ret = clk_rpmh_send(c, state, &cmd, wait);
 171                         if (ret) {
 172                                 dev_err(c->dev, "set %s state of %s failed: (%d)\n",
 173                                         !state ? "sleep" :
 174                                         state == RPMH_WAKE_ONLY_STATE   ?
 175                                         "wake" : "active", c->res_name, ret);
 176                                 return ret;
 177                         }
 178                 }
 179         }
 180
 181         c->last_sent_aggr_state = c->aggr_state;
 182         c->peer->last_sent_aggr_state =  c->last_sent_aggr_state;
 183
 184         return 0;
 185 }
 186
 187 /*
 188  * Update state and aggregate state values based on enable value.
 189  */
 190 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
 191                                                 bool enable)
 192 {
 193         int ret;
 194
 195         c->state = enable ? c->valid_state_mask : 0;
 196         c->aggr_state = c->state | c->peer->state;
 197         c->peer->aggr_state = c->aggr_state;
 198
 199         ret = clk_rpmh_send_aggregate_command(c);
 200         if (!ret)
 201                 return 0;
 202
 203         if (ret && enable)
 204                 c->state = 0;
 205         else if (ret)
 206                 c->state = c->valid_state_mask;
 207
 208         WARN(1, "clk: %s failed to %s\n", c->res_name,
 209              enable ? "enable" : "disable");
 210         return ret;
 211 }
 212
 213 static int clk_rpmh_prepare(struct clk_hw *hw)
 214 {
 215         struct clk_rpmh *c = to_clk_rpmh(hw);
 216         int ret = 0;
 217
 218         mutex_lock(&rpmh_clk_lock);
 219         ret = clk_rpmh_aggregate_state_send_command(c, true);
 220         mutex_unlock(&rpmh_clk_lock);
 221
 222         return ret;
 223 }
 224
 225 static void clk_rpmh_unprepare(struct clk_hw *hw)
 226 {
 227         struct clk_rpmh *c = to_clk_rpmh(hw);
 228
 229         mutex_lock(&rpmh_clk_lock);
 230         clk_rpmh_aggregate_state_send_command(c, false);
 231         mutex_unlock(&rpmh_clk_lock);
 232 };
 233
 234 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
 235                                         unsigned long prate)
 236 {
 237         struct clk_rpmh *r = to_clk_rpmh(hw);
 238
 239         /*
 240          * RPMh clocks have a fixed rate. Return static rate.
 241          */
 242         return prate / r->div;
 243 }
 244
 245 static const struct clk_ops clk_rpmh_ops = {
 246         .prepare        = clk_rpmh_prepare,
 247         .unprepare      = clk_rpmh_unprepare,
 248         .recalc_rate    = clk_rpmh_recalc_rate,
 249 };
 250
 251 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
 252 {
 253         struct tcs_cmd cmd = { 0 };
 254         u32 cmd_state;
 255         int ret = 0;
 256
 257         mutex_lock(&rpmh_clk_lock);
 258         if (enable) {
 259                 cmd_state = 1;
 260                 if (c->aggr_state)
 261                         cmd_state = c->aggr_state;
 262         } else {
 263                 cmd_state = 0;
 264         }
 265
 266         cmd_state = min(cmd_state, BCM_TCS_CMD_VOTE_MASK);
 267
 268         if (c->last_sent_aggr_state != cmd_state) {
 269                 cmd.addr = c->res_addr;
 270                 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
 271
 272                 /*
 273                  * Send only an active only state request. RPMh continues to
 274                  * use the active state when we're in sleep/wake state as long
 275                  * as the sleep/wake state has never been set.
 276                  */
 277                 ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable);
 278                 if (ret) {
 279                         dev_err(c->dev, "set active state of %s failed: (%d)\n",
 280                                 c->res_name, ret);
 281                 } else {
 282                         c->last_sent_aggr_state = cmd_state;
 283                 }
 284         }
 285
 286         mutex_unlock(&rpmh_clk_lock);
 287
 288         return ret;
 289 }
 290
 291 static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
 292 {
 293         struct clk_rpmh *c = to_clk_rpmh(hw);
 294
 295         return clk_rpmh_bcm_send_cmd(c, true);
 296 }
 297
 298 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
 299 {
 300         struct clk_rpmh *c = to_clk_rpmh(hw);
 301
 302         clk_rpmh_bcm_send_cmd(c, false);
 303 }
 304
 305 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
 306                                  unsigned long parent_rate)
 307 {
 308         struct clk_rpmh *c = to_clk_rpmh(hw);
 309
 310         c->aggr_state = rate / c->unit;
 311         /*
 312          * Since any non-zero value sent to hw would result in enabling the
 313          * clock, only send the value if the clock has already been prepared.
 314          */
 315         if (clk_hw_is_prepared(hw))
 316                 clk_rpmh_bcm_send_cmd(c, true);
 317
 318         return 0;
 319 }
 320
 321 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
 322                                 unsigned long *parent_rate)
 323 {
 324         return rate;
 325 }
 326
 327 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
 328                                         unsigned long prate)
 329 {
 330         struct clk_rpmh *c = to_clk_rpmh(hw);
 331
 332         return c->aggr_state * c->unit;
 333 }
 334
 335 static const struct clk_ops clk_rpmh_bcm_ops = {
 336         .prepare        = clk_rpmh_bcm_prepare,
 337         .unprepare      = clk_rpmh_bcm_unprepare,
 338         .set_rate       = clk_rpmh_bcm_set_rate,
 339         .round_rate     = clk_rpmh_round_rate,
 340         .recalc_rate    = clk_rpmh_bcm_recalc_rate,
 341 };
 342
 343 /* Resource name must match resource id present in cmd-db */
 344 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1);
 345 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
 346 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
 347 DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
 348
 349 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
 350 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
 351 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
 352
 353 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);
 354 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);
 355 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a4, "lnbclka3", 4);
 356
 357 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);
 358 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
 359
 360 DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1);
 361 DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1);
 362 DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1);
 363 DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1);
 364 DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1);
 365
 366 DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1);
 367 DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
 368 DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
 369 DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
 370
 371 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
 372 DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
 373 DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
 374 DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);
 375 DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
 376
 377 DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2);
 378 DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2);
 379 DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2);
 380 DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);
 381 DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2);
 382 DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2);
 383
 384 DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
 385
 386 DEFINE_CLK_RPMH_BCM(ce, "CE0");
 387 DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
 388 DEFINE_CLK_RPMH_BCM(ipa, "IP0");
 389 DEFINE_CLK_RPMH_BCM(pka, "PKA0");
 390 DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
 391
 392 static struct clk_hw *sar2130p_rpmh_clocks[] = {
 393         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div1.hw,
 394         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div1_ao.hw,
 395         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 396         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 397 };
 398
 399 static const struct clk_rpmh_desc clk_rpmh_sar2130p = {
 400         .clks = sar2130p_rpmh_clocks,
 401         .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks),
 402 };
 403
 404 static struct clk_hw *sdm845_rpmh_clocks[] = {
 405         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 406         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 407         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a2.hw,
 408         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
 409         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a2.hw,
 410         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
 411         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 412         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 413         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_a.hw,
 414         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_a_ao.hw,
 415         [RPMH_RF_CLK3]          = &clk_rpmh_rf_clk3_a.hw,
 416         [RPMH_RF_CLK3_A]        = &clk_rpmh_rf_clk3_a_ao.hw,
 417         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 418         [RPMH_CE_CLK]           = &clk_rpmh_ce.hw,
 419 };
 420
 421 static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
 422         .clks = sdm845_rpmh_clocks,
 423         .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
 424 };
 425
 426 static struct clk_hw *sa8775p_rpmh_clocks[] = {
 427         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 428         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 429         [RPMH_LN_BB_CLK1]       = &clk_rpmh_ln_bb_clk1_a2.hw,
 430         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a2.hw,
 431         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
 432         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 433         [RPMH_PKA_CLK]          = &clk_rpmh_pka.hw,
 434         [RPMH_HWKM_CLK]         = &clk_rpmh_hwkm.hw,
 435 };
 436
 437 static const struct clk_rpmh_desc clk_rpmh_sa8775p = {
 438         .clks = sa8775p_rpmh_clocks,
 439         .num_clks = ARRAY_SIZE(sa8775p_rpmh_clocks),
 440 };
 441
 442 static struct clk_hw *sdm670_rpmh_clocks[] = {
 443         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 444         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 445         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a2.hw,
 446         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
 447         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a2.hw,
 448         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
 449         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 450         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 451         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_a.hw,
 452         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_a_ao.hw,
 453         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 454         [RPMH_CE_CLK]           = &clk_rpmh_ce.hw,
 455 };
 456
 457 static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
 458         .clks = sdm670_rpmh_clocks,
 459         .num_clks = ARRAY_SIZE(sdm670_rpmh_clocks),
 460 };
 461
 462 static struct clk_hw *sdx55_rpmh_clocks[] = {
 463         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 464         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 465         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_d.hw,
 466         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_d_ao.hw,
 467         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_d.hw,
 468         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_d_ao.hw,
 469         [RPMH_QPIC_CLK]         = &clk_rpmh_qpic_clk.hw,
 470         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 471 };
 472
 473 static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
 474         .clks = sdx55_rpmh_clocks,
 475         .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks),
 476 };
 477
 478 static struct clk_hw *sm8150_rpmh_clocks[] = {
 479         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 480         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 481         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a2.hw,
 482         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
 483         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a2.hw,
 484         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
 485         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 486         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 487         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_a.hw,
 488         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_a_ao.hw,
 489         [RPMH_RF_CLK3]          = &clk_rpmh_rf_clk3_a.hw,
 490         [RPMH_RF_CLK3_A]        = &clk_rpmh_rf_clk3_a_ao.hw,
 491         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 492 };
 493
 494 static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
 495         .clks = sm8150_rpmh_clocks,
 496         .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
 497 };
 498
 499 static struct clk_hw *sc7180_rpmh_clocks[] = {
 500         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 501         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 502         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a2.hw,
 503         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
 504         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a2.hw,
 505         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
 506         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 507         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 508         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_a.hw,
 509         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_a_ao.hw,
 510         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 511 };
 512
 513 static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
 514         .clks = sc7180_rpmh_clocks,
 515         .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks),
 516 };
 517
 518 static struct clk_hw *sc8180x_rpmh_clocks[] = {
 519         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 520         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 521         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a2.hw,
 522         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
 523         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a2.hw,
 524         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
 525         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_d.hw,
 526         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_d_ao.hw,
 527         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_d.hw,
 528         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_d_ao.hw,
 529         [RPMH_RF_CLK3]          = &clk_rpmh_rf_clk3_d.hw,
 530         [RPMH_RF_CLK3_A]        = &clk_rpmh_rf_clk3_d_ao.hw,
 531         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 532 };
 533
 534 static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
 535         .clks = sc8180x_rpmh_clocks,
 536         .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks),
 537 };
 538
 539 static struct clk_hw *sm8250_rpmh_clocks[] = {
 540         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 541         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 542         [RPMH_LN_BB_CLK1]       = &clk_rpmh_ln_bb_clk1_a2.hw,
 543         [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
 544         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a2.hw,
 545         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
 546         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a2.hw,
 547         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
 548         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 549         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 550         [RPMH_RF_CLK3]          = &clk_rpmh_rf_clk3_a.hw,
 551         [RPMH_RF_CLK3_A]        = &clk_rpmh_rf_clk3_a_ao.hw,
 552         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 553 };
 554
 555 static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
 556         .clks = sm8250_rpmh_clocks,
 557         .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
 558 };
 559
 560 static struct clk_hw *sm8350_rpmh_clocks[] = {
 561         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 562         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 563         [RPMH_DIV_CLK1]         = &clk_rpmh_div_clk1_div2.hw,
 564         [RPMH_DIV_CLK1_A]       = &clk_rpmh_div_clk1_div2_ao.hw,
 565         [RPMH_LN_BB_CLK1]       = &clk_rpmh_ln_bb_clk1_a2.hw,
 566         [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
 567         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a2.hw,
 568         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
 569         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 570         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 571         [RPMH_RF_CLK3]          = &clk_rpmh_rf_clk3_a.hw,
 572         [RPMH_RF_CLK3_A]        = &clk_rpmh_rf_clk3_a_ao.hw,
 573         [RPMH_RF_CLK4]          = &clk_rpmh_rf_clk4_a.hw,
 574         [RPMH_RF_CLK4_A]        = &clk_rpmh_rf_clk4_a_ao.hw,
 575         [RPMH_RF_CLK5]          = &clk_rpmh_rf_clk5_a.hw,
 576         [RPMH_RF_CLK5_A]        = &clk_rpmh_rf_clk5_a_ao.hw,
 577         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 578         [RPMH_PKA_CLK]          = &clk_rpmh_pka.hw,
 579         [RPMH_HWKM_CLK]         = &clk_rpmh_hwkm.hw,
 580 };
 581
 582 static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
 583         .clks = sm8350_rpmh_clocks,
 584         .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
 585 };
 586
 587 static struct clk_hw *sc8280xp_rpmh_clocks[] = {
 588         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 589         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 590         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a2.hw,
 591         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
 592         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 593         [RPMH_PKA_CLK]          = &clk_rpmh_pka.hw,
 594         [RPMH_HWKM_CLK]         = &clk_rpmh_hwkm.hw,
 595 };
 596
 597 static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
 598         .clks = sc8280xp_rpmh_clocks,
 599         .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks),
 600 };
 601
 602 static struct clk_hw *sm8450_rpmh_clocks[] = {
 603         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div4.hw,
 604         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div4_ao.hw,
 605         [RPMH_LN_BB_CLK1]       = &clk_rpmh_ln_bb_clk1_a4.hw,
 606         [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
 607         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a4.hw,
 608         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
 609         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 610         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 611         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_a.hw,
 612         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_a_ao.hw,
 613         [RPMH_RF_CLK3]          = &clk_rpmh_rf_clk3_a.hw,
 614         [RPMH_RF_CLK3_A]        = &clk_rpmh_rf_clk3_a_ao.hw,
 615         [RPMH_RF_CLK4]          = &clk_rpmh_rf_clk4_a.hw,
 616         [RPMH_RF_CLK4_A]        = &clk_rpmh_rf_clk4_a_ao.hw,
 617         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 618 };
 619
 620 static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
 621         .clks = sm8450_rpmh_clocks,
 622         .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks),
 623 };
 624
 625 static struct clk_hw *sm8550_rpmh_clocks[] = {
 626         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 627         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 628         [RPMH_LN_BB_CLK1]       = &clk_rpmh_clk6_a2.hw,
 629         [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_clk6_a2_ao.hw,
 630         [RPMH_LN_BB_CLK2]       = &clk_rpmh_clk7_a2.hw,
 631         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_clk7_a2_ao.hw,
 632         [RPMH_LN_BB_CLK3]       = &clk_rpmh_clk8_a2.hw,
 633         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_clk8_a2_ao.hw,
 634         [RPMH_RF_CLK1]          = &clk_rpmh_clk1_a1.hw,
 635         [RPMH_RF_CLK1_A]        = &clk_rpmh_clk1_a1_ao.hw,
 636         [RPMH_RF_CLK2]          = &clk_rpmh_clk2_a1.hw,
 637         [RPMH_RF_CLK2_A]        = &clk_rpmh_clk2_a1_ao.hw,
 638         [RPMH_RF_CLK3]          = &clk_rpmh_clk3_a1.hw,
 639         [RPMH_RF_CLK3_A]        = &clk_rpmh_clk3_a1_ao.hw,
 640         [RPMH_RF_CLK4]          = &clk_rpmh_clk4_a1.hw,
 641         [RPMH_RF_CLK4_A]        = &clk_rpmh_clk4_a1_ao.hw,
 642         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 643 };
 644
 645 static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
 646         .clks = sm8550_rpmh_clocks,
 647         .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
 648 };
 649
 650 static struct clk_hw *sm8650_rpmh_clocks[] = {
 651         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 652         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 653         [RPMH_LN_BB_CLK1]       = &clk_rpmh_clk6_a2.hw,
 654         [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_clk6_a2_ao.hw,
 655         [RPMH_LN_BB_CLK2]       = &clk_rpmh_clk7_a2.hw,
 656         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_clk7_a2_ao.hw,
 657         [RPMH_LN_BB_CLK3]       = &clk_rpmh_clk8_a2.hw,
 658         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_clk8_a2_ao.hw,
 659         [RPMH_RF_CLK1]          = &clk_rpmh_clk1_a1.hw,
 660         [RPMH_RF_CLK1_A]        = &clk_rpmh_clk1_a1_ao.hw,
 661         [RPMH_RF_CLK2]          = &clk_rpmh_clk2_a1.hw,
 662         [RPMH_RF_CLK2_A]        = &clk_rpmh_clk2_a1_ao.hw,
 663         /*
 664          * The clka3 RPMh resource is missing in cmd-db
 665          * for current platforms, while the clka3 exists
 666          * on the PMK8550, the clock is unconnected and
 667          * unused.
 668          */
 669         [RPMH_RF_CLK4]          = &clk_rpmh_clk4_a2.hw,
 670         [RPMH_RF_CLK4_A]        = &clk_rpmh_clk4_a2_ao.hw,
 671         [RPMH_RF_CLK5]          = &clk_rpmh_clk5_a2.hw,
 672         [RPMH_RF_CLK5_A]        = &clk_rpmh_clk5_a2_ao.hw,
 673         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 674 };
 675
 676 static const struct clk_rpmh_desc clk_rpmh_sm8650 = {
 677         .clks = sm8650_rpmh_clocks,
 678         .num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),
 679 };
 680
 681 static struct clk_hw *sc7280_rpmh_clocks[] = {
 682         [RPMH_CXO_CLK]      = &clk_rpmh_bi_tcxo_div4.hw,
 683         [RPMH_CXO_CLK_A]    = &clk_rpmh_bi_tcxo_div4_ao.hw,
 684         [RPMH_LN_BB_CLK2]   = &clk_rpmh_ln_bb_clk2_a2.hw,
 685         [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
 686         [RPMH_RF_CLK1]      = &clk_rpmh_rf_clk1_a.hw,
 687         [RPMH_RF_CLK1_A]    = &clk_rpmh_rf_clk1_a_ao.hw,
 688         [RPMH_RF_CLK3]      = &clk_rpmh_rf_clk3_a.hw,
 689         [RPMH_RF_CLK3_A]    = &clk_rpmh_rf_clk3_a_ao.hw,
 690         [RPMH_RF_CLK4]      = &clk_rpmh_rf_clk4_a.hw,
 691         [RPMH_RF_CLK4_A]    = &clk_rpmh_rf_clk4_a_ao.hw,
 692         [RPMH_IPA_CLK]      = &clk_rpmh_ipa.hw,
 693         [RPMH_PKA_CLK]      = &clk_rpmh_pka.hw,
 694         [RPMH_HWKM_CLK]     = &clk_rpmh_hwkm.hw,
 695 };
 696
 697 static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
 698         .clks = sc7280_rpmh_clocks,
 699         .num_clks = ARRAY_SIZE(sc7280_rpmh_clocks),
 700 };
 701
 702 static struct clk_hw *sm6350_rpmh_clocks[] = {
 703         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div4.hw,
 704         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div4_ao.hw,
 705         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_g4.hw,
 706         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_g4_ao.hw,
 707         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_g4.hw,
 708         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_g4_ao.hw,
 709         [RPMH_QLINK_CLK]        = &clk_rpmh_qlink_div4.hw,
 710         [RPMH_QLINK_CLK_A]      = &clk_rpmh_qlink_div4_ao.hw,
 711         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 712 };
 713
 714 static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
 715         .clks = sm6350_rpmh_clocks,
 716         .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
 717 };
 718
 719 static struct clk_hw *sdx65_rpmh_clocks[] = {
 720         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div4.hw,
 721         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div4_ao.hw,
 722         [RPMH_LN_BB_CLK1]       = &clk_rpmh_ln_bb_clk1_a4.hw,
 723         [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
 724         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 725         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 726         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_a.hw,
 727         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_a_ao.hw,
 728         [RPMH_RF_CLK3]          = &clk_rpmh_rf_clk3_a.hw,
 729         [RPMH_RF_CLK3_A]        = &clk_rpmh_rf_clk3_a_ao.hw,
 730         [RPMH_RF_CLK4]          = &clk_rpmh_rf_clk4_a.hw,
 731         [RPMH_RF_CLK4_A]        = &clk_rpmh_rf_clk4_a_ao.hw,
 732         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 733         [RPMH_QPIC_CLK]         = &clk_rpmh_qpic_clk.hw,
 734 };
 735
 736 static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
 737         .clks = sdx65_rpmh_clocks,
 738         .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks),
 739 };
 740
 741 static struct clk_hw *qdu1000_rpmh_clocks[] = {
 742         [RPMH_CXO_CLK]      = &clk_rpmh_bi_tcxo_div1.hw,
 743         [RPMH_CXO_CLK_A]    = &clk_rpmh_bi_tcxo_div1_ao.hw,
 744 };
 745
 746 static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
 747         .clks = qdu1000_rpmh_clocks,
 748         .num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks),
 749 };
 750
 751 static struct clk_hw *sdx75_rpmh_clocks[] = {
 752         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div4.hw,
 753         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div4_ao.hw,
 754         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 755         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 756         [RPMH_RF_CLK2]          = &clk_rpmh_rf_clk2_a.hw,
 757         [RPMH_RF_CLK2_A]        = &clk_rpmh_rf_clk2_a_ao.hw,
 758         [RPMH_RF_CLK3]          = &clk_rpmh_rf_clk3_a.hw,
 759         [RPMH_RF_CLK3_A]        = &clk_rpmh_rf_clk3_a_ao.hw,
 760         [RPMH_QPIC_CLK]         = &clk_rpmh_qpic_clk.hw,
 761         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 762 };
 763
 764 static const struct clk_rpmh_desc clk_rpmh_sdx75 = {
 765         .clks = sdx75_rpmh_clocks,
 766         .num_clks = ARRAY_SIZE(sdx75_rpmh_clocks),
 767 };
 768
 769 static struct clk_hw *sm4450_rpmh_clocks[] = {
 770         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div4.hw,
 771         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div4_ao.hw,
 772         [RPMH_LN_BB_CLK2]       = &clk_rpmh_ln_bb_clk2_a4.hw,
 773         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
 774         [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a4.hw,
 775         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a4_ao.hw,
 776         [RPMH_RF_CLK1]          = &clk_rpmh_rf_clk1_a.hw,
 777         [RPMH_RF_CLK1_A]        = &clk_rpmh_rf_clk1_a_ao.hw,
 778         [RPMH_RF_CLK5]          = &clk_rpmh_rf_clk5_a.hw,
 779         [RPMH_RF_CLK5_A]        = &clk_rpmh_rf_clk5_a_ao.hw,
 780         [RPMH_IPA_CLK]          = &clk_rpmh_ipa.hw,
 781 };
 782
 783 static const struct clk_rpmh_desc clk_rpmh_sm4450 = {
 784         .clks = sm4450_rpmh_clocks,
 785         .num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),
 786 };
 787
 788 static struct clk_hw *x1e80100_rpmh_clocks[] = {
 789         [RPMH_CXO_CLK]          = &clk_rpmh_bi_tcxo_div2.hw,
 790         [RPMH_CXO_CLK_A]        = &clk_rpmh_bi_tcxo_div2_ao.hw,
 791         [RPMH_LN_BB_CLK1]       = &clk_rpmh_clk6_a2.hw,
 792         [RPMH_LN_BB_CLK1_A]     = &clk_rpmh_clk6_a2_ao.hw,
 793         [RPMH_LN_BB_CLK2]       = &clk_rpmh_clk7_a2.hw,
 794         [RPMH_LN_BB_CLK2_A]     = &clk_rpmh_clk7_a2_ao.hw,
 795         [RPMH_LN_BB_CLK3]       = &clk_rpmh_clk8_a2.hw,
 796         [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_clk8_a2_ao.hw,
 797         [RPMH_RF_CLK3]          = &clk_rpmh_clk3_a2.hw,
 798         [RPMH_RF_CLK3_A]        = &clk_rpmh_clk3_a2_ao.hw,
 799         [RPMH_RF_CLK4]          = &clk_rpmh_clk4_a2.hw,
 800         [RPMH_RF_CLK4_A]        = &clk_rpmh_clk4_a2_ao.hw,
 801         [RPMH_RF_CLK5]          = &clk_rpmh_clk5_a2.hw,
 802         [RPMH_RF_CLK5_A]        = &clk_rpmh_clk5_a2_ao.hw,
 803 };
 804
 805 static const struct clk_rpmh_desc clk_rpmh_x1e80100 = {
 806         .clks = x1e80100_rpmh_clocks,
 807         .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks),
 808 };
 809
 810 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
 811                                          void *data)
 812 {
 813         struct clk_rpmh_desc *rpmh = data;
 814         unsigned int idx = clkspec->args[0];
 815
 816         if (idx >= rpmh->num_clks) {
 817                 pr_err("%s: invalid index %u\n", __func__, idx);
 818                 return ERR_PTR(-EINVAL);
 819         }
 820
 821         return rpmh->clks[idx];
 822 }
 823
 824 static int clk_rpmh_probe(struct platform_device *pdev)
 825 {
 826         struct clk_hw **hw_clks;
 827         struct clk_rpmh *rpmh_clk;
 828         const struct clk_rpmh_desc *desc;
 829         int ret, i;
 830
 831         desc = of_device_get_match_data(&pdev->dev);
 832         if (!desc)
 833                 return -ENODEV;
 834
 835         hw_clks = desc->clks;
 836
 837         for (i = 0; i < desc->num_clks; i++) {
 838                 const char *name;
 839                 u32 res_addr;
 840                 size_t aux_data_len;
 841                 const struct bcm_db *data;
 842
 843                 if (!hw_clks[i])
 844                         continue;
 845
 846                 name = hw_clks[i]->init->name;
 847
 848                 rpmh_clk = to_clk_rpmh(hw_clks[i]);
 849                 res_addr = cmd_db_read_addr(rpmh_clk->res_name);
 850                 if (!res_addr) {
 851                         dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
 852                                 rpmh_clk->res_name);
 853                         return -ENODEV;
 854                 }
 855
 856                 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
 857                 if (IS_ERR(data)) {
 858                         ret = PTR_ERR(data);
 859                         dev_err(&pdev->dev,
 860                                 "error reading RPMh aux data for %s (%d)\n",
 861                                 rpmh_clk->res_name, ret);
 862                         return ret;
 863                 }
 864
 865                 /* Convert unit from Khz to Hz */
 866                 if (aux_data_len == sizeof(*data))
 867                         rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
 868
 869                 rpmh_clk->res_addr += res_addr;
 870                 rpmh_clk->dev = &pdev->dev;
 871
 872                 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
 873                 if (ret) {
 874                         dev_err(&pdev->dev, "failed to register %s\n", name);
 875                         return ret;
 876                 }
 877         }
 878
 879         /* typecast to silence compiler warning */
 880         ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
 881                                           (void *)desc);
 882         if (ret) {
 883                 dev_err(&pdev->dev, "Failed to add clock provider\n");
 884                 return ret;
 885         }
 886
 887         dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
 888
 889         return 0;
 890 }
 891
 892 static const struct of_device_id clk_rpmh_match_table[] = {
 893         { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
 894         { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p},
 895         { .compatible = "qcom,sar2130p-rpmh-clk", .data = &clk_rpmh_sar2130p},
 896         { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
 897         { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
 898         { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},
 899         { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
 900         { .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670},
 901         { .compatible = "qcom,sdx55-rpmh-clk",  .data = &clk_rpmh_sdx55},
 902         { .compatible = "qcom,sdx65-rpmh-clk",  .data = &clk_rpmh_sdx65},
 903         { .compatible = "qcom,sdx75-rpmh-clk",  .data = &clk_rpmh_sdx75},
 904         { .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450},
 905         { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
 906         { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
 907         { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
 908         { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
 909         { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
 910         { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
 911         { .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650},
 912         { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
 913         { .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100},
 914         { }
 915 };
 916 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
 917
 918 static struct platform_driver clk_rpmh_driver = {
 919         .probe          = clk_rpmh_probe,
 920         .driver         = {
 921                 .name   = "clk-rpmh",
 922                 .of_match_table = clk_rpmh_match_table,
 923         },
 924 };
 925
 926 static int __init clk_rpmh_init(void)
 927 {
 928         return platform_driver_register(&clk_rpmh_driver);
 929 }
 930 core_initcall(clk_rpmh_init);
 931
 932 static void __exit clk_rpmh_exit(void)
 933 {
 934         platform_driver_unregister(&clk_rpmh_driver);
 935 }
 936 module_exit(clk_rpmh_exit);
 937
 938 MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
 939 MODULE_LICENSE("GPL v2");