drivers/clk/qcom/dispcc0-sa8775p.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/module.h>
   8 #include <linux/mod_devicetable.h>
   9 #include <linux/of.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/regmap.h>
  13
  14 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
  15
  16 #include "clk-alpha-pll.h"
  17 #include "clk-branch.h"
  18 #include "clk-pll.h"
  19 #include "clk-rcg.h"
  20 #include "clk-regmap.h"
  21 #include "clk-regmap-divider.h"
  22 #include "clk-regmap-mux.h"
  23 #include "common.h"
  24 #include "gdsc.h"
  25 #include "reset.h"
  26
  27 enum {
  28         DT_IFACE,
  29         DT_BI_TCXO,
  30         DT_BI_TCXO_AO,
  31         DT_SLEEP_CLK,
  32         DT_DP0_PHY_PLL_LINK_CLK,
  33         DT_DP0_PHY_PLL_VCO_DIV_CLK,
  34         DT_DP1_PHY_PLL_LINK_CLK,
  35         DT_DP1_PHY_PLL_VCO_DIV_CLK,
  36         DT_DSI0_PHY_PLL_OUT_BYTECLK,
  37         DT_DSI0_PHY_PLL_OUT_DSICLK,
  38         DT_DSI1_PHY_PLL_OUT_BYTECLK,
  39         DT_DSI1_PHY_PLL_OUT_DSICLK,
  40 };
  41
  42 enum {
  43         P_BI_TCXO,
  44         P_DP0_PHY_PLL_LINK_CLK,
  45         P_DP0_PHY_PLL_VCO_DIV_CLK,
  46         P_DP1_PHY_PLL_LINK_CLK,
  47         P_DP1_PHY_PLL_VCO_DIV_CLK,
  48         P_DSI0_PHY_PLL_OUT_BYTECLK,
  49         P_DSI0_PHY_PLL_OUT_DSICLK,
  50         P_DSI1_PHY_PLL_OUT_BYTECLK,
  51         P_DSI1_PHY_PLL_OUT_DSICLK,
  52         P_MDSS_0_DISP_CC_PLL0_OUT_MAIN,
  53         P_MDSS_0_DISP_CC_PLL1_OUT_EVEN,
  54         P_MDSS_0_DISP_CC_PLL1_OUT_MAIN,
  55         P_SLEEP_CLK,
  56 };
  57
  58 static const struct pll_vco lucid_evo_vco[] = {
  59         { 249600000, 2020000000, 0 },
  60 };
  61
  62 static const struct alpha_pll_config mdss_0_disp_cc_pll0_config = {
  63         .l = 0x3a,
  64         .alpha = 0x9800,
  65         .config_ctl_val = 0x20485699,
  66         .config_ctl_hi_val = 0x00182261,
  67         .config_ctl_hi1_val = 0x32aa299c,
  68         .user_ctl_val = 0x00000000,
  69         .user_ctl_hi_val = 0x00400805,
  70 };
  71
  72 static struct clk_alpha_pll mdss_0_disp_cc_pll0 = {
  73         .offset = 0x0,
  74         .vco_table = lucid_evo_vco,
  75         .num_vco = ARRAY_SIZE(lucid_evo_vco),
  76         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  77         .clkr = {
  78                 .hw.init = &(const struct clk_init_data) {
  79                         .name = "mdss_0_disp_cc_pll0",
  80                         .parent_data = &(const struct clk_parent_data) {
  81                                 .index = DT_BI_TCXO,
  82                         },
  83                         .num_parents = 1,
  84                         .ops = &clk_alpha_pll_lucid_evo_ops,
  85                 },
  86         },
  87 };
  88
  89 static const struct alpha_pll_config mdss_0_disp_cc_pll1_config = {
  90         .l = 0x1f,
  91         .alpha = 0x4000,
  92         .config_ctl_val = 0x20485699,
  93         .config_ctl_hi_val = 0x00182261,
  94         .config_ctl_hi1_val = 0x32aa299c,
  95         .user_ctl_val = 0x00000000,
  96         .user_ctl_hi_val = 0x00400805,
  97 };
  98
  99 static struct clk_alpha_pll mdss_0_disp_cc_pll1 = {
 100         .offset = 0x1000,
 101         .vco_table = lucid_evo_vco,
 102         .num_vco = ARRAY_SIZE(lucid_evo_vco),
 103         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 104         .clkr = {
 105                 .hw.init = &(const struct clk_init_data) {
 106                         .name = "mdss_0_disp_cc_pll1",
 107                         .parent_data = &(const struct clk_parent_data) {
 108                                 .index = DT_BI_TCXO,
 109                         },
 110                         .num_parents = 1,
 111                         .ops = &clk_alpha_pll_lucid_evo_ops,
 112                 },
 113         },
 114 };
 115
 116 static const struct parent_map disp_cc_0_parent_map_0[] = {
 117         { P_BI_TCXO, 0 },
 118         { P_DP0_PHY_PLL_LINK_CLK, 1 },
 119         { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
 120         { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
 121 };
 122
 123 static const struct clk_parent_data disp_cc_0_parent_data_0[] = {
 124         { .index = DT_BI_TCXO },
 125         { .index = DT_DP0_PHY_PLL_LINK_CLK },
 126         { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
 127         { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
 128 };
 129
 130 static const struct parent_map disp_cc_0_parent_map_1[] = {
 131         { P_BI_TCXO, 0 },
 132         { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 133         { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 134         { P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
 135         { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 136 };
 137
 138 static const struct clk_parent_data disp_cc_0_parent_data_1[] = {
 139         { .index = DT_BI_TCXO },
 140         { .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
 141         { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 142         { .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
 143         { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 144 };
 145
 146 static const struct parent_map disp_cc_0_parent_map_2[] = {
 147         { P_BI_TCXO, 0 },
 148 };
 149
 150 static const struct clk_parent_data disp_cc_0_parent_data_2[] = {
 151         { .index = DT_BI_TCXO },
 152 };
 153
 154 static const struct clk_parent_data disp_cc_0_parent_data_2_ao[] = {
 155         { .index = DT_BI_TCXO_AO },
 156 };
 157
 158 static const struct parent_map disp_cc_0_parent_map_3[] = {
 159         { P_BI_TCXO, 0 },
 160         { P_DP0_PHY_PLL_LINK_CLK, 1 },
 161         { P_DP1_PHY_PLL_LINK_CLK, 2 },
 162 };
 163
 164 static const struct clk_parent_data disp_cc_0_parent_data_3[] = {
 165         { .index = DT_BI_TCXO },
 166         { .index = DT_DP0_PHY_PLL_LINK_CLK },
 167         { .index = DT_DP1_PHY_PLL_LINK_CLK },
 168 };
 169
 170 static const struct parent_map disp_cc_0_parent_map_4[] = {
 171         { P_BI_TCXO, 0 },
 172         { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 173         { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 174 };
 175
 176 static const struct clk_parent_data disp_cc_0_parent_data_4[] = {
 177         { .index = DT_BI_TCXO },
 178         { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 179         { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 180 };
 181
 182 static const struct parent_map disp_cc_0_parent_map_5[] = {
 183         { P_BI_TCXO, 0 },
 184         { P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 },
 185         { P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 },
 186 };
 187
 188 static const struct clk_parent_data disp_cc_0_parent_data_5[] = {
 189         { .index = DT_BI_TCXO },
 190         { .hw = &mdss_0_disp_cc_pll1.clkr.hw },
 191         { .hw = &mdss_0_disp_cc_pll1.clkr.hw },
 192 };
 193
 194 static const struct parent_map disp_cc_0_parent_map_6[] = {
 195         { P_BI_TCXO, 0 },
 196         { P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 1 },
 197         { P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 },
 198         { P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 },
 199 };
 200
 201 static const struct clk_parent_data disp_cc_0_parent_data_6[] = {
 202         { .index = DT_BI_TCXO },
 203         { .hw = &mdss_0_disp_cc_pll0.clkr.hw },
 204         { .hw = &mdss_0_disp_cc_pll1.clkr.hw },
 205         { .hw = &mdss_0_disp_cc_pll1.clkr.hw },
 206 };
 207
 208 static const struct parent_map disp_cc_0_parent_map_7[] = {
 209         { P_SLEEP_CLK, 0 },
 210 };
 211
 212 static const struct clk_parent_data disp_cc_0_parent_data_7[] = {
 213         { .index = DT_SLEEP_CLK },
 214 };
 215
 216 static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_ahb_clk_src[] = {
 217         F(37500000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
 218         F(75000000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
 219         { }
 220 };
 221
 222 static struct clk_rcg2 mdss_0_disp_cc_mdss_ahb_clk_src = {
 223         .cmd_rcgr = 0x824c,
 224         .mnd_width = 0,
 225         .hid_width = 5,
 226         .parent_map = disp_cc_0_parent_map_5,
 227         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_ahb_clk_src,
 228         .clkr.hw.init = &(const struct clk_init_data) {
 229                 .name = "mdss_0_disp_cc_mdss_ahb_clk_src",
 230                 .parent_data = disp_cc_0_parent_data_5,
 231                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_5),
 232                 .flags = CLK_SET_RATE_PARENT,
 233                 .ops = &clk_rcg2_shared_ops,
 234         },
 235 };
 236
 237 static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_byte0_clk_src[] = {
 238         F(19200000, P_BI_TCXO, 1, 0, 0),
 239         { }
 240 };
 241
 242 static struct clk_rcg2 mdss_0_disp_cc_mdss_byte0_clk_src = {
 243         .cmd_rcgr = 0x80ec,
 244         .mnd_width = 0,
 245         .hid_width = 5,
 246         .parent_map = disp_cc_0_parent_map_1,
 247         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 248         .clkr.hw.init = &(const struct clk_init_data) {
 249                 .name = "mdss_0_disp_cc_mdss_byte0_clk_src",
 250                 .parent_data = disp_cc_0_parent_data_1,
 251                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
 252                 .flags = CLK_SET_RATE_PARENT,
 253                 .ops = &clk_byte2_ops,
 254         },
 255 };
 256
 257 static struct clk_rcg2 mdss_0_disp_cc_mdss_byte1_clk_src = {
 258         .cmd_rcgr = 0x8108,
 259         .mnd_width = 0,
 260         .hid_width = 5,
 261         .parent_map = disp_cc_0_parent_map_1,
 262         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 263         .clkr.hw.init = &(const struct clk_init_data) {
 264                 .name = "mdss_0_disp_cc_mdss_byte1_clk_src",
 265                 .parent_data = disp_cc_0_parent_data_1,
 266                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
 267                 .flags = CLK_SET_RATE_PARENT,
 268                 .ops = &clk_byte2_ops,
 269         },
 270 };
 271
 272 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_aux_clk_src = {
 273         .cmd_rcgr = 0x81b8,
 274         .mnd_width = 0,
 275         .hid_width = 5,
 276         .parent_map = disp_cc_0_parent_map_2,
 277         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 278         .clkr.hw.init = &(const struct clk_init_data) {
 279                 .name = "mdss_0_disp_cc_mdss_dptx0_aux_clk_src",
 280                 .parent_data = disp_cc_0_parent_data_2,
 281                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
 282                 .flags = CLK_SET_RATE_PARENT,
 283                 .ops = &clk_rcg2_shared_ops,
 284         },
 285 };
 286
 287 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_crypto_clk_src = {
 288         .cmd_rcgr = 0x8170,
 289         .mnd_width = 0,
 290         .hid_width = 5,
 291         .parent_map = disp_cc_0_parent_map_3,
 292         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 293         .clkr.hw.init = &(const struct clk_init_data) {
 294                 .name = "mdss_0_disp_cc_mdss_dptx0_crypto_clk_src",
 295                 .parent_data = disp_cc_0_parent_data_3,
 296                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
 297                 .flags = CLK_SET_RATE_PARENT,
 298                 .ops = &clk_byte2_ops,
 299         },
 300 };
 301
 302 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_link_clk_src = {
 303         .cmd_rcgr = 0x8154,
 304         .mnd_width = 0,
 305         .hid_width = 5,
 306         .parent_map = disp_cc_0_parent_map_3,
 307         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 308         .clkr.hw.init = &(const struct clk_init_data) {
 309                 .name = "mdss_0_disp_cc_mdss_dptx0_link_clk_src",
 310                 .parent_data = disp_cc_0_parent_data_3,
 311                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
 312                 .flags = CLK_SET_RATE_PARENT,
 313                 .ops = &clk_byte2_ops,
 314         },
 315 };
 316
 317 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src = {
 318         .cmd_rcgr = 0x8188,
 319         .mnd_width = 16,
 320         .hid_width = 5,
 321         .parent_map = disp_cc_0_parent_map_0,
 322         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 323         .clkr.hw.init = &(const struct clk_init_data) {
 324                 .name = "mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src",
 325                 .parent_data = disp_cc_0_parent_data_0,
 326                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 327                 .flags = CLK_SET_RATE_PARENT,
 328                 .ops = &clk_dp_ops,
 329         },
 330 };
 331
 332 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src = {
 333         .cmd_rcgr = 0x81a0,
 334         .mnd_width = 16,
 335         .hid_width = 5,
 336         .parent_map = disp_cc_0_parent_map_0,
 337         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 338         .clkr.hw.init = &(const struct clk_init_data) {
 339                 .name = "mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src",
 340                 .parent_data = disp_cc_0_parent_data_0,
 341                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 342                 .flags = CLK_SET_RATE_PARENT,
 343                 .ops = &clk_dp_ops,
 344         },
 345 };
 346
 347 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src = {
 348         .cmd_rcgr = 0x826c,
 349         .mnd_width = 16,
 350         .hid_width = 5,
 351         .parent_map = disp_cc_0_parent_map_0,
 352         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 353         .clkr.hw.init = &(const struct clk_init_data) {
 354                 .name = "mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src",
 355                 .parent_data = disp_cc_0_parent_data_0,
 356                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 357                 .flags = CLK_SET_RATE_PARENT,
 358                 .ops = &clk_dp_ops,
 359         },
 360 };
 361
 362 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src = {
 363         .cmd_rcgr = 0x8284,
 364         .mnd_width = 16,
 365         .hid_width = 5,
 366         .parent_map = disp_cc_0_parent_map_0,
 367         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 368         .clkr.hw.init = &(const struct clk_init_data) {
 369                 .name = "mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src",
 370                 .parent_data = disp_cc_0_parent_data_0,
 371                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 372                 .flags = CLK_SET_RATE_PARENT,
 373                 .ops = &clk_dp_ops,
 374         },
 375 };
 376
 377 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_aux_clk_src = {
 378         .cmd_rcgr = 0x8234,
 379         .mnd_width = 0,
 380         .hid_width = 5,
 381         .parent_map = disp_cc_0_parent_map_2,
 382         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 383         .clkr.hw.init = &(const struct clk_init_data) {
 384                 .name = "mdss_0_disp_cc_mdss_dptx1_aux_clk_src",
 385                 .parent_data = disp_cc_0_parent_data_2,
 386                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
 387                 .flags = CLK_SET_RATE_PARENT,
 388                 .ops = &clk_rcg2_shared_ops,
 389         },
 390 };
 391
 392 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_crypto_clk_src = {
 393         .cmd_rcgr = 0x821c,
 394         .mnd_width = 0,
 395         .hid_width = 5,
 396         .parent_map = disp_cc_0_parent_map_3,
 397         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 398         .clkr.hw.init = &(const struct clk_init_data) {
 399                 .name = "mdss_0_disp_cc_mdss_dptx1_crypto_clk_src",
 400                 .parent_data = disp_cc_0_parent_data_3,
 401                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
 402                 .flags = CLK_SET_RATE_PARENT,
 403                 .ops = &clk_byte2_ops,
 404         },
 405 };
 406
 407 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_link_clk_src = {
 408         .cmd_rcgr = 0x8200,
 409         .mnd_width = 0,
 410         .hid_width = 5,
 411         .parent_map = disp_cc_0_parent_map_3,
 412         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 413         .clkr.hw.init = &(const struct clk_init_data) {
 414                 .name = "mdss_0_disp_cc_mdss_dptx1_link_clk_src",
 415                 .parent_data = disp_cc_0_parent_data_3,
 416                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
 417                 .flags = CLK_SET_RATE_PARENT,
 418                 .ops = &clk_byte2_ops,
 419         },
 420 };
 421
 422 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src = {
 423         .cmd_rcgr = 0x81d0,
 424         .mnd_width = 16,
 425         .hid_width = 5,
 426         .parent_map = disp_cc_0_parent_map_0,
 427         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 428         .clkr.hw.init = &(const struct clk_init_data) {
 429                 .name = "mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src",
 430                 .parent_data = disp_cc_0_parent_data_0,
 431                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 432                 .flags = CLK_SET_RATE_PARENT,
 433                 .ops = &clk_dp_ops,
 434         },
 435 };
 436
 437 static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src = {
 438         .cmd_rcgr = 0x81e8,
 439         .mnd_width = 16,
 440         .hid_width = 5,
 441         .parent_map = disp_cc_0_parent_map_0,
 442         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 443         .clkr.hw.init = &(const struct clk_init_data) {
 444                 .name = "mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src",
 445                 .parent_data = disp_cc_0_parent_data_0,
 446                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 447                 .flags = CLK_SET_RATE_PARENT,
 448                 .ops = &clk_dp_ops,
 449         },
 450 };
 451
 452 static struct clk_rcg2 mdss_0_disp_cc_mdss_esc0_clk_src = {
 453         .cmd_rcgr = 0x8124,
 454         .mnd_width = 0,
 455         .hid_width = 5,
 456         .parent_map = disp_cc_0_parent_map_4,
 457         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 458         .clkr.hw.init = &(const struct clk_init_data) {
 459                 .name = "mdss_0_disp_cc_mdss_esc0_clk_src",
 460                 .parent_data = disp_cc_0_parent_data_4,
 461                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_4),
 462                 .flags = CLK_SET_RATE_PARENT,
 463                 .ops = &clk_rcg2_shared_ops,
 464         },
 465 };
 466
 467 static struct clk_rcg2 mdss_0_disp_cc_mdss_esc1_clk_src = {
 468         .cmd_rcgr = 0x813c,
 469         .mnd_width = 0,
 470         .hid_width = 5,
 471         .parent_map = disp_cc_0_parent_map_4,
 472         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 473         .clkr.hw.init = &(const struct clk_init_data) {
 474                 .name = "mdss_0_disp_cc_mdss_esc1_clk_src",
 475                 .parent_data = disp_cc_0_parent_data_4,
 476                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_4),
 477                 .flags = CLK_SET_RATE_PARENT,
 478                 .ops = &clk_rcg2_shared_ops,
 479         },
 480 };
 481
 482 static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_mdp_clk_src[] = {
 483         F(375000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 484         F(500000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 485         F(575000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 486         F(650000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 487         { }
 488 };
 489
 490 static struct clk_rcg2 mdss_0_disp_cc_mdss_mdp_clk_src = {
 491         .cmd_rcgr = 0x80bc,
 492         .mnd_width = 0,
 493         .hid_width = 5,
 494         .parent_map = disp_cc_0_parent_map_6,
 495         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_mdp_clk_src,
 496         .clkr.hw.init = &(const struct clk_init_data) {
 497                 .name = "mdss_0_disp_cc_mdss_mdp_clk_src",
 498                 .parent_data = disp_cc_0_parent_data_6,
 499                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_6),
 500                 .flags = CLK_SET_RATE_PARENT,
 501                 .ops = &clk_rcg2_shared_ops,
 502         },
 503 };
 504
 505 static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk0_clk_src = {
 506         .cmd_rcgr = 0x808c,
 507         .mnd_width = 8,
 508         .hid_width = 5,
 509         .parent_map = disp_cc_0_parent_map_1,
 510         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 511         .clkr.hw.init = &(const struct clk_init_data) {
 512                 .name = "mdss_0_disp_cc_mdss_pclk0_clk_src",
 513                 .parent_data = disp_cc_0_parent_data_1,
 514                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
 515                 .flags = CLK_SET_RATE_PARENT,
 516                 .ops = &clk_pixel_ops,
 517         },
 518 };
 519
 520 static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk1_clk_src = {
 521         .cmd_rcgr = 0x80a4,
 522         .mnd_width = 8,
 523         .hid_width = 5,
 524         .parent_map = disp_cc_0_parent_map_1,
 525         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 526         .clkr.hw.init = &(const struct clk_init_data) {
 527                 .name = "mdss_0_disp_cc_mdss_pclk1_clk_src",
 528                 .parent_data = disp_cc_0_parent_data_1,
 529                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
 530                 .flags = CLK_SET_RATE_PARENT,
 531                 .ops = &clk_pixel_ops,
 532         },
 533 };
 534
 535 static struct clk_rcg2 mdss_0_disp_cc_mdss_vsync_clk_src = {
 536         .cmd_rcgr = 0x80d4,
 537         .mnd_width = 0,
 538         .hid_width = 5,
 539         .parent_map = disp_cc_0_parent_map_2,
 540         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 541         .clkr.hw.init = &(const struct clk_init_data) {
 542                 .name = "mdss_0_disp_cc_mdss_vsync_clk_src",
 543                 .parent_data = disp_cc_0_parent_data_2,
 544                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
 545                 .flags = CLK_SET_RATE_PARENT,
 546                 .ops = &clk_rcg2_shared_ops,
 547         },
 548 };
 549
 550 static const struct freq_tbl ftbl_mdss_0_disp_cc_sleep_clk_src[] = {
 551         F(32000, P_SLEEP_CLK, 1, 0, 0),
 552         { }
 553 };
 554
 555 static struct clk_rcg2 mdss_0_disp_cc_sleep_clk_src = {
 556         .cmd_rcgr = 0xc058,
 557         .mnd_width = 0,
 558         .hid_width = 5,
 559         .parent_map = disp_cc_0_parent_map_7,
 560         .freq_tbl = ftbl_mdss_0_disp_cc_sleep_clk_src,
 561         .clkr.hw.init = &(const struct clk_init_data) {
 562                 .name = "mdss_0_disp_cc_sleep_clk_src",
 563                 .parent_data = disp_cc_0_parent_data_7,
 564                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_7),
 565                 .flags = CLK_SET_RATE_PARENT,
 566                 .ops = &clk_rcg2_shared_ops,
 567         },
 568 };
 569
 570 static struct clk_rcg2 mdss_0_disp_cc_xo_clk_src = {
 571         .cmd_rcgr = 0xc03c,
 572         .mnd_width = 0,
 573         .hid_width = 5,
 574         .parent_map = disp_cc_0_parent_map_2,
 575         .freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 576         .clkr.hw.init = &(const struct clk_init_data) {
 577                 .name = "mdss_0_disp_cc_xo_clk_src",
 578                 .parent_data = disp_cc_0_parent_data_2_ao,
 579                 .num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2_ao),
 580                 .flags = CLK_SET_RATE_PARENT,
 581                 .ops = &clk_rcg2_shared_ops,
 582         },
 583 };
 584
 585 static struct clk_regmap_div mdss_0_disp_cc_mdss_byte0_div_clk_src = {
 586         .reg = 0x8104,
 587         .shift = 0,
 588         .width = 4,
 589         .clkr.hw.init = &(const struct clk_init_data) {
 590                 .name = "mdss_0_disp_cc_mdss_byte0_div_clk_src",
 591                 .parent_hws = (const struct clk_hw*[]) {
 592                         &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw,
 593                 },
 594                 .num_parents = 1,
 595                 .flags = CLK_SET_RATE_PARENT,
 596                 .ops = &clk_regmap_div_ops,
 597         },
 598 };
 599
 600 static struct clk_regmap_div mdss_0_disp_cc_mdss_byte1_div_clk_src = {
 601         .reg = 0x8120,
 602         .shift = 0,
 603         .width = 4,
 604         .clkr.hw.init = &(const struct clk_init_data) {
 605                 .name = "mdss_0_disp_cc_mdss_byte1_div_clk_src",
 606                 .parent_hws = (const struct clk_hw*[]) {
 607                         &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw,
 608                 },
 609                 .num_parents = 1,
 610                 .flags = CLK_SET_RATE_PARENT,
 611                 .ops = &clk_regmap_div_ops,
 612         },
 613 };
 614
 615 static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx0_link_div_clk_src = {
 616         .reg = 0x816c,
 617         .shift = 0,
 618         .width = 4,
 619         .clkr.hw.init = &(const struct clk_init_data) {
 620                 .name = "mdss_0_disp_cc_mdss_dptx0_link_div_clk_src",
 621                 .parent_hws = (const struct clk_hw*[]) {
 622                         &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
 623                 },
 624                 .num_parents = 1,
 625                 .flags = CLK_SET_RATE_PARENT,
 626                 .ops = &clk_regmap_div_ro_ops,
 627         },
 628 };
 629
 630 static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx1_link_div_clk_src = {
 631         .reg = 0x8218,
 632         .shift = 0,
 633         .width = 4,
 634         .clkr.hw.init = &(const struct clk_init_data) {
 635                 .name = "mdss_0_disp_cc_mdss_dptx1_link_div_clk_src",
 636                 .parent_hws = (const struct clk_hw*[]) {
 637                         &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
 638                 },
 639                 .num_parents = 1,
 640                 .flags = CLK_SET_RATE_PARENT,
 641                 .ops = &clk_regmap_div_ro_ops,
 642         },
 643 };
 644
 645 static struct clk_branch mdss_0_disp_cc_mdss_ahb1_clk = {
 646         .halt_reg = 0x8088,
 647         .halt_check = BRANCH_HALT,
 648         .clkr = {
 649                 .enable_reg = 0x8088,
 650                 .enable_mask = BIT(0),
 651                 .hw.init = &(const struct clk_init_data) {
 652                         .name = "mdss_0_disp_cc_mdss_ahb1_clk",
 653                         .parent_hws = (const struct clk_hw*[]) {
 654                                 &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
 655                         },
 656                         .num_parents = 1,
 657                         .flags = CLK_SET_RATE_PARENT,
 658                         .ops = &clk_branch2_ops,
 659                 },
 660         },
 661 };
 662
 663 static struct clk_branch mdss_0_disp_cc_mdss_ahb_clk = {
 664         .halt_reg = 0x8084,
 665         .halt_check = BRANCH_HALT,
 666         .clkr = {
 667                 .enable_reg = 0x8084,
 668                 .enable_mask = BIT(0),
 669                 .hw.init = &(const struct clk_init_data) {
 670                         .name = "mdss_0_disp_cc_mdss_ahb_clk",
 671                         .parent_hws = (const struct clk_hw*[]) {
 672                                 &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
 673                         },
 674                         .num_parents = 1,
 675                         .flags = CLK_SET_RATE_PARENT,
 676                         .ops = &clk_branch2_ops,
 677                 },
 678         },
 679 };
 680
 681 static struct clk_branch mdss_0_disp_cc_mdss_byte0_clk = {
 682         .halt_reg = 0x8034,
 683         .halt_check = BRANCH_HALT,
 684         .clkr = {
 685                 .enable_reg = 0x8034,
 686                 .enable_mask = BIT(0),
 687                 .hw.init = &(const struct clk_init_data) {
 688                         .name = "mdss_0_disp_cc_mdss_byte0_clk",
 689                         .parent_hws = (const struct clk_hw*[]) {
 690                                 &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw,
 691                         },
 692                         .num_parents = 1,
 693                         .flags = CLK_SET_RATE_PARENT,
 694                         .ops = &clk_branch2_ops,
 695                 },
 696         },
 697 };
 698
 699 static struct clk_branch mdss_0_disp_cc_mdss_byte0_intf_clk = {
 700         .halt_reg = 0x8038,
 701         .halt_check = BRANCH_HALT,
 702         .clkr = {
 703                 .enable_reg = 0x8038,
 704                 .enable_mask = BIT(0),
 705                 .hw.init = &(const struct clk_init_data) {
 706                         .name = "mdss_0_disp_cc_mdss_byte0_intf_clk",
 707                         .parent_hws = (const struct clk_hw*[]) {
 708                                 &mdss_0_disp_cc_mdss_byte0_div_clk_src.clkr.hw,
 709                         },
 710                         .num_parents = 1,
 711                         .flags = CLK_SET_RATE_PARENT,
 712                         .ops = &clk_branch2_ops,
 713                 },
 714         },
 715 };
 716
 717 static struct clk_branch mdss_0_disp_cc_mdss_byte1_clk = {
 718         .halt_reg = 0x803c,
 719         .halt_check = BRANCH_HALT,
 720         .clkr = {
 721                 .enable_reg = 0x803c,
 722                 .enable_mask = BIT(0),
 723                 .hw.init = &(const struct clk_init_data) {
 724                         .name = "mdss_0_disp_cc_mdss_byte1_clk",
 725                         .parent_hws = (const struct clk_hw*[]) {
 726                                 &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw,
 727                         },
 728                         .num_parents = 1,
 729                         .flags = CLK_SET_RATE_PARENT,
 730                         .ops = &clk_branch2_ops,
 731                 },
 732         },
 733 };
 734
 735 static struct clk_branch mdss_0_disp_cc_mdss_byte1_intf_clk = {
 736         .halt_reg = 0x8040,
 737         .halt_check = BRANCH_HALT,
 738         .clkr = {
 739                 .enable_reg = 0x8040,
 740                 .enable_mask = BIT(0),
 741                 .hw.init = &(const struct clk_init_data) {
 742                         .name = "mdss_0_disp_cc_mdss_byte1_intf_clk",
 743                         .parent_hws = (const struct clk_hw*[]) {
 744                                 &mdss_0_disp_cc_mdss_byte1_div_clk_src.clkr.hw,
 745                         },
 746                         .num_parents = 1,
 747                         .flags = CLK_SET_RATE_PARENT,
 748                         .ops = &clk_branch2_ops,
 749                 },
 750         },
 751 };
 752
 753 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_aux_clk = {
 754         .halt_reg = 0x805c,
 755         .halt_check = BRANCH_HALT,
 756         .clkr = {
 757                 .enable_reg = 0x805c,
 758                 .enable_mask = BIT(0),
 759                 .hw.init = &(const struct clk_init_data) {
 760                         .name = "mdss_0_disp_cc_mdss_dptx0_aux_clk",
 761                         .parent_hws = (const struct clk_hw*[]) {
 762                                 &mdss_0_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
 763                         },
 764                         .num_parents = 1,
 765                         .flags = CLK_SET_RATE_PARENT,
 766                         .ops = &clk_branch2_ops,
 767                 },
 768         },
 769 };
 770
 771 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_crypto_clk = {
 772         .halt_reg = 0x8058,
 773         .halt_check = BRANCH_HALT,
 774         .clkr = {
 775                 .enable_reg = 0x8058,
 776                 .enable_mask = BIT(0),
 777                 .hw.init = &(const struct clk_init_data) {
 778                         .name = "mdss_0_disp_cc_mdss_dptx0_crypto_clk",
 779                         .parent_hws = (const struct clk_hw*[]) {
 780                                 &mdss_0_disp_cc_mdss_dptx0_crypto_clk_src.clkr.hw,
 781                         },
 782                         .num_parents = 1,
 783                         .flags = CLK_SET_RATE_PARENT,
 784                         .ops = &clk_branch2_ops,
 785                 },
 786         },
 787 };
 788
 789 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_clk = {
 790         .halt_reg = 0x804c,
 791         .halt_check = BRANCH_HALT,
 792         .clkr = {
 793                 .enable_reg = 0x804c,
 794                 .enable_mask = BIT(0),
 795                 .hw.init = &(const struct clk_init_data) {
 796                         .name = "mdss_0_disp_cc_mdss_dptx0_link_clk",
 797                         .parent_hws = (const struct clk_hw*[]) {
 798                                 &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
 799                         },
 800                         .num_parents = 1,
 801                         .flags = CLK_SET_RATE_PARENT,
 802                         .ops = &clk_branch2_ops,
 803                 },
 804         },
 805 };
 806
 807 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_intf_clk = {
 808         .halt_reg = 0x8050,
 809         .halt_check = BRANCH_HALT,
 810         .clkr = {
 811                 .enable_reg = 0x8050,
 812                 .enable_mask = BIT(0),
 813                 .hw.init = &(const struct clk_init_data) {
 814                         .name = "mdss_0_disp_cc_mdss_dptx0_link_intf_clk",
 815                         .parent_hws = (const struct clk_hw*[]) {
 816                                 &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
 817                         },
 818                         .num_parents = 1,
 819                         .flags = CLK_SET_RATE_PARENT,
 820                         .ops = &clk_branch2_ops,
 821                 },
 822         },
 823 };
 824
 825 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel0_clk = {
 826         .halt_reg = 0x8060,
 827         .halt_check = BRANCH_HALT,
 828         .clkr = {
 829                 .enable_reg = 0x8060,
 830                 .enable_mask = BIT(0),
 831                 .hw.init = &(const struct clk_init_data) {
 832                         .name = "mdss_0_disp_cc_mdss_dptx0_pixel0_clk",
 833                         .parent_hws = (const struct clk_hw*[]) {
 834                                 &mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
 835                         },
 836                         .num_parents = 1,
 837                         .flags = CLK_SET_RATE_PARENT,
 838                         .ops = &clk_branch2_ops,
 839                 },
 840         },
 841 };
 842
 843 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel1_clk = {
 844         .halt_reg = 0x8064,
 845         .halt_check = BRANCH_HALT,
 846         .clkr = {
 847                 .enable_reg = 0x8064,
 848                 .enable_mask = BIT(0),
 849                 .hw.init = &(const struct clk_init_data) {
 850                         .name = "mdss_0_disp_cc_mdss_dptx0_pixel1_clk",
 851                         .parent_hws = (const struct clk_hw*[]) {
 852                                 &mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
 853                         },
 854                         .num_parents = 1,
 855                         .flags = CLK_SET_RATE_PARENT,
 856                         .ops = &clk_branch2_ops,
 857                 },
 858         },
 859 };
 860
 861 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel2_clk = {
 862         .halt_reg = 0x8264,
 863         .halt_check = BRANCH_HALT,
 864         .clkr = {
 865                 .enable_reg = 0x8264,
 866                 .enable_mask = BIT(0),
 867                 .hw.init = &(const struct clk_init_data) {
 868                         .name = "mdss_0_disp_cc_mdss_dptx0_pixel2_clk",
 869                         .parent_hws = (const struct clk_hw*[]) {
 870                                 &mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw,
 871                         },
 872                         .num_parents = 1,
 873                         .flags = CLK_SET_RATE_PARENT,
 874                         .ops = &clk_branch2_ops,
 875                 },
 876         },
 877 };
 878
 879 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel3_clk = {
 880         .halt_reg = 0x8268,
 881         .halt_check = BRANCH_HALT,
 882         .clkr = {
 883                 .enable_reg = 0x8268,
 884                 .enable_mask = BIT(0),
 885                 .hw.init = &(const struct clk_init_data) {
 886                         .name = "mdss_0_disp_cc_mdss_dptx0_pixel3_clk",
 887                         .parent_hws = (const struct clk_hw*[]) {
 888                                 &mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw,
 889                         },
 890                         .num_parents = 1,
 891                         .flags = CLK_SET_RATE_PARENT,
 892                         .ops = &clk_branch2_ops,
 893                 },
 894         },
 895 };
 896
 897 static struct clk_branch mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
 898         .halt_reg = 0x8054,
 899         .halt_check = BRANCH_HALT,
 900         .clkr = {
 901                 .enable_reg = 0x8054,
 902                 .enable_mask = BIT(0),
 903                 .hw.init = &(const struct clk_init_data) {
 904                         .name = "mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk",
 905                         .parent_hws = (const struct clk_hw*[]) {
 906                                 &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
 907                         },
 908                         .num_parents = 1,
 909                         .flags = CLK_SET_RATE_PARENT,
 910                         .ops = &clk_branch2_ops,
 911                 },
 912         },
 913 };
 914
 915 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_aux_clk = {
 916         .halt_reg = 0x8080,
 917         .halt_check = BRANCH_HALT,
 918         .clkr = {
 919                 .enable_reg = 0x8080,
 920                 .enable_mask = BIT(0),
 921                 .hw.init = &(const struct clk_init_data) {
 922                         .name = "mdss_0_disp_cc_mdss_dptx1_aux_clk",
 923                         .parent_hws = (const struct clk_hw*[]) {
 924                                 &mdss_0_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
 925                         },
 926                         .num_parents = 1,
 927                         .flags = CLK_SET_RATE_PARENT,
 928                         .ops = &clk_branch2_ops,
 929                 },
 930         },
 931 };
 932
 933 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_crypto_clk = {
 934         .halt_reg = 0x807c,
 935         .halt_check = BRANCH_HALT,
 936         .clkr = {
 937                 .enable_reg = 0x807c,
 938                 .enable_mask = BIT(0),
 939                 .hw.init = &(const struct clk_init_data) {
 940                         .name = "mdss_0_disp_cc_mdss_dptx1_crypto_clk",
 941                         .parent_hws = (const struct clk_hw*[]) {
 942                                 &mdss_0_disp_cc_mdss_dptx1_crypto_clk_src.clkr.hw,
 943                         },
 944                         .num_parents = 1,
 945                         .flags = CLK_SET_RATE_PARENT,
 946                         .ops = &clk_branch2_ops,
 947                 },
 948         },
 949 };
 950
 951 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_clk = {
 952         .halt_reg = 0x8070,
 953         .halt_check = BRANCH_HALT,
 954         .clkr = {
 955                 .enable_reg = 0x8070,
 956                 .enable_mask = BIT(0),
 957                 .hw.init = &(const struct clk_init_data) {
 958                         .name = "mdss_0_disp_cc_mdss_dptx1_link_clk",
 959                         .parent_hws = (const struct clk_hw*[]) {
 960                                 &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
 961                         },
 962                         .num_parents = 1,
 963                         .flags = CLK_SET_RATE_PARENT,
 964                         .ops = &clk_branch2_ops,
 965                 },
 966         },
 967 };
 968
 969 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_intf_clk = {
 970         .halt_reg = 0x8074,
 971         .halt_check = BRANCH_HALT,
 972         .clkr = {
 973                 .enable_reg = 0x8074,
 974                 .enable_mask = BIT(0),
 975                 .hw.init = &(const struct clk_init_data) {
 976                         .name = "mdss_0_disp_cc_mdss_dptx1_link_intf_clk",
 977                         .parent_hws = (const struct clk_hw*[]) {
 978                                 &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
 979                         },
 980                         .num_parents = 1,
 981                         .flags = CLK_SET_RATE_PARENT,
 982                         .ops = &clk_branch2_ops,
 983                 },
 984         },
 985 };
 986
 987 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel0_clk = {
 988         .halt_reg = 0x8068,
 989         .halt_check = BRANCH_HALT,
 990         .clkr = {
 991                 .enable_reg = 0x8068,
 992                 .enable_mask = BIT(0),
 993                 .hw.init = &(const struct clk_init_data) {
 994                         .name = "mdss_0_disp_cc_mdss_dptx1_pixel0_clk",
 995                         .parent_hws = (const struct clk_hw*[]) {
 996                                 &mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
 997                         },
 998                         .num_parents = 1,
 999                         .flags = CLK_SET_RATE_PARENT,
1000                         .ops = &clk_branch2_ops,
1001                 },
1002         },
1003 };
1004
1005 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel1_clk = {
1006         .halt_reg = 0x806c,
1007         .halt_check = BRANCH_HALT,
1008         .clkr = {
1009                 .enable_reg = 0x806c,
1010                 .enable_mask = BIT(0),
1011                 .hw.init = &(const struct clk_init_data) {
1012                         .name = "mdss_0_disp_cc_mdss_dptx1_pixel1_clk",
1013                         .parent_hws = (const struct clk_hw*[]) {
1014                                 &mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1015                         },
1016                         .num_parents = 1,
1017                         .flags = CLK_SET_RATE_PARENT,
1018                         .ops = &clk_branch2_ops,
1019                 },
1020         },
1021 };
1022
1023 static struct clk_branch mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1024         .halt_reg = 0x8078,
1025         .halt_check = BRANCH_HALT,
1026         .clkr = {
1027                 .enable_reg = 0x8078,
1028                 .enable_mask = BIT(0),
1029                 .hw.init = &(const struct clk_init_data) {
1030                         .name = "mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1031                         .parent_hws = (const struct clk_hw*[]) {
1032                                 &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1033                         },
1034                         .num_parents = 1,
1035                         .flags = CLK_SET_RATE_PARENT,
1036                         .ops = &clk_branch2_ops,
1037                 },
1038         },
1039 };
1040
1041 static struct clk_branch mdss_0_disp_cc_mdss_esc0_clk = {
1042         .halt_reg = 0x8044,
1043         .halt_check = BRANCH_HALT,
1044         .clkr = {
1045                 .enable_reg = 0x8044,
1046                 .enable_mask = BIT(0),
1047                 .hw.init = &(const struct clk_init_data) {
1048                         .name = "mdss_0_disp_cc_mdss_esc0_clk",
1049                         .parent_hws = (const struct clk_hw*[]) {
1050                                 &mdss_0_disp_cc_mdss_esc0_clk_src.clkr.hw,
1051                         },
1052                         .num_parents = 1,
1053                         .flags = CLK_SET_RATE_PARENT,
1054                         .ops = &clk_branch2_ops,
1055                 },
1056         },
1057 };
1058
1059 static struct clk_branch mdss_0_disp_cc_mdss_esc1_clk = {
1060         .halt_reg = 0x8048,
1061         .halt_check = BRANCH_HALT,
1062         .clkr = {
1063                 .enable_reg = 0x8048,
1064                 .enable_mask = BIT(0),
1065                 .hw.init = &(const struct clk_init_data) {
1066                         .name = "mdss_0_disp_cc_mdss_esc1_clk",
1067                         .parent_hws = (const struct clk_hw*[]) {
1068                                 &mdss_0_disp_cc_mdss_esc1_clk_src.clkr.hw,
1069                         },
1070                         .num_parents = 1,
1071                         .flags = CLK_SET_RATE_PARENT,
1072                         .ops = &clk_branch2_ops,
1073                 },
1074         },
1075 };
1076
1077 static struct clk_branch mdss_0_disp_cc_mdss_mdp1_clk = {
1078         .halt_reg = 0x8014,
1079         .halt_check = BRANCH_HALT,
1080         .clkr = {
1081                 .enable_reg = 0x8014,
1082                 .enable_mask = BIT(0),
1083                 .hw.init = &(const struct clk_init_data) {
1084                         .name = "mdss_0_disp_cc_mdss_mdp1_clk",
1085                         .parent_hws = (const struct clk_hw*[]) {
1086                                 &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1087                         },
1088                         .num_parents = 1,
1089                         .flags = CLK_SET_RATE_PARENT,
1090                         .ops = &clk_branch2_ops,
1091                 },
1092         },
1093 };
1094
1095 static struct clk_branch mdss_0_disp_cc_mdss_mdp_clk = {
1096         .halt_reg = 0x800c,
1097         .halt_check = BRANCH_HALT,
1098         .clkr = {
1099                 .enable_reg = 0x800c,
1100                 .enable_mask = BIT(0),
1101                 .hw.init = &(const struct clk_init_data) {
1102                         .name = "mdss_0_disp_cc_mdss_mdp_clk",
1103                         .parent_hws = (const struct clk_hw*[]) {
1104                                 &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1105                         },
1106                         .num_parents = 1,
1107                         .flags = CLK_SET_RATE_PARENT,
1108                         .ops = &clk_branch2_ops,
1109                 },
1110         },
1111 };
1112
1113 static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut1_clk = {
1114         .halt_reg = 0x8024,
1115         .halt_check = BRANCH_HALT_VOTED,
1116         .clkr = {
1117                 .enable_reg = 0x8024,
1118                 .enable_mask = BIT(0),
1119                 .hw.init = &(const struct clk_init_data) {
1120                         .name = "mdss_0_disp_cc_mdss_mdp_lut1_clk",
1121                         .parent_hws = (const struct clk_hw*[]) {
1122                                 &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1123                         },
1124                         .num_parents = 1,
1125                         .flags = CLK_SET_RATE_PARENT,
1126                         .ops = &clk_branch2_ops,
1127                 },
1128         },
1129 };
1130
1131 static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut_clk = {
1132         .halt_reg = 0x801c,
1133         .halt_check = BRANCH_HALT_VOTED,
1134         .clkr = {
1135                 .enable_reg = 0x801c,
1136                 .enable_mask = BIT(0),
1137                 .hw.init = &(const struct clk_init_data) {
1138                         .name = "mdss_0_disp_cc_mdss_mdp_lut_clk",
1139                         .parent_hws = (const struct clk_hw*[]) {
1140                                 &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1141                         },
1142                         .num_parents = 1,
1143                         .flags = CLK_SET_RATE_PARENT,
1144                         .ops = &clk_branch2_ops,
1145                 },
1146         },
1147 };
1148
1149 static struct clk_branch mdss_0_disp_cc_mdss_non_gdsc_ahb_clk = {
1150         .halt_reg = 0xa004,
1151         .halt_check = BRANCH_HALT_VOTED,
1152         .clkr = {
1153                 .enable_reg = 0xa004,
1154                 .enable_mask = BIT(0),
1155                 .hw.init = &(const struct clk_init_data) {
1156                         .name = "mdss_0_disp_cc_mdss_non_gdsc_ahb_clk",
1157                         .parent_hws = (const struct clk_hw*[]) {
1158                                 &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
1159                         },
1160                         .num_parents = 1,
1161                         .flags = CLK_SET_RATE_PARENT,
1162                         .ops = &clk_branch2_ops,
1163                 },
1164         },
1165 };
1166
1167 static struct clk_branch mdss_0_disp_cc_mdss_pclk0_clk = {
1168         .halt_reg = 0x8004,
1169         .halt_check = BRANCH_HALT,
1170         .clkr = {
1171                 .enable_reg = 0x8004,
1172                 .enable_mask = BIT(0),
1173                 .hw.init = &(const struct clk_init_data) {
1174                         .name = "mdss_0_disp_cc_mdss_pclk0_clk",
1175                         .parent_hws = (const struct clk_hw*[]) {
1176                                 &mdss_0_disp_cc_mdss_pclk0_clk_src.clkr.hw,
1177                         },
1178                         .num_parents = 1,
1179                         .flags = CLK_SET_RATE_PARENT,
1180                         .ops = &clk_branch2_ops,
1181                 },
1182         },
1183 };
1184
1185 static struct clk_branch mdss_0_disp_cc_mdss_pclk1_clk = {
1186         .halt_reg = 0x8008,
1187         .halt_check = BRANCH_HALT,
1188         .clkr = {
1189                 .enable_reg = 0x8008,
1190                 .enable_mask = BIT(0),
1191                 .hw.init = &(const struct clk_init_data) {
1192                         .name = "mdss_0_disp_cc_mdss_pclk1_clk",
1193                         .parent_hws = (const struct clk_hw*[]) {
1194                                 &mdss_0_disp_cc_mdss_pclk1_clk_src.clkr.hw,
1195                         },
1196                         .num_parents = 1,
1197                         .flags = CLK_SET_RATE_PARENT,
1198                         .ops = &clk_branch2_ops,
1199                 },
1200         },
1201 };
1202
1203 static struct clk_branch mdss_0_disp_cc_mdss_pll_lock_monitor_clk = {
1204         .halt_reg = 0xe000,
1205         .halt_check = BRANCH_HALT,
1206         .clkr = {
1207                 .enable_reg = 0xe000,
1208                 .enable_mask = BIT(0),
1209                 .hw.init = &(const struct clk_init_data) {
1210                         .name = "mdss_0_disp_cc_mdss_pll_lock_monitor_clk",
1211                         .parent_hws = (const struct clk_hw*[]) {
1212                                 &mdss_0_disp_cc_xo_clk_src.clkr.hw,
1213                         },
1214                         .num_parents = 1,
1215                         .flags = CLK_SET_RATE_PARENT,
1216                         .ops = &clk_branch2_ops,
1217                 },
1218         },
1219 };
1220
1221 static struct clk_branch mdss_0_disp_cc_mdss_rscc_ahb_clk = {
1222         .halt_reg = 0xa00c,
1223         .halt_check = BRANCH_HALT,
1224         .clkr = {
1225                 .enable_reg = 0xa00c,
1226                 .enable_mask = BIT(0),
1227                 .hw.init = &(const struct clk_init_data) {
1228                         .name = "mdss_0_disp_cc_mdss_rscc_ahb_clk",
1229                         .parent_hws = (const struct clk_hw*[]) {
1230                                 &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
1231                         },
1232                         .num_parents = 1,
1233                         .flags = CLK_SET_RATE_PARENT,
1234                         .ops = &clk_branch2_ops,
1235                 },
1236         },
1237 };
1238
1239 static struct clk_branch mdss_0_disp_cc_mdss_rscc_vsync_clk = {
1240         .halt_reg = 0xa008,
1241         .halt_check = BRANCH_HALT,
1242         .clkr = {
1243                 .enable_reg = 0xa008,
1244                 .enable_mask = BIT(0),
1245                 .hw.init = &(const struct clk_init_data) {
1246                         .name = "mdss_0_disp_cc_mdss_rscc_vsync_clk",
1247                         .parent_hws = (const struct clk_hw*[]) {
1248                                 &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw,
1249                         },
1250                         .num_parents = 1,
1251                         .flags = CLK_SET_RATE_PARENT,
1252                         .ops = &clk_branch2_ops,
1253                 },
1254         },
1255 };
1256
1257 static struct clk_branch mdss_0_disp_cc_mdss_vsync1_clk = {
1258         .halt_reg = 0x8030,
1259         .halt_check = BRANCH_HALT,
1260         .clkr = {
1261                 .enable_reg = 0x8030,
1262                 .enable_mask = BIT(0),
1263                 .hw.init = &(const struct clk_init_data) {
1264                         .name = "mdss_0_disp_cc_mdss_vsync1_clk",
1265                         .parent_hws = (const struct clk_hw*[]) {
1266                                 &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw,
1267                         },
1268                         .num_parents = 1,
1269                         .flags = CLK_SET_RATE_PARENT,
1270                         .ops = &clk_branch2_ops,
1271                 },
1272         },
1273 };
1274
1275 static struct clk_branch mdss_0_disp_cc_mdss_vsync_clk = {
1276         .halt_reg = 0x802c,
1277         .halt_check = BRANCH_HALT,
1278         .clkr = {
1279                 .enable_reg = 0x802c,
1280                 .enable_mask = BIT(0),
1281                 .hw.init = &(const struct clk_init_data) {
1282                         .name = "mdss_0_disp_cc_mdss_vsync_clk",
1283                         .parent_hws = (const struct clk_hw*[]) {
1284                                 &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw,
1285                         },
1286                         .num_parents = 1,
1287                         .flags = CLK_SET_RATE_PARENT,
1288                         .ops = &clk_branch2_ops,
1289                 },
1290         },
1291 };
1292
1293 static struct clk_branch mdss_0_disp_cc_sm_obs_clk = {
1294         .halt_reg = 0x11014,
1295         .halt_check = BRANCH_HALT_SKIP,
1296         .clkr = {
1297                 .enable_reg = 0x11014,
1298                 .enable_mask = BIT(0),
1299                 .hw.init = &(const struct clk_init_data) {
1300                         .name = "mdss_0_disp_cc_sm_obs_clk",
1301                         .ops = &clk_branch2_ops,
1302                 },
1303         },
1304 };
1305
1306 static struct gdsc mdss_0_disp_cc_mdss_core_gdsc = {
1307         .gdscr = 0x9000,
1308         .en_rest_wait_val = 0x2,
1309         .en_few_wait_val = 0x2,
1310         .clk_dis_wait_val = 0xf,
1311         .pd = {
1312                 .name = "mdss_0_disp_cc_mdss_core_gdsc",
1313         },
1314         .pwrsts = PWRSTS_OFF_ON,
1315         .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
1316 };
1317
1318 static struct gdsc mdss_0_disp_cc_mdss_core_int2_gdsc = {
1319         .gdscr = 0xd000,
1320         .en_rest_wait_val = 0x2,
1321         .en_few_wait_val = 0x2,
1322         .clk_dis_wait_val = 0xf,
1323         .pd = {
1324                 .name = "mdss_0_disp_cc_mdss_core_int2_gdsc",
1325         },
1326         .pwrsts = PWRSTS_OFF_ON,
1327         .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
1328 };
1329
1330 static struct clk_regmap *disp_cc_0_sa8775p_clocks[] = {
1331         [MDSS_DISP_CC_MDSS_AHB1_CLK] = &mdss_0_disp_cc_mdss_ahb1_clk.clkr,
1332         [MDSS_DISP_CC_MDSS_AHB_CLK] = &mdss_0_disp_cc_mdss_ahb_clk.clkr,
1333         [MDSS_DISP_CC_MDSS_AHB_CLK_SRC] = &mdss_0_disp_cc_mdss_ahb_clk_src.clkr,
1334         [MDSS_DISP_CC_MDSS_BYTE0_CLK] = &mdss_0_disp_cc_mdss_byte0_clk.clkr,
1335         [MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC] = &mdss_0_disp_cc_mdss_byte0_clk_src.clkr,
1336         [MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &mdss_0_disp_cc_mdss_byte0_div_clk_src.clkr,
1337         [MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK] = &mdss_0_disp_cc_mdss_byte0_intf_clk.clkr,
1338         [MDSS_DISP_CC_MDSS_BYTE1_CLK] = &mdss_0_disp_cc_mdss_byte1_clk.clkr,
1339         [MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC] = &mdss_0_disp_cc_mdss_byte1_clk_src.clkr,
1340         [MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &mdss_0_disp_cc_mdss_byte1_div_clk_src.clkr,
1341         [MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK] = &mdss_0_disp_cc_mdss_byte1_intf_clk.clkr,
1342         [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK] = &mdss_0_disp_cc_mdss_dptx0_aux_clk.clkr,
1343         [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_aux_clk_src.clkr,
1344         [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &mdss_0_disp_cc_mdss_dptx0_crypto_clk.clkr,
1345         [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_crypto_clk_src.clkr,
1346         [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK] = &mdss_0_disp_cc_mdss_dptx0_link_clk.clkr,
1347         [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr,
1348         [MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =
1349               &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1350         [MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &mdss_0_disp_cc_mdss_dptx0_link_intf_clk.clkr,
1351         [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel0_clk.clkr,
1352         [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1353         [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel1_clk.clkr,
1354         [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1355         [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel2_clk.clkr,
1356         [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src.clkr,
1357         [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel3_clk.clkr,
1358         [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src.clkr,
1359         [MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1360               &mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1361         [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK] = &mdss_0_disp_cc_mdss_dptx1_aux_clk.clkr,
1362         [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_aux_clk_src.clkr,
1363         [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &mdss_0_disp_cc_mdss_dptx1_crypto_clk.clkr,
1364         [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_crypto_clk_src.clkr,
1365         [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK] = &mdss_0_disp_cc_mdss_dptx1_link_clk.clkr,
1366         [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr,
1367         [MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =
1368               &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1369         [MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &mdss_0_disp_cc_mdss_dptx1_link_intf_clk.clkr,
1370         [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &mdss_0_disp_cc_mdss_dptx1_pixel0_clk.clkr,
1371         [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1372         [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &mdss_0_disp_cc_mdss_dptx1_pixel1_clk.clkr,
1373         [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1374         [MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1375               &mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1376         [MDSS_DISP_CC_MDSS_ESC0_CLK] = &mdss_0_disp_cc_mdss_esc0_clk.clkr,
1377         [MDSS_DISP_CC_MDSS_ESC0_CLK_SRC] = &mdss_0_disp_cc_mdss_esc0_clk_src.clkr,
1378         [MDSS_DISP_CC_MDSS_ESC1_CLK] = &mdss_0_disp_cc_mdss_esc1_clk.clkr,
1379         [MDSS_DISP_CC_MDSS_ESC1_CLK_SRC] = &mdss_0_disp_cc_mdss_esc1_clk_src.clkr,
1380         [MDSS_DISP_CC_MDSS_MDP1_CLK] = &mdss_0_disp_cc_mdss_mdp1_clk.clkr,
1381         [MDSS_DISP_CC_MDSS_MDP_CLK] = &mdss_0_disp_cc_mdss_mdp_clk.clkr,
1382         [MDSS_DISP_CC_MDSS_MDP_CLK_SRC] = &mdss_0_disp_cc_mdss_mdp_clk_src.clkr,
1383         [MDSS_DISP_CC_MDSS_MDP_LUT1_CLK] = &mdss_0_disp_cc_mdss_mdp_lut1_clk.clkr,
1384         [MDSS_DISP_CC_MDSS_MDP_LUT_CLK] = &mdss_0_disp_cc_mdss_mdp_lut_clk.clkr,
1385         [MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &mdss_0_disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1386         [MDSS_DISP_CC_MDSS_PCLK0_CLK] = &mdss_0_disp_cc_mdss_pclk0_clk.clkr,
1387         [MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC] = &mdss_0_disp_cc_mdss_pclk0_clk_src.clkr,
1388         [MDSS_DISP_CC_MDSS_PCLK1_CLK] = &mdss_0_disp_cc_mdss_pclk1_clk.clkr,
1389         [MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC] = &mdss_0_disp_cc_mdss_pclk1_clk_src.clkr,
1390         [MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK] = &mdss_0_disp_cc_mdss_pll_lock_monitor_clk.clkr,
1391         [MDSS_DISP_CC_MDSS_RSCC_AHB_CLK] = &mdss_0_disp_cc_mdss_rscc_ahb_clk.clkr,
1392         [MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK] = &mdss_0_disp_cc_mdss_rscc_vsync_clk.clkr,
1393         [MDSS_DISP_CC_MDSS_VSYNC1_CLK] = &mdss_0_disp_cc_mdss_vsync1_clk.clkr,
1394         [MDSS_DISP_CC_MDSS_VSYNC_CLK] = &mdss_0_disp_cc_mdss_vsync_clk.clkr,
1395         [MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC] = &mdss_0_disp_cc_mdss_vsync_clk_src.clkr,
1396         [MDSS_DISP_CC_PLL0] = &mdss_0_disp_cc_pll0.clkr,
1397         [MDSS_DISP_CC_PLL1] = &mdss_0_disp_cc_pll1.clkr,
1398         [MDSS_DISP_CC_SLEEP_CLK_SRC] = &mdss_0_disp_cc_sleep_clk_src.clkr,
1399         [MDSS_DISP_CC_SM_OBS_CLK] = &mdss_0_disp_cc_sm_obs_clk.clkr,
1400         [MDSS_DISP_CC_XO_CLK_SRC] = &mdss_0_disp_cc_xo_clk_src.clkr,
1401 };
1402
1403 static struct gdsc *disp_cc_0_sa8775p_gdscs[] = {
1404         [MDSS_DISP_CC_MDSS_CORE_GDSC] = &mdss_0_disp_cc_mdss_core_gdsc,
1405         [MDSS_DISP_CC_MDSS_CORE_INT2_GDSC] = &mdss_0_disp_cc_mdss_core_int2_gdsc,
1406 };
1407
1408 static const struct qcom_reset_map disp_cc_0_sa8775p_resets[] = {
1409         [MDSS_DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1410         [MDSS_DISP_CC_MDSS_RSCC_BCR] = { 0xa000 },
1411 };
1412
1413 static const struct regmap_config disp_cc_0_sa8775p_regmap_config = {
1414         .reg_bits = 32,
1415         .reg_stride = 4,
1416         .val_bits = 32,
1417         .max_register = 0x12414,
1418         .fast_io = true,
1419 };
1420
1421 static struct qcom_cc_desc disp_cc_0_sa8775p_desc = {
1422         .config = &disp_cc_0_sa8775p_regmap_config,
1423         .clks = disp_cc_0_sa8775p_clocks,
1424         .num_clks = ARRAY_SIZE(disp_cc_0_sa8775p_clocks),
1425         .resets = disp_cc_0_sa8775p_resets,
1426         .num_resets = ARRAY_SIZE(disp_cc_0_sa8775p_resets),
1427         .gdscs = disp_cc_0_sa8775p_gdscs,
1428         .num_gdscs = ARRAY_SIZE(disp_cc_0_sa8775p_gdscs),
1429 };
1430
1431 static const struct of_device_id disp_cc_0_sa8775p_match_table[] = {
1432         { .compatible = "qcom,sa8775p-dispcc0" },
1433         { }
1434 };
1435 MODULE_DEVICE_TABLE(of, disp_cc_0_sa8775p_match_table);
1436
1437 static int disp_cc_0_sa8775p_probe(struct platform_device *pdev)
1438 {
1439         struct regmap *regmap;
1440         int ret;
1441
1442         ret = devm_pm_runtime_enable(&pdev->dev);
1443         if (ret)
1444                 return ret;
1445
1446         ret = pm_runtime_resume_and_get(&pdev->dev);
1447         if (ret)
1448                 return ret;
1449
1450         regmap = qcom_cc_map(pdev, &disp_cc_0_sa8775p_desc);
1451         if (IS_ERR(regmap)) {
1452                 pm_runtime_put(&pdev->dev);
1453                 return PTR_ERR(regmap);
1454         }
1455
1456         clk_lucid_evo_pll_configure(&mdss_0_disp_cc_pll0, regmap, &mdss_0_disp_cc_pll0_config);
1457         clk_lucid_evo_pll_configure(&mdss_0_disp_cc_pll1, regmap, &mdss_0_disp_cc_pll1_config);
1458
1459         /* Keep some clocks always enabled */
1460         qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_0_DISP_CC_SLEEP_CLK */
1461         qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_0_DISP_CC_XO_CLK */
1462
1463         ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_0_sa8775p_desc, regmap);
1464
1465         pm_runtime_put(&pdev->dev);
1466
1467         return ret;
1468 }
1469
1470 static struct platform_driver disp_cc_0_sa8775p_driver = {
1471         .probe = disp_cc_0_sa8775p_probe,
1472         .driver = {
1473                 .name = "dispcc0-sa8775p",
1474                 .of_match_table = disp_cc_0_sa8775p_match_table,
1475         },
1476 };
1477
1478 module_platform_driver(disp_cc_0_sa8775p_driver);
1479
1480 MODULE_DESCRIPTION("QTI DISPCC0 SA8775P Driver");
1481 MODULE_LICENSE("GPL");