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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / clk / qcom / gcc-qdu1000.c
blobdbe9e9437939afbcd50759dfc21a599864278816
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
13
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "clk-regmap-phy-mux.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 P_BI_TCXO,
26 P_GCC_GPLL0_OUT_EVEN,
27 P_GCC_GPLL0_OUT_MAIN,
28 P_GCC_GPLL1_OUT_MAIN,
29 P_GCC_GPLL2_OUT_MAIN,
30 P_GCC_GPLL3_OUT_MAIN,
31 P_GCC_GPLL4_OUT_MAIN,
32 P_GCC_GPLL5_OUT_MAIN,
33 P_GCC_GPLL6_OUT_MAIN,
34 P_GCC_GPLL7_OUT_MAIN,
35 P_GCC_GPLL8_OUT_MAIN,
36 P_PCIE_0_PHY_AUX_CLK,
37 P_PCIE_0_PIPE_CLK,
38 P_SLEEP_CLK,
39 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
40 };
41
42 enum {
43 DT_TCXO_IDX,
44 DT_SLEEP_CLK_IDX,
45 DT_PCIE_0_PIPE_CLK_IDX,
46 DT_PCIE_0_PHY_AUX_CLK_IDX,
47 DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX,
48 };
49
50 static struct clk_alpha_pll gcc_gpll0 = {
51 .offset = 0x0,
52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
53 .clkr = {
54 .enable_reg = 0x62018,
55 .enable_mask = BIT(0),
56 .hw.init = &(const struct clk_init_data) {
57 .name = "gcc_gpll0",
58 .parent_data = &(const struct clk_parent_data) {
59 .index = DT_TCXO_IDX,
60 },
61 .num_parents = 1,
62 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
63 },
64 },
65 };
66
67 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
68 { 0x1, 2 }
69 };
70
71 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
72 .offset = 0x0,
73 .post_div_shift = 10,
74 .post_div_table = post_div_table_gcc_gpll0_out_even,
75 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
76 .width = 4,
77 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
78 .clkr.hw.init = &(const struct clk_init_data) {
79 .name = "gcc_gpll0_out_even",
80 .parent_hws = (const struct clk_hw*[]) {
81 &gcc_gpll0.clkr.hw,
82 },
83 .num_parents = 1,
84 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
85 },
86 };
87
88 static struct clk_alpha_pll gcc_gpll1 = {
89 .offset = 0x1000,
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
91 .clkr = {
92 .enable_reg = 0x62018,
93 .enable_mask = BIT(1),
94 .hw.init = &(const struct clk_init_data) {
95 .name = "gcc_gpll1",
96 .parent_data = &(const struct clk_parent_data) {
97 .index = DT_TCXO_IDX,
98 },
99 .num_parents = 1,
100 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
101 },
102 },
103 };
104
105 static struct clk_alpha_pll_postdiv gcc_gpll1_out_even = {
106 .offset = 0x1000,
107 .post_div_shift = 10,
108 .post_div_table = post_div_table_gcc_gpll0_out_even,
109 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
110 .width = 4,
111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
112 .clkr.hw.init = &(const struct clk_init_data) {
113 .name = "gcc_gpll1_out_even",
114 .parent_hws = (const struct clk_hw*[]) {
115 &gcc_gpll1.clkr.hw,
116 },
117 .num_parents = 1,
118 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
119 },
120 };
121
122 static struct clk_alpha_pll gcc_gpll2 = {
123 .offset = 0x2000,
124 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
125 .clkr = {
126 .enable_reg = 0x62018,
127 .enable_mask = BIT(2),
128 .hw.init = &(const struct clk_init_data) {
129 .name = "gcc_gpll2",
130 .parent_data = &(const struct clk_parent_data) {
131 .index = DT_TCXO_IDX,
132 },
133 .num_parents = 1,
134 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
135 },
136 },
137 };
138
139 static struct clk_alpha_pll_postdiv gcc_gpll2_out_even = {
140 .offset = 0x2000,
141 .post_div_shift = 10,
142 .post_div_table = post_div_table_gcc_gpll0_out_even,
143 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
144 .width = 4,
145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
146 .clkr.hw.init = &(const struct clk_init_data) {
147 .name = "gcc_gpll2_out_even",
148 .parent_hws = (const struct clk_hw*[]) {
149 &gcc_gpll2.clkr.hw,
150 },
151 .num_parents = 1,
152 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
153 },
154 };
155
156 static struct clk_alpha_pll gcc_gpll3 = {
157 .offset = 0x3000,
158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
159 .clkr = {
160 .enable_reg = 0x62018,
161 .enable_mask = BIT(3),
162 .hw.init = &(const struct clk_init_data) {
163 .name = "gcc_gpll3",
164 .parent_data = &(const struct clk_parent_data) {
165 .index = DT_TCXO_IDX,
166 },
167 .num_parents = 1,
168 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
169 },
170 },
171 };
172
173 static struct clk_alpha_pll gcc_gpll4 = {
174 .offset = 0x4000,
175 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
176 .clkr = {
177 .enable_reg = 0x62018,
178 .enable_mask = BIT(4),
179 .hw.init = &(const struct clk_init_data) {
180 .name = "gcc_gpll4",
181 .parent_data = &(const struct clk_parent_data) {
182 .index = DT_TCXO_IDX,
183 },
184 .num_parents = 1,
185 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
186 },
187 },
188 };
189
190 static struct clk_alpha_pll gcc_gpll5 = {
191 .offset = 0x5000,
192 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
193 .clkr = {
194 .enable_reg = 0x62018,
195 .enable_mask = BIT(5),
196 .hw.init = &(const struct clk_init_data) {
197 .name = "gcc_gpll5",
198 .parent_data = &(const struct clk_parent_data) {
199 .index = DT_TCXO_IDX,
200 },
201 .num_parents = 1,
202 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
203 },
204 },
205 };
206
207 static struct clk_alpha_pll_postdiv gcc_gpll5_out_even = {
208 .offset = 0x5000,
209 .post_div_shift = 10,
210 .post_div_table = post_div_table_gcc_gpll0_out_even,
211 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
212 .width = 4,
213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
214 .clkr.hw.init = &(const struct clk_init_data) {
215 .name = "gcc_gpll5_out_even",
216 .parent_hws = (const struct clk_hw*[]) {
217 &gcc_gpll5.clkr.hw,
218 },
219 .num_parents = 1,
220 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
221 },
222 };
223
224 static struct clk_alpha_pll gcc_gpll6 = {
225 .offset = 0x6000,
226 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
227 .clkr = {
228 .enable_reg = 0x62018,
229 .enable_mask = BIT(6),
230 .hw.init = &(const struct clk_init_data) {
231 .name = "gcc_gpll6",
232 .parent_data = &(const struct clk_parent_data) {
233 .index = DT_TCXO_IDX,
234 },
235 .num_parents = 1,
236 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
237 },
238 },
239 };
240
241 static struct clk_alpha_pll gcc_gpll7 = {
242 .offset = 0x7000,
243 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
244 .clkr = {
245 .enable_reg = 0x62018,
246 .enable_mask = BIT(7),
247 .hw.init = &(const struct clk_init_data) {
248 .name = "gcc_gpll7",
249 .parent_data = &(const struct clk_parent_data) {
250 .index = DT_TCXO_IDX,
251 },
252 .num_parents = 1,
253 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
254 },
255 },
256 };
257
258 static struct clk_alpha_pll gcc_gpll8 = {
259 .offset = 0x8000,
260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
261 .clkr = {
262 .enable_reg = 0x62018,
263 .enable_mask = BIT(8),
264 .hw.init = &(const struct clk_init_data) {
265 .name = "gcc_gpll8",
266 .parent_data = &(const struct clk_parent_data) {
267 .index = DT_TCXO_IDX,
268 },
269 .num_parents = 1,
270 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
271 },
272 },
273 };
274
275 static const struct parent_map gcc_parent_map_0[] = {
276 { P_BI_TCXO, 0 },
277 { P_GCC_GPLL0_OUT_MAIN, 1 },
278 { P_GCC_GPLL0_OUT_EVEN, 6 },
279 };
280
281 static const struct clk_parent_data gcc_parent_data_0[] = {
282 { .index = DT_TCXO_IDX },
283 { .hw = &gcc_gpll0.clkr.hw },
284 { .hw = &gcc_gpll0_out_even.clkr.hw },
285 };
286
287 static const struct parent_map gcc_parent_map_1[] = {
288 { P_BI_TCXO, 0 },
289 { P_GCC_GPLL0_OUT_MAIN, 1 },
290 { P_SLEEP_CLK, 5 },
291 { P_GCC_GPLL0_OUT_EVEN, 6 },
292 };
293
294 static const struct clk_parent_data gcc_parent_data_1[] = {
295 { .index = DT_TCXO_IDX },
296 { .hw = &gcc_gpll0.clkr.hw },
297 { .index = DT_SLEEP_CLK_IDX },
298 { .hw = &gcc_gpll0_out_even.clkr.hw },
299 };
300
301 static const struct parent_map gcc_parent_map_2[] = {
302 { P_BI_TCXO, 0 },
303 { P_GCC_GPLL0_OUT_MAIN, 1 },
304 { P_GCC_GPLL5_OUT_MAIN, 3 },
305 { P_GCC_GPLL4_OUT_MAIN, 5 },
306 };
307
308 static const struct clk_parent_data gcc_parent_data_2[] = {
309 { .index = DT_TCXO_IDX },
310 { .hw = &gcc_gpll0.clkr.hw },
311 { .hw = &gcc_gpll5.clkr.hw },
312 { .hw = &gcc_gpll4.clkr.hw },
313 };
314
315 static const struct parent_map gcc_parent_map_3[] = {
316 { P_BI_TCXO, 0 },
317 { P_SLEEP_CLK, 5 },
318 };
319
320 static const struct clk_parent_data gcc_parent_data_3[] = {
321 { .index = DT_TCXO_IDX },
322 { .index = DT_SLEEP_CLK_IDX },
323 };
324
325 static const struct parent_map gcc_parent_map_4[] = {
326 { P_BI_TCXO, 0 },
327 { P_GCC_GPLL0_OUT_MAIN, 1 },
328 { P_GCC_GPLL2_OUT_MAIN, 2 },
329 { P_GCC_GPLL5_OUT_MAIN, 3 },
330 { P_GCC_GPLL1_OUT_MAIN, 4 },
331 { P_GCC_GPLL4_OUT_MAIN, 5 },
332 { P_GCC_GPLL3_OUT_MAIN, 6 },
333 };
334
335 static const struct clk_parent_data gcc_parent_data_4[] = {
336 { .index = DT_TCXO_IDX },
337 { .hw = &gcc_gpll0.clkr.hw },
338 { .hw = &gcc_gpll2.clkr.hw },
339 { .hw = &gcc_gpll5.clkr.hw },
340 { .hw = &gcc_gpll1.clkr.hw },
341 { .hw = &gcc_gpll4.clkr.hw },
342 { .hw = &gcc_gpll3.clkr.hw },
343 };
344
345 static const struct parent_map gcc_parent_map_5[] = {
346 { P_BI_TCXO, 0 },
347 { P_GCC_GPLL0_OUT_MAIN, 1 },
348 { P_GCC_GPLL2_OUT_MAIN, 2 },
349 { P_GCC_GPLL6_OUT_MAIN, 3 },
350 { P_GCC_GPLL1_OUT_MAIN, 4 },
351 { P_GCC_GPLL4_OUT_MAIN, 5 },
352 { P_GCC_GPLL3_OUT_MAIN, 6 },
353 };
354
355 static const struct clk_parent_data gcc_parent_data_5[] = {
356 { .index = DT_TCXO_IDX },
357 { .hw = &gcc_gpll0.clkr.hw },
358 { .hw = &gcc_gpll2.clkr.hw },
359 { .hw = &gcc_gpll6.clkr.hw },
360 { .hw = &gcc_gpll1.clkr.hw },
361 { .hw = &gcc_gpll4.clkr.hw },
362 { .hw = &gcc_gpll3.clkr.hw },
363 };
364
365 static const struct parent_map gcc_parent_map_6[] = {
366 { P_PCIE_0_PHY_AUX_CLK, 0 },
367 { P_BI_TCXO, 2 },
368 };
369
370 static const struct clk_parent_data gcc_parent_data_6[] = {
371 { .index = DT_PCIE_0_PHY_AUX_CLK_IDX },
372 { .index = DT_TCXO_IDX },
373 };
374
375 static const struct parent_map gcc_parent_map_8[] = {
376 { P_BI_TCXO, 0 },
377 { P_GCC_GPLL0_OUT_MAIN, 1 },
378 { P_GCC_GPLL8_OUT_MAIN, 2 },
379 { P_GCC_GPLL5_OUT_MAIN, 3 },
380 { P_GCC_GPLL4_OUT_MAIN, 5 },
381 };
382
383 static const struct clk_parent_data gcc_parent_data_8[] = {
384 { .index = DT_TCXO_IDX },
385 { .hw = &gcc_gpll0.clkr.hw },
386 { .hw = &gcc_gpll8.clkr.hw },
387 { .hw = &gcc_gpll5.clkr.hw },
388 { .hw = &gcc_gpll4.clkr.hw },
389 };
390
391 static const struct parent_map gcc_parent_map_9[] = {
392 { P_BI_TCXO, 0 },
393 { P_GCC_GPLL0_OUT_MAIN, 1 },
394 { P_GCC_GPLL2_OUT_MAIN, 2 },
395 { P_GCC_GPLL5_OUT_MAIN, 3 },
396 { P_GCC_GPLL7_OUT_MAIN, 4 },
397 { P_GCC_GPLL4_OUT_MAIN, 5 },
398 };
399
400 static const struct clk_parent_data gcc_parent_data_9[] = {
401 { .index = DT_TCXO_IDX },
402 { .hw = &gcc_gpll0.clkr.hw },
403 { .hw = &gcc_gpll2.clkr.hw },
404 { .hw = &gcc_gpll5.clkr.hw },
405 { .hw = &gcc_gpll7.clkr.hw },
406 { .hw = &gcc_gpll4.clkr.hw },
407 };
408
409 static const struct parent_map gcc_parent_map_10[] = {
410 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
411 { P_BI_TCXO, 2 },
412 };
413
414 static const struct clk_parent_data gcc_parent_data_10[] = {
415 { .index = DT_USB3_PHY_WRAPPER_PIPE_CLK_IDX },
416 { .index = DT_TCXO_IDX },
417 };
418
419 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
420 .reg = 0x9d080,
421 .shift = 0,
422 .width = 2,
423 .parent_map = gcc_parent_map_6,
424 .clkr = {
425 .hw.init = &(const struct clk_init_data) {
426 .name = "gcc_pcie_0_phy_aux_clk_src",
427 .parent_data = gcc_parent_data_6,
428 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
429 .ops = &clk_regmap_mux_closest_ops,
430 },
431 },
432 };
433
434 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
435 .reg = 0x9d064,
436 .clkr = {
437 .hw.init = &(const struct clk_init_data) {
438 .name = "gcc_pcie_0_pipe_clk_src",
439 .parent_data = &(const struct clk_parent_data){
440 .index = DT_PCIE_0_PIPE_CLK_IDX,
441 },
442 .num_parents = 1,
443 .ops = &clk_regmap_phy_mux_ops,
444 },
445 },
446 };
447
448 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
449 .reg = 0x4906c,
450 .shift = 0,
451 .width = 2,
452 .parent_map = gcc_parent_map_10,
453 .clkr = {
454 .hw.init = &(const struct clk_init_data) {
455 .name = "gcc_usb3_prim_phy_pipe_clk_src",
456 .parent_data = gcc_parent_data_10,
457 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
458 .ops = &clk_regmap_mux_closest_ops,
459 },
460 },
461 };
462
463 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_dma_clk_src[] = {
464 F(466500000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0),
465 F(500000000, P_GCC_GPLL2_OUT_MAIN, 2, 0, 0),
466 { }
467 };
468
469 static struct clk_rcg2 gcc_aggre_noc_ecpri_dma_clk_src = {
470 .cmd_rcgr = 0x92020,
471 .mnd_width = 0,
472 .hid_width = 5,
473 .parent_map = gcc_parent_map_4,
474 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_dma_clk_src,
475 .clkr.hw.init = &(const struct clk_init_data) {
476 .name = "gcc_aggre_noc_ecpri_dma_clk_src",
477 .parent_data = gcc_parent_data_4,
478 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
479 .ops = &clk_rcg2_shared_ops,
480 },
481 };
482
483 static const struct freq_tbl ftbl_gcc_aggre_noc_ecpri_gsi_clk_src[] = {
484 F(250000000, P_GCC_GPLL2_OUT_MAIN, 4, 0, 0),
485 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
486 { }
487 };
488
489 static struct clk_rcg2 gcc_aggre_noc_ecpri_gsi_clk_src = {
490 .cmd_rcgr = 0x92038,
491 .mnd_width = 0,
492 .hid_width = 5,
493 .parent_map = gcc_parent_map_5,
494 .freq_tbl = ftbl_gcc_aggre_noc_ecpri_gsi_clk_src,
495 .clkr.hw.init = &(const struct clk_init_data) {
496 .name = "gcc_aggre_noc_ecpri_gsi_clk_src",
497 .parent_data = gcc_parent_data_5,
498 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
499 .ops = &clk_rcg2_shared_ops,
500 },
501 };
502
503 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
504 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
505 { }
506 };
507
508 static struct clk_rcg2 gcc_gp1_clk_src = {
509 .cmd_rcgr = 0x74004,
510 .mnd_width = 16,
511 .hid_width = 5,
512 .parent_map = gcc_parent_map_1,
513 .freq_tbl = ftbl_gcc_gp1_clk_src,
514 .clkr.hw.init = &(const struct clk_init_data) {
515 .name = "gcc_gp1_clk_src",
516 .parent_data = gcc_parent_data_1,
517 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
518 .ops = &clk_rcg2_shared_ops,
519 },
520 };
521
522 static struct clk_rcg2 gcc_gp2_clk_src = {
523 .cmd_rcgr = 0x75004,
524 .mnd_width = 16,
525 .hid_width = 5,
526 .parent_map = gcc_parent_map_1,
527 .freq_tbl = ftbl_gcc_gp1_clk_src,
528 .clkr.hw.init = &(const struct clk_init_data) {
529 .name = "gcc_gp2_clk_src",
530 .parent_data = gcc_parent_data_1,
531 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
532 .ops = &clk_rcg2_shared_ops,
533 },
534 };
535
536 static struct clk_rcg2 gcc_gp3_clk_src = {
537 .cmd_rcgr = 0x76004,
538 .mnd_width = 16,
539 .hid_width = 5,
540 .parent_map = gcc_parent_map_1,
541 .freq_tbl = ftbl_gcc_gp1_clk_src,
542 .clkr.hw.init = &(const struct clk_init_data) {
543 .name = "gcc_gp3_clk_src",
544 .parent_data = gcc_parent_data_1,
545 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
546 .ops = &clk_rcg2_shared_ops,
547 },
548 };
549
550 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
551 F(19200000, P_BI_TCXO, 1, 0, 0),
552 { }
553 };
554
555 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
556 .cmd_rcgr = 0x9d068,
557 .mnd_width = 16,
558 .hid_width = 5,
559 .parent_map = gcc_parent_map_3,
560 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
561 .clkr.hw.init = &(const struct clk_init_data) {
562 .name = "gcc_pcie_0_aux_clk_src",
563 .parent_data = gcc_parent_data_3,
564 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
565 .ops = &clk_rcg2_shared_ops,
566 },
567 };
568
569 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
570 F(19200000, P_BI_TCXO, 1, 0, 0),
571 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
572 { }
573 };
574
575 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
576 .cmd_rcgr = 0x9d04c,
577 .mnd_width = 0,
578 .hid_width = 5,
579 .parent_map = gcc_parent_map_0,
580 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
581 .clkr.hw.init = &(const struct clk_init_data) {
582 .name = "gcc_pcie_0_phy_rchng_clk_src",
583 .parent_data = gcc_parent_data_0,
584 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
585 .ops = &clk_rcg2_shared_ops,
586 },
587 };
588
589 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
590 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
591 { }
592 };
593
594 static struct clk_rcg2 gcc_pdm2_clk_src = {
595 .cmd_rcgr = 0x43010,
596 .mnd_width = 0,
597 .hid_width = 5,
598 .parent_map = gcc_parent_map_0,
599 .freq_tbl = ftbl_gcc_pdm2_clk_src,
600 .clkr.hw.init = &(const struct clk_init_data) {
601 .name = "gcc_pdm2_clk_src",
602 .parent_data = gcc_parent_data_0,
603 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
604 .ops = &clk_rcg2_shared_ops,
605 },
606 };
607
608 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
609 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
610 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
611 F(19200000, P_BI_TCXO, 1, 0, 0),
612 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
613 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
614 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
615 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
616 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
617 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
618 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
619 { }
620 };
621
622 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
623 .name = "gcc_qupv3_wrap0_s0_clk_src",
624 .parent_data = gcc_parent_data_0,
625 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
626 .ops = &clk_rcg2_shared_ops,
627 };
628
629 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
630 .cmd_rcgr = 0x27154,
631 .mnd_width = 16,
632 .hid_width = 5,
633 .parent_map = gcc_parent_map_0,
634 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
635 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
636 };
637
638 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
639 .name = "gcc_qupv3_wrap0_s1_clk_src",
640 .parent_data = gcc_parent_data_0,
641 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
642 .ops = &clk_rcg2_shared_ops,
643 };
644
645 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
646 .cmd_rcgr = 0x27288,
647 .mnd_width = 16,
648 .hid_width = 5,
649 .parent_map = gcc_parent_map_0,
650 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
651 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
652 };
653
654 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
655 .name = "gcc_qupv3_wrap0_s2_clk_src",
656 .parent_data = gcc_parent_data_0,
657 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
658 .ops = &clk_rcg2_shared_ops,
659 };
660
661 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
662 .cmd_rcgr = 0x273bc,
663 .mnd_width = 16,
664 .hid_width = 5,
665 .parent_map = gcc_parent_map_0,
666 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
667 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
668 };
669
670 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
671 .name = "gcc_qupv3_wrap0_s3_clk_src",
672 .parent_data = gcc_parent_data_0,
673 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
674 .ops = &clk_rcg2_shared_ops,
675 };
676
677 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
678 .cmd_rcgr = 0x274f0,
679 .mnd_width = 16,
680 .hid_width = 5,
681 .parent_map = gcc_parent_map_0,
682 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
683 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
684 };
685
686 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
687 .name = "gcc_qupv3_wrap0_s4_clk_src",
688 .parent_data = gcc_parent_data_0,
689 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
690 .ops = &clk_rcg2_shared_ops,
691 };
692
693 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
694 .cmd_rcgr = 0x27624,
695 .mnd_width = 16,
696 .hid_width = 5,
697 .parent_map = gcc_parent_map_0,
698 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
699 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
700 };
701
702 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
703 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
704 { }
705 };
706
707 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
708 .name = "gcc_qupv3_wrap0_s5_clk_src",
709 .parent_data = gcc_parent_data_0,
710 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
711 .ops = &clk_rcg2_shared_ops,
712 };
713
714 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
715 .cmd_rcgr = 0x27758,
716 .mnd_width = 16,
717 .hid_width = 5,
718 .parent_map = gcc_parent_map_0,
719 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
720 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
721 };
722
723 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
724 .name = "gcc_qupv3_wrap0_s6_clk_src",
725 .parent_data = gcc_parent_data_0,
726 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
727 .ops = &clk_rcg2_shared_ops,
728 };
729
730 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
731 .cmd_rcgr = 0x2788c,
732 .mnd_width = 16,
733 .hid_width = 5,
734 .parent_map = gcc_parent_map_0,
735 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
736 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
737 };
738
739 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
740 .name = "gcc_qupv3_wrap0_s7_clk_src",
741 .parent_data = gcc_parent_data_0,
742 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
743 .ops = &clk_rcg2_shared_ops,
744 };
745
746 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
747 .cmd_rcgr = 0x279c0,
748 .mnd_width = 16,
749 .hid_width = 5,
750 .parent_map = gcc_parent_map_0,
751 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
752 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
753 };
754
755 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
756 .name = "gcc_qupv3_wrap1_s0_clk_src",
757 .parent_data = gcc_parent_data_0,
758 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
759 .ops = &clk_rcg2_shared_ops,
760 };
761
762 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
763 .cmd_rcgr = 0x28154,
764 .mnd_width = 16,
765 .hid_width = 5,
766 .parent_map = gcc_parent_map_0,
767 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
768 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
769 };
770
771 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
772 .name = "gcc_qupv3_wrap1_s1_clk_src",
773 .parent_data = gcc_parent_data_0,
774 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
775 .ops = &clk_rcg2_shared_ops,
776 };
777
778 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
779 .cmd_rcgr = 0x28288,
780 .mnd_width = 16,
781 .hid_width = 5,
782 .parent_map = gcc_parent_map_0,
783 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
784 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
785 };
786
787 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
788 .name = "gcc_qupv3_wrap1_s2_clk_src",
789 .parent_data = gcc_parent_data_0,
790 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
791 .ops = &clk_rcg2_shared_ops,
792 };
793
794 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
795 .cmd_rcgr = 0x283bc,
796 .mnd_width = 16,
797 .hid_width = 5,
798 .parent_map = gcc_parent_map_0,
799 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
800 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
801 };
802
803 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
804 .name = "gcc_qupv3_wrap1_s3_clk_src",
805 .parent_data = gcc_parent_data_0,
806 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
807 .ops = &clk_rcg2_shared_ops,
808 };
809
810 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
811 .cmd_rcgr = 0x284f0,
812 .mnd_width = 16,
813 .hid_width = 5,
814 .parent_map = gcc_parent_map_0,
815 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
816 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
817 };
818
819 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
820 .name = "gcc_qupv3_wrap1_s4_clk_src",
821 .parent_data = gcc_parent_data_0,
822 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
823 .ops = &clk_rcg2_shared_ops,
824 };
825
826 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
827 .cmd_rcgr = 0x28624,
828 .mnd_width = 16,
829 .hid_width = 5,
830 .parent_map = gcc_parent_map_0,
831 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
832 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
833 };
834
835 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
836 .name = "gcc_qupv3_wrap1_s5_clk_src",
837 .parent_data = gcc_parent_data_0,
838 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
839 .ops = &clk_rcg2_shared_ops,
840 };
841
842 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
843 .cmd_rcgr = 0x28758,
844 .mnd_width = 16,
845 .hid_width = 5,
846 .parent_map = gcc_parent_map_0,
847 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
848 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
849 };
850
851 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
852 .name = "gcc_qupv3_wrap1_s6_clk_src",
853 .parent_data = gcc_parent_data_0,
854 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
855 .ops = &clk_rcg2_shared_ops,
856 };
857
858 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
859 .cmd_rcgr = 0x2888c,
860 .mnd_width = 16,
861 .hid_width = 5,
862 .parent_map = gcc_parent_map_0,
863 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
864 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
865 };
866
867 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
868 .name = "gcc_qupv3_wrap1_s7_clk_src",
869 .parent_data = gcc_parent_data_0,
870 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
871 .ops = &clk_rcg2_shared_ops,
872 };
873
874 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
875 .cmd_rcgr = 0x289c0,
876 .mnd_width = 16,
877 .hid_width = 5,
878 .parent_map = gcc_parent_map_0,
879 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
880 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
881 };
882
883 static const struct freq_tbl ftbl_gcc_sdcc5_apps_clk_src[] = {
884 F(144000, P_BI_TCXO, 16, 3, 25),
885 F(400000, P_BI_TCXO, 12, 1, 4),
886 F(19200000, P_BI_TCXO, 1, 0, 0),
887 F(20000000, P_GCC_GPLL0_OUT_MAIN, 10, 1, 3),
888 F(25000000, P_GCC_GPLL0_OUT_MAIN, 12, 1, 2),
889 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
890 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
891 F(192000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
892 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
893 F(384000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
894 { }
895 };
896
897 static struct clk_rcg2 gcc_sdcc5_apps_clk_src = {
898 .cmd_rcgr = 0x3b034,
899 .mnd_width = 8,
900 .hid_width = 5,
901 .parent_map = gcc_parent_map_8,
902 .freq_tbl = ftbl_gcc_sdcc5_apps_clk_src,
903 .clkr.hw.init = &(const struct clk_init_data) {
904 .name = "gcc_sdcc5_apps_clk_src",
905 .parent_data = gcc_parent_data_8,
906 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
907 .ops = &clk_rcg2_floor_ops,
908 },
909 };
910
911 static const struct freq_tbl ftbl_gcc_sdcc5_ice_core_clk_src[] = {
912 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
913 { }
914 };
915
916 static struct clk_rcg2 gcc_sdcc5_ice_core_clk_src = {
917 .cmd_rcgr = 0x3b01c,
918 .mnd_width = 0,
919 .hid_width = 5,
920 .parent_map = gcc_parent_map_2,
921 .freq_tbl = ftbl_gcc_sdcc5_ice_core_clk_src,
922 .clkr.hw.init = &(const struct clk_init_data) {
923 .name = "gcc_sdcc5_ice_core_clk_src",
924 .parent_data = gcc_parent_data_2,
925 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
926 .ops = &clk_rcg2_floor_ops,
927 },
928 };
929
930 static struct clk_rcg2 gcc_sm_bus_xo_clk_src = {
931 .cmd_rcgr = 0x5b00c,
932 .mnd_width = 0,
933 .hid_width = 5,
934 .parent_map = gcc_parent_map_2,
935 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
936 .clkr.hw.init = &(const struct clk_init_data) {
937 .name = "gcc_sm_bus_xo_clk_src",
938 .parent_data = gcc_parent_data_2,
939 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
940 .ops = &clk_rcg2_shared_ops,
941 },
942 };
943
944 static const struct freq_tbl ftbl_gcc_tsc_clk_src[] = {
945 F(500000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
946 { }
947 };
948
949 static struct clk_rcg2 gcc_tsc_clk_src = {
950 .cmd_rcgr = 0x57010,
951 .mnd_width = 0,
952 .hid_width = 5,
953 .parent_map = gcc_parent_map_9,
954 .freq_tbl = ftbl_gcc_tsc_clk_src,
955 .clkr.hw.init = &(const struct clk_init_data) {
956 .name = "gcc_tsc_clk_src",
957 .parent_data = gcc_parent_data_9,
958 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
959 .ops = &clk_rcg2_shared_ops,
960 },
961 };
962
963 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
964 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
965 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
966 { }
967 };
968
969 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
970 .cmd_rcgr = 0x49028,
971 .mnd_width = 8,
972 .hid_width = 5,
973 .parent_map = gcc_parent_map_0,
974 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
975 .clkr.hw.init = &(const struct clk_init_data) {
976 .name = "gcc_usb30_prim_master_clk_src",
977 .parent_data = gcc_parent_data_0,
978 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
979 .ops = &clk_rcg2_shared_ops,
980 },
981 };
982
983 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
984 .cmd_rcgr = 0x49044,
985 .mnd_width = 0,
986 .hid_width = 5,
987 .parent_map = gcc_parent_map_0,
988 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
989 .clkr.hw.init = &(const struct clk_init_data) {
990 .name = "gcc_usb30_prim_mock_utmi_clk_src",
991 .parent_data = gcc_parent_data_0,
992 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
993 .ops = &clk_rcg2_shared_ops,
994 },
995 };
996
997 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
998 .cmd_rcgr = 0x49070,
999 .mnd_width = 0,
1000 .hid_width = 5,
1001 .parent_map = gcc_parent_map_3,
1002 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1003 .clkr.hw.init = &(const struct clk_init_data) {
1004 .name = "gcc_usb3_prim_phy_aux_clk_src",
1005 .parent_data = gcc_parent_data_3,
1006 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1007 .ops = &clk_rcg2_shared_ops,
1008 },
1009 };
1010
1011 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1012 .reg = 0x4905c,
1013 .shift = 0,
1014 .width = 4,
1015 .clkr.hw.init = &(const struct clk_init_data) {
1016 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1017 .parent_hws = (const struct clk_hw*[]) {
1018 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1019 },
1020 .num_parents = 1,
1021 .flags = CLK_SET_RATE_PARENT,
1022 .ops = &clk_regmap_div_ro_ops,
1023 },
1024 };
1025
1026 static struct clk_branch gcc_aggre_noc_ecpri_dma_clk = {
1027 .halt_reg = 0x92008,
1028 .halt_check = BRANCH_HALT_VOTED,
1029 .hwcg_reg = 0x92008,
1030 .hwcg_bit = 1,
1031 .clkr = {
1032 .enable_reg = 0x92008,
1033 .enable_mask = BIT(0),
1034 .hw.init = &(const struct clk_init_data) {
1035 .name = "gcc_aggre_noc_ecpri_dma_clk",
1036 .parent_hws = (const struct clk_hw*[]) {
1037 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw,
1038 },
1039 .num_parents = 1,
1040 .flags = CLK_SET_RATE_PARENT,
1041 .ops = &clk_branch2_ops,
1042 },
1043 },
1044 };
1045
1046 static struct clk_branch gcc_aggre_noc_ecpri_gsi_clk = {
1047 .halt_reg = 0x9201c,
1048 .halt_check = BRANCH_HALT_VOTED,
1049 .hwcg_reg = 0x9201c,
1050 .hwcg_bit = 1,
1051 .clkr = {
1052 .enable_reg = 0x9201c,
1053 .enable_mask = BIT(0),
1054 .hw.init = &(const struct clk_init_data) {
1055 .name = "gcc_aggre_noc_ecpri_gsi_clk",
1056 .parent_hws = (const struct clk_hw*[]) {
1057 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
1058 },
1059 .num_parents = 1,
1060 .flags = CLK_SET_RATE_PARENT,
1061 .ops = &clk_branch2_ops,
1062 },
1063 },
1064 };
1065
1066 static struct clk_branch gcc_boot_rom_ahb_clk = {
1067 .halt_reg = 0x48004,
1068 .halt_check = BRANCH_HALT_VOTED,
1069 .hwcg_reg = 0x48004,
1070 .hwcg_bit = 1,
1071 .clkr = {
1072 .enable_reg = 0x62000,
1073 .enable_mask = BIT(10),
1074 .hw.init = &(const struct clk_init_data) {
1075 .name = "gcc_boot_rom_ahb_clk",
1076 .ops = &clk_branch2_ops,
1077 },
1078 },
1079 };
1080
1081 static struct clk_branch gcc_cfg_noc_ecpri_cc_ahb_clk = {
1082 .halt_reg = 0x3e004,
1083 .halt_check = BRANCH_HALT_VOTED,
1084 .hwcg_reg = 0x3e004,
1085 .hwcg_bit = 1,
1086 .clkr = {
1087 .enable_reg = 0x3e004,
1088 .enable_mask = BIT(0),
1089 .hw.init = &(const struct clk_init_data) {
1090 .name = "gcc_cfg_noc_ecpri_cc_ahb_clk",
1091 .ops = &clk_branch2_ops,
1092 },
1093 },
1094 };
1095
1096 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1097 .halt_reg = 0x8401c,
1098 .halt_check = BRANCH_HALT_VOTED,
1099 .hwcg_reg = 0x8401c,
1100 .hwcg_bit = 1,
1101 .clkr = {
1102 .enable_reg = 0x8401c,
1103 .enable_mask = BIT(0),
1104 .hw.init = &(const struct clk_init_data) {
1105 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1106 .parent_hws = (const struct clk_hw*[]) {
1107 &gcc_usb30_prim_master_clk_src.clkr.hw,
1108 },
1109 .num_parents = 1,
1110 .flags = CLK_SET_RATE_PARENT,
1111 .ops = &clk_branch2_ops,
1112 },
1113 },
1114 };
1115
1116 static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
1117 .halt_reg = 0x54030,
1118 .halt_check = BRANCH_HALT_VOTED,
1119 .hwcg_reg = 0x54030,
1120 .hwcg_bit = 1,
1121 .clkr = {
1122 .enable_reg = 0x54030,
1123 .enable_mask = BIT(0),
1124 .hw.init = &(const struct clk_init_data) {
1125 .name = "gcc_ddrss_ecpri_dma_clk",
1126 .parent_hws = (const struct clk_hw*[]) {
1127 &gcc_aggre_noc_ecpri_dma_clk_src.clkr.hw,
1128 },
1129 .num_parents = 1,
1130 .flags = CLK_SET_RATE_PARENT,
1131 .ops = &clk_branch2_aon_ops,
1132 },
1133 },
1134 };
1135
1136 static struct clk_branch gcc_ddrss_ecpri_gsi_clk = {
1137 .halt_reg = 0x54298,
1138 .halt_check = BRANCH_HALT_VOTED,
1139 .hwcg_reg = 0x54298,
1140 .hwcg_bit = 1,
1141 .clkr = {
1142 .enable_reg = 0x54298,
1143 .enable_mask = BIT(0),
1144 .hw.init = &(const struct clk_init_data) {
1145 .name = "gcc_ddrss_ecpri_gsi_clk",
1146 .parent_hws = (const struct clk_hw*[]) {
1147 &gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
1148 },
1149 .num_parents = 1,
1150 .flags = CLK_SET_RATE_PARENT,
1151 .ops = &clk_branch2_aon_ops,
1152 },
1153 },
1154 };
1155
1156 static struct clk_branch gcc_ecpri_ahb_clk = {
1157 .halt_reg = 0x3a008,
1158 .halt_check = BRANCH_HALT_VOTED,
1159 .hwcg_reg = 0x3a008,
1160 .hwcg_bit = 1,
1161 .clkr = {
1162 .enable_reg = 0x3a008,
1163 .enable_mask = BIT(0),
1164 .hw.init = &(const struct clk_init_data) {
1165 .name = "gcc_ecpri_ahb_clk",
1166 .ops = &clk_branch2_ops,
1167 },
1168 },
1169 };
1170
1171 static struct clk_branch gcc_ecpri_cc_gpll0_clk_src = {
1172 .halt_check = BRANCH_HALT_DELAY,
1173 .clkr = {
1174 .enable_reg = 0x62010,
1175 .enable_mask = BIT(0),
1176 .hw.init = &(const struct clk_init_data) {
1177 .name = "gcc_ecpri_cc_gpll0_clk_src",
1178 .parent_hws = (const struct clk_hw*[]) {
1179 &gcc_gpll0.clkr.hw,
1180 },
1181 .num_parents = 1,
1182 .flags = CLK_SET_RATE_PARENT,
1183 .ops = &clk_branch2_ops,
1184 },
1185 },
1186 };
1187
1188 static struct clk_branch gcc_ecpri_cc_gpll1_even_clk_src = {
1189 .halt_check = BRANCH_HALT_DELAY,
1190 .clkr = {
1191 .enable_reg = 0x62010,
1192 .enable_mask = BIT(1),
1193 .hw.init = &(const struct clk_init_data) {
1194 .name = "gcc_ecpri_cc_gpll1_even_clk_src",
1195 .parent_hws = (const struct clk_hw*[]) {
1196 &gcc_gpll1_out_even.clkr.hw,
1197 },
1198 .num_parents = 1,
1199 .flags = CLK_SET_RATE_PARENT,
1200 .ops = &clk_branch2_ops,
1201 },
1202 },
1203 };
1204
1205 static struct clk_branch gcc_ecpri_cc_gpll2_even_clk_src = {
1206 .halt_check = BRANCH_HALT_DELAY,
1207 .clkr = {
1208 .enable_reg = 0x62010,
1209 .enable_mask = BIT(2),
1210 .hw.init = &(const struct clk_init_data) {
1211 .name = "gcc_ecpri_cc_gpll2_even_clk_src",
1212 .parent_hws = (const struct clk_hw*[]) {
1213 &gcc_gpll2_out_even.clkr.hw,
1214 },
1215 .num_parents = 1,
1216 .flags = CLK_SET_RATE_PARENT,
1217 .ops = &clk_branch2_ops,
1218 },
1219 },
1220 };
1221
1222 static struct clk_branch gcc_ecpri_cc_gpll3_clk_src = {
1223 .halt_check = BRANCH_HALT_DELAY,
1224 .clkr = {
1225 .enable_reg = 0x62010,
1226 .enable_mask = BIT(3),
1227 .hw.init = &(const struct clk_init_data) {
1228 .name = "gcc_ecpri_cc_gpll3_clk_src",
1229 .parent_hws = (const struct clk_hw*[]) {
1230 &gcc_gpll3.clkr.hw,
1231 },
1232 .num_parents = 1,
1233 .flags = CLK_SET_RATE_PARENT,
1234 .ops = &clk_branch2_ops,
1235 },
1236 },
1237 };
1238
1239 static struct clk_branch gcc_ecpri_cc_gpll4_clk_src = {
1240 .halt_check = BRANCH_HALT_DELAY,
1241 .clkr = {
1242 .enable_reg = 0x62010,
1243 .enable_mask = BIT(4),
1244 .hw.init = &(const struct clk_init_data) {
1245 .name = "gcc_ecpri_cc_gpll4_clk_src",
1246 .parent_hws = (const struct clk_hw*[]) {
1247 &gcc_gpll4.clkr.hw,
1248 },
1249 .num_parents = 1,
1250 .flags = CLK_SET_RATE_PARENT,
1251 .ops = &clk_branch2_ops,
1252 },
1253 },
1254 };
1255
1256 static struct clk_branch gcc_ecpri_cc_gpll5_even_clk_src = {
1257 .halt_check = BRANCH_HALT_DELAY,
1258 .clkr = {
1259 .enable_reg = 0x62010,
1260 .enable_mask = BIT(5),
1261 .hw.init = &(const struct clk_init_data) {
1262 .name = "gcc_ecpri_cc_gpll5_even_clk_src",
1263 .parent_hws = (const struct clk_hw*[]) {
1264 &gcc_gpll5_out_even.clkr.hw,
1265 },
1266 .num_parents = 1,
1267 .flags = CLK_SET_RATE_PARENT,
1268 .ops = &clk_branch2_ops,
1269 },
1270 },
1271 };
1272
1273 static struct clk_branch gcc_ecpri_xo_clk = {
1274 .halt_reg = 0x3a004,
1275 .halt_check = BRANCH_HALT,
1276 .clkr = {
1277 .enable_reg = 0x3a004,
1278 .enable_mask = BIT(0),
1279 .hw.init = &(const struct clk_init_data) {
1280 .name = "gcc_ecpri_xo_clk",
1281 .ops = &clk_branch2_ops,
1282 },
1283 },
1284 };
1285
1286 static struct clk_branch gcc_eth_100g_c2c_hm_apb_clk = {
1287 .halt_reg = 0x39010,
1288 .halt_check = BRANCH_HALT,
1289 .clkr = {
1290 .enable_reg = 0x39010,
1291 .enable_mask = BIT(0),
1292 .hw.init = &(const struct clk_init_data) {
1293 .name = "gcc_eth_100g_c2c_hm_apb_clk",
1294 .ops = &clk_branch2_ops,
1295 },
1296 },
1297 };
1298
1299 static struct clk_branch gcc_eth_100g_fh_hm_apb_0_clk = {
1300 .halt_reg = 0x39004,
1301 .halt_check = BRANCH_HALT,
1302 .clkr = {
1303 .enable_reg = 0x39004,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(const struct clk_init_data) {
1306 .name = "gcc_eth_100g_fh_hm_apb_0_clk",
1307 .ops = &clk_branch2_ops,
1308 },
1309 },
1310 };
1311
1312 static struct clk_branch gcc_eth_100g_fh_hm_apb_1_clk = {
1313 .halt_reg = 0x39008,
1314 .halt_check = BRANCH_HALT,
1315 .clkr = {
1316 .enable_reg = 0x39008,
1317 .enable_mask = BIT(0),
1318 .hw.init = &(const struct clk_init_data) {
1319 .name = "gcc_eth_100g_fh_hm_apb_1_clk",
1320 .ops = &clk_branch2_ops,
1321 },
1322 },
1323 };
1324
1325 static struct clk_branch gcc_eth_100g_fh_hm_apb_2_clk = {
1326 .halt_reg = 0x3900c,
1327 .halt_check = BRANCH_HALT,
1328 .clkr = {
1329 .enable_reg = 0x3900c,
1330 .enable_mask = BIT(0),
1331 .hw.init = &(const struct clk_init_data) {
1332 .name = "gcc_eth_100g_fh_hm_apb_2_clk",
1333 .ops = &clk_branch2_ops,
1334 },
1335 },
1336 };
1337
1338 static struct clk_branch gcc_eth_dbg_c2c_hm_apb_clk = {
1339 .halt_reg = 0x39014,
1340 .halt_check = BRANCH_HALT,
1341 .clkr = {
1342 .enable_reg = 0x39014,
1343 .enable_mask = BIT(0),
1344 .hw.init = &(const struct clk_init_data) {
1345 .name = "gcc_eth_dbg_c2c_hm_apb_clk",
1346 .ops = &clk_branch2_ops,
1347 },
1348 },
1349 };
1350
1351 static struct clk_branch gcc_eth_dbg_snoc_axi_clk = {
1352 .halt_reg = 0x3901c,
1353 .halt_check = BRANCH_HALT_VOTED,
1354 .hwcg_reg = 0x3901c,
1355 .hwcg_bit = 1,
1356 .clkr = {
1357 .enable_reg = 0x3901c,
1358 .enable_mask = BIT(0),
1359 .hw.init = &(const struct clk_init_data) {
1360 .name = "gcc_eth_dbg_snoc_axi_clk",
1361 .ops = &clk_branch2_ops,
1362 },
1363 },
1364 };
1365
1366 static struct clk_branch gcc_gemnoc_pcie_qx_clk = {
1367 .halt_reg = 0x5402c,
1368 .halt_check = BRANCH_HALT_VOTED,
1369 .hwcg_reg = 0x5402c,
1370 .hwcg_bit = 1,
1371 .clkr = {
1372 .enable_reg = 0x62008,
1373 .enable_mask = BIT(0),
1374 .hw.init = &(const struct clk_init_data) {
1375 .name = "gcc_gemnoc_pcie_qx_clk",
1376 .ops = &clk_branch2_aon_ops,
1377 },
1378 },
1379 };
1380
1381 static struct clk_branch gcc_gp1_clk = {
1382 .halt_reg = 0x74000,
1383 .halt_check = BRANCH_HALT,
1384 .clkr = {
1385 .enable_reg = 0x74000,
1386 .enable_mask = BIT(0),
1387 .hw.init = &(const struct clk_init_data) {
1388 .name = "gcc_gp1_clk",
1389 .parent_hws = (const struct clk_hw*[]) {
1390 &gcc_gp1_clk_src.clkr.hw,
1391 },
1392 .num_parents = 1,
1393 .flags = CLK_SET_RATE_PARENT,
1394 .ops = &clk_branch2_ops,
1395 },
1396 },
1397 };
1398
1399 static struct clk_branch gcc_gp2_clk = {
1400 .halt_reg = 0x75000,
1401 .halt_check = BRANCH_HALT,
1402 .clkr = {
1403 .enable_reg = 0x75000,
1404 .enable_mask = BIT(0),
1405 .hw.init = &(const struct clk_init_data) {
1406 .name = "gcc_gp2_clk",
1407 .parent_hws = (const struct clk_hw*[]) {
1408 &gcc_gp2_clk_src.clkr.hw,
1409 },
1410 .num_parents = 1,
1411 .flags = CLK_SET_RATE_PARENT,
1412 .ops = &clk_branch2_ops,
1413 },
1414 },
1415 };
1416
1417 static struct clk_branch gcc_gp3_clk = {
1418 .halt_reg = 0x76000,
1419 .halt_check = BRANCH_HALT,
1420 .clkr = {
1421 .enable_reg = 0x76000,
1422 .enable_mask = BIT(0),
1423 .hw.init = &(const struct clk_init_data) {
1424 .name = "gcc_gp3_clk",
1425 .parent_hws = (const struct clk_hw*[]) {
1426 &gcc_gp3_clk_src.clkr.hw,
1427 },
1428 .num_parents = 1,
1429 .flags = CLK_SET_RATE_PARENT,
1430 .ops = &clk_branch2_ops,
1431 },
1432 },
1433 };
1434
1435 static struct clk_branch gcc_pcie_0_aux_clk = {
1436 .halt_reg = 0x9d030,
1437 .halt_check = BRANCH_HALT_VOTED,
1438 .hwcg_reg = 0x9d030,
1439 .hwcg_bit = 1,
1440 .clkr = {
1441 .enable_reg = 0x62000,
1442 .enable_mask = BIT(29),
1443 .hw.init = &(const struct clk_init_data) {
1444 .name = "gcc_pcie_0_aux_clk",
1445 .parent_hws = (const struct clk_hw*[]) {
1446 &gcc_pcie_0_aux_clk_src.clkr.hw,
1447 },
1448 .num_parents = 1,
1449 .flags = CLK_SET_RATE_PARENT,
1450 .ops = &clk_branch2_ops,
1451 },
1452 },
1453 };
1454
1455 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1456 .halt_reg = 0x9d02c,
1457 .halt_check = BRANCH_HALT_VOTED,
1458 .hwcg_reg = 0x9d02c,
1459 .hwcg_bit = 1,
1460 .clkr = {
1461 .enable_reg = 0x62000,
1462 .enable_mask = BIT(28),
1463 .hw.init = &(const struct clk_init_data) {
1464 .name = "gcc_pcie_0_cfg_ahb_clk",
1465 .ops = &clk_branch2_ops,
1466 },
1467 },
1468 };
1469
1470 static struct clk_branch gcc_pcie_0_clkref_en = {
1471 .halt_reg = 0x9c004,
1472 .halt_check = BRANCH_HALT,
1473 .clkr = {
1474 .enable_reg = 0x9c004,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(const struct clk_init_data) {
1477 .name = "gcc_pcie_0_clkref_en",
1478 .ops = &clk_branch2_ops,
1479 },
1480 },
1481 };
1482
1483 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1484 .halt_reg = 0x9d024,
1485 .halt_check = BRANCH_HALT_SKIP,
1486 .hwcg_reg = 0x9d024,
1487 .hwcg_bit = 1,
1488 .clkr = {
1489 .enable_reg = 0x62000,
1490 .enable_mask = BIT(27),
1491 .hw.init = &(const struct clk_init_data) {
1492 .name = "gcc_pcie_0_mstr_axi_clk",
1493 .ops = &clk_branch2_ops,
1494 },
1495 },
1496 };
1497
1498 static struct clk_branch gcc_pcie_0_phy_aux_clk = {
1499 .halt_reg = 0x9d038,
1500 .halt_check = BRANCH_HALT_VOTED,
1501 .hwcg_reg = 0x9d038,
1502 .hwcg_bit = 1,
1503 .clkr = {
1504 .enable_reg = 0x62000,
1505 .enable_mask = BIT(24),
1506 .hw.init = &(const struct clk_init_data) {
1507 .name = "gcc_pcie_0_phy_aux_clk",
1508 .parent_hws = (const struct clk_hw*[]) {
1509 &gcc_pcie_0_phy_aux_clk_src.clkr.hw,
1510 },
1511 .num_parents = 1,
1512 .flags = CLK_SET_RATE_PARENT,
1513 .ops = &clk_branch2_ops,
1514 },
1515 },
1516 };
1517
1518 static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1519 .halt_reg = 0x9d048,
1520 .halt_check = BRANCH_HALT_VOTED,
1521 .hwcg_reg = 0x9d048,
1522 .hwcg_bit = 1,
1523 .clkr = {
1524 .enable_reg = 0x62000,
1525 .enable_mask = BIT(23),
1526 .hw.init = &(const struct clk_init_data) {
1527 .name = "gcc_pcie_0_phy_rchng_clk",
1528 .parent_hws = (const struct clk_hw*[]) {
1529 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1530 },
1531 .num_parents = 1,
1532 .flags = CLK_SET_RATE_PARENT,
1533 .ops = &clk_branch2_ops,
1534 },
1535 },
1536 };
1537
1538 static struct clk_branch gcc_pcie_0_pipe_clk = {
1539 .halt_reg = 0x9d040,
1540 .halt_check = BRANCH_HALT_VOTED,
1541 .hwcg_reg = 0x9d040,
1542 .hwcg_bit = 1,
1543 .clkr = {
1544 .enable_reg = 0x62000,
1545 .enable_mask = BIT(30),
1546 .hw.init = &(const struct clk_init_data) {
1547 .name = "gcc_pcie_0_pipe_clk",
1548 .parent_hws = (const struct clk_hw*[]) {
1549 &gcc_pcie_0_pipe_clk_src.clkr.hw,
1550 },
1551 .num_parents = 1,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1554 },
1555 },
1556 };
1557
1558 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1559 .halt_reg = 0x9d01c,
1560 .halt_check = BRANCH_HALT_VOTED,
1561 .hwcg_reg = 0x9d01c,
1562 .hwcg_bit = 1,
1563 .clkr = {
1564 .enable_reg = 0x62000,
1565 .enable_mask = BIT(26),
1566 .hw.init = &(const struct clk_init_data) {
1567 .name = "gcc_pcie_0_slv_axi_clk",
1568 .ops = &clk_branch2_ops,
1569 },
1570 },
1571 };
1572
1573 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1574 .halt_reg = 0x9d018,
1575 .halt_check = BRANCH_HALT_VOTED,
1576 .hwcg_reg = 0x9d018,
1577 .hwcg_bit = 1,
1578 .clkr = {
1579 .enable_reg = 0x62000,
1580 .enable_mask = BIT(25),
1581 .hw.init = &(const struct clk_init_data) {
1582 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1583 .ops = &clk_branch2_ops,
1584 },
1585 },
1586 };
1587
1588 static struct clk_branch gcc_pdm2_clk = {
1589 .halt_reg = 0x4300c,
1590 .halt_check = BRANCH_HALT,
1591 .clkr = {
1592 .enable_reg = 0x4300c,
1593 .enable_mask = BIT(0),
1594 .hw.init = &(const struct clk_init_data) {
1595 .name = "gcc_pdm2_clk",
1596 .parent_hws = (const struct clk_hw*[]) {
1597 &gcc_pdm2_clk_src.clkr.hw,
1598 },
1599 .num_parents = 1,
1600 .flags = CLK_SET_RATE_PARENT,
1601 .ops = &clk_branch2_ops,
1602 },
1603 },
1604 };
1605
1606 static struct clk_branch gcc_pdm_ahb_clk = {
1607 .halt_reg = 0x43004,
1608 .halt_check = BRANCH_HALT_VOTED,
1609 .hwcg_reg = 0x43004,
1610 .hwcg_bit = 1,
1611 .clkr = {
1612 .enable_reg = 0x43004,
1613 .enable_mask = BIT(0),
1614 .hw.init = &(const struct clk_init_data) {
1615 .name = "gcc_pdm_ahb_clk",
1616 .ops = &clk_branch2_ops,
1617 },
1618 },
1619 };
1620
1621 static struct clk_branch gcc_pdm_xo4_clk = {
1622 .halt_reg = 0x43008,
1623 .halt_check = BRANCH_HALT,
1624 .clkr = {
1625 .enable_reg = 0x43008,
1626 .enable_mask = BIT(0),
1627 .hw.init = &(const struct clk_init_data) {
1628 .name = "gcc_pdm_xo4_clk",
1629 .ops = &clk_branch2_ops,
1630 },
1631 },
1632 };
1633
1634 static struct clk_branch gcc_qmip_anoc_pcie_clk = {
1635 .halt_reg = 0x84044,
1636 .halt_check = BRANCH_HALT_VOTED,
1637 .hwcg_reg = 0x84044,
1638 .hwcg_bit = 1,
1639 .clkr = {
1640 .enable_reg = 0x84044,
1641 .enable_mask = BIT(0),
1642 .hw.init = &(const struct clk_init_data) {
1643 .name = "gcc_qmip_anoc_pcie_clk",
1644 .ops = &clk_branch2_ops,
1645 },
1646 },
1647 };
1648
1649 static struct clk_branch gcc_qmip_ecpri_dma0_clk = {
1650 .halt_reg = 0x84038,
1651 .halt_check = BRANCH_HALT_VOTED,
1652 .hwcg_reg = 0x84038,
1653 .hwcg_bit = 1,
1654 .clkr = {
1655 .enable_reg = 0x84038,
1656 .enable_mask = BIT(0),
1657 .hw.init = &(const struct clk_init_data) {
1658 .name = "gcc_qmip_ecpri_dma0_clk",
1659 .ops = &clk_branch2_ops,
1660 },
1661 },
1662 };
1663
1664 static struct clk_branch gcc_qmip_ecpri_dma1_clk = {
1665 .halt_reg = 0x8403c,
1666 .halt_check = BRANCH_HALT_VOTED,
1667 .hwcg_reg = 0x8403c,
1668 .hwcg_bit = 1,
1669 .clkr = {
1670 .enable_reg = 0x8403c,
1671 .enable_mask = BIT(0),
1672 .hw.init = &(const struct clk_init_data) {
1673 .name = "gcc_qmip_ecpri_dma1_clk",
1674 .ops = &clk_branch2_ops,
1675 },
1676 },
1677 };
1678
1679 static struct clk_branch gcc_qmip_ecpri_gsi_clk = {
1680 .halt_reg = 0x84040,
1681 .halt_check = BRANCH_HALT_VOTED,
1682 .hwcg_reg = 0x84040,
1683 .hwcg_bit = 1,
1684 .clkr = {
1685 .enable_reg = 0x84040,
1686 .enable_mask = BIT(0),
1687 .hw.init = &(const struct clk_init_data) {
1688 .name = "gcc_qmip_ecpri_gsi_clk",
1689 .ops = &clk_branch2_ops,
1690 },
1691 },
1692 };
1693
1694 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1695 .halt_reg = 0x27018,
1696 .halt_check = BRANCH_HALT_VOTED,
1697 .clkr = {
1698 .enable_reg = 0x62008,
1699 .enable_mask = BIT(9),
1700 .hw.init = &(const struct clk_init_data) {
1701 .name = "gcc_qupv3_wrap0_core_2x_clk",
1702 .ops = &clk_branch2_ops,
1703 },
1704 },
1705 };
1706
1707 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1708 .halt_reg = 0x2700c,
1709 .halt_check = BRANCH_HALT_VOTED,
1710 .clkr = {
1711 .enable_reg = 0x62008,
1712 .enable_mask = BIT(8),
1713 .hw.init = &(const struct clk_init_data) {
1714 .name = "gcc_qupv3_wrap0_core_clk",
1715 .ops = &clk_branch2_ops,
1716 },
1717 },
1718 };
1719
1720 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1721 .halt_reg = 0x2714c,
1722 .halt_check = BRANCH_HALT_VOTED,
1723 .clkr = {
1724 .enable_reg = 0x62008,
1725 .enable_mask = BIT(10),
1726 .hw.init = &(const struct clk_init_data) {
1727 .name = "gcc_qupv3_wrap0_s0_clk",
1728 .parent_hws = (const struct clk_hw*[]) {
1729 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1730 },
1731 .num_parents = 1,
1732 .flags = CLK_SET_RATE_PARENT,
1733 .ops = &clk_branch2_ops,
1734 },
1735 },
1736 };
1737
1738 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1739 .halt_reg = 0x27280,
1740 .halt_check = BRANCH_HALT_VOTED,
1741 .clkr = {
1742 .enable_reg = 0x62008,
1743 .enable_mask = BIT(11),
1744 .hw.init = &(const struct clk_init_data) {
1745 .name = "gcc_qupv3_wrap0_s1_clk",
1746 .parent_hws = (const struct clk_hw*[]) {
1747 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1748 },
1749 .num_parents = 1,
1750 .flags = CLK_SET_RATE_PARENT,
1751 .ops = &clk_branch2_ops,
1752 },
1753 },
1754 };
1755
1756 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1757 .halt_reg = 0x273b4,
1758 .halt_check = BRANCH_HALT_VOTED,
1759 .clkr = {
1760 .enable_reg = 0x62008,
1761 .enable_mask = BIT(12),
1762 .hw.init = &(const struct clk_init_data) {
1763 .name = "gcc_qupv3_wrap0_s2_clk",
1764 .parent_hws = (const struct clk_hw*[]) {
1765 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1766 },
1767 .num_parents = 1,
1768 .flags = CLK_SET_RATE_PARENT,
1769 .ops = &clk_branch2_ops,
1770 },
1771 },
1772 };
1773
1774 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1775 .halt_reg = 0x274e8,
1776 .halt_check = BRANCH_HALT_VOTED,
1777 .clkr = {
1778 .enable_reg = 0x62008,
1779 .enable_mask = BIT(13),
1780 .hw.init = &(const struct clk_init_data) {
1781 .name = "gcc_qupv3_wrap0_s3_clk",
1782 .parent_hws = (const struct clk_hw*[]) {
1783 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1784 },
1785 .num_parents = 1,
1786 .flags = CLK_SET_RATE_PARENT,
1787 .ops = &clk_branch2_ops,
1788 },
1789 },
1790 };
1791
1792 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1793 .halt_reg = 0x2761c,
1794 .halt_check = BRANCH_HALT_VOTED,
1795 .clkr = {
1796 .enable_reg = 0x62008,
1797 .enable_mask = BIT(14),
1798 .hw.init = &(const struct clk_init_data) {
1799 .name = "gcc_qupv3_wrap0_s4_clk",
1800 .parent_hws = (const struct clk_hw*[]) {
1801 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1802 },
1803 .num_parents = 1,
1804 .flags = CLK_SET_RATE_PARENT,
1805 .ops = &clk_branch2_ops,
1806 },
1807 },
1808 };
1809
1810 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1811 .halt_reg = 0x27750,
1812 .halt_check = BRANCH_HALT_VOTED,
1813 .clkr = {
1814 .enable_reg = 0x62008,
1815 .enable_mask = BIT(15),
1816 .hw.init = &(const struct clk_init_data) {
1817 .name = "gcc_qupv3_wrap0_s5_clk",
1818 .parent_hws = (const struct clk_hw*[]) {
1819 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1820 },
1821 .num_parents = 1,
1822 .flags = CLK_SET_RATE_PARENT,
1823 .ops = &clk_branch2_ops,
1824 },
1825 },
1826 };
1827
1828 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
1829 .halt_reg = 0x27884,
1830 .halt_check = BRANCH_HALT_VOTED,
1831 .clkr = {
1832 .enable_reg = 0x62008,
1833 .enable_mask = BIT(16),
1834 .hw.init = &(const struct clk_init_data) {
1835 .name = "gcc_qupv3_wrap0_s6_clk",
1836 .parent_hws = (const struct clk_hw*[]) {
1837 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
1838 },
1839 .num_parents = 1,
1840 .flags = CLK_SET_RATE_PARENT,
1841 .ops = &clk_branch2_ops,
1842 },
1843 },
1844 };
1845
1846 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
1847 .halt_reg = 0x279b8,
1848 .halt_check = BRANCH_HALT_VOTED,
1849 .clkr = {
1850 .enable_reg = 0x62008,
1851 .enable_mask = BIT(17),
1852 .hw.init = &(const struct clk_init_data) {
1853 .name = "gcc_qupv3_wrap0_s7_clk",
1854 .parent_hws = (const struct clk_hw*[]) {
1855 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
1856 },
1857 .num_parents = 1,
1858 .flags = CLK_SET_RATE_PARENT,
1859 .ops = &clk_branch2_ops,
1860 },
1861 },
1862 };
1863
1864 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1865 .halt_reg = 0x28018,
1866 .halt_check = BRANCH_HALT_VOTED,
1867 .clkr = {
1868 .enable_reg = 0x62008,
1869 .enable_mask = BIT(18),
1870 .hw.init = &(const struct clk_init_data) {
1871 .name = "gcc_qupv3_wrap1_core_2x_clk",
1872 .ops = &clk_branch2_ops,
1873 },
1874 },
1875 };
1876
1877 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1878 .halt_reg = 0x2800c,
1879 .halt_check = BRANCH_HALT_VOTED,
1880 .clkr = {
1881 .enable_reg = 0x62008,
1882 .enable_mask = BIT(19),
1883 .hw.init = &(const struct clk_init_data) {
1884 .name = "gcc_qupv3_wrap1_core_clk",
1885 .ops = &clk_branch2_ops,
1886 },
1887 },
1888 };
1889
1890 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1891 .halt_reg = 0x2814c,
1892 .halt_check = BRANCH_HALT_VOTED,
1893 .clkr = {
1894 .enable_reg = 0x62008,
1895 .enable_mask = BIT(22),
1896 .hw.init = &(const struct clk_init_data) {
1897 .name = "gcc_qupv3_wrap1_s0_clk",
1898 .parent_hws = (const struct clk_hw*[]) {
1899 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1900 },
1901 .num_parents = 1,
1902 .flags = CLK_SET_RATE_PARENT,
1903 .ops = &clk_branch2_ops,
1904 },
1905 },
1906 };
1907
1908 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1909 .halt_reg = 0x28280,
1910 .halt_check = BRANCH_HALT_VOTED,
1911 .clkr = {
1912 .enable_reg = 0x62008,
1913 .enable_mask = BIT(23),
1914 .hw.init = &(const struct clk_init_data) {
1915 .name = "gcc_qupv3_wrap1_s1_clk",
1916 .parent_hws = (const struct clk_hw*[]) {
1917 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1918 },
1919 .num_parents = 1,
1920 .flags = CLK_SET_RATE_PARENT,
1921 .ops = &clk_branch2_ops,
1922 },
1923 },
1924 };
1925
1926 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1927 .halt_reg = 0x283b4,
1928 .halt_check = BRANCH_HALT_VOTED,
1929 .clkr = {
1930 .enable_reg = 0x62008,
1931 .enable_mask = BIT(24),
1932 .hw.init = &(const struct clk_init_data) {
1933 .name = "gcc_qupv3_wrap1_s2_clk",
1934 .parent_hws = (const struct clk_hw*[]) {
1935 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1936 },
1937 .num_parents = 1,
1938 .flags = CLK_SET_RATE_PARENT,
1939 .ops = &clk_branch2_ops,
1940 },
1941 },
1942 };
1943
1944 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1945 .halt_reg = 0x284e8,
1946 .halt_check = BRANCH_HALT_VOTED,
1947 .clkr = {
1948 .enable_reg = 0x62008,
1949 .enable_mask = BIT(25),
1950 .hw.init = &(const struct clk_init_data) {
1951 .name = "gcc_qupv3_wrap1_s3_clk",
1952 .parent_hws = (const struct clk_hw*[]) {
1953 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1954 },
1955 .num_parents = 1,
1956 .flags = CLK_SET_RATE_PARENT,
1957 .ops = &clk_branch2_ops,
1958 },
1959 },
1960 };
1961
1962 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1963 .halt_reg = 0x2861c,
1964 .halt_check = BRANCH_HALT_VOTED,
1965 .clkr = {
1966 .enable_reg = 0x62008,
1967 .enable_mask = BIT(26),
1968 .hw.init = &(const struct clk_init_data) {
1969 .name = "gcc_qupv3_wrap1_s4_clk",
1970 .parent_hws = (const struct clk_hw*[]) {
1971 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1972 },
1973 .num_parents = 1,
1974 .flags = CLK_SET_RATE_PARENT,
1975 .ops = &clk_branch2_ops,
1976 },
1977 },
1978 };
1979
1980 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1981 .halt_reg = 0x28750,
1982 .halt_check = BRANCH_HALT_VOTED,
1983 .clkr = {
1984 .enable_reg = 0x62008,
1985 .enable_mask = BIT(27),
1986 .hw.init = &(const struct clk_init_data) {
1987 .name = "gcc_qupv3_wrap1_s5_clk",
1988 .parent_hws = (const struct clk_hw*[]) {
1989 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1990 },
1991 .num_parents = 1,
1992 .flags = CLK_SET_RATE_PARENT,
1993 .ops = &clk_branch2_ops,
1994 },
1995 },
1996 };
1997
1998 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
1999 .halt_reg = 0x28884,
2000 .halt_check = BRANCH_HALT_VOTED,
2001 .clkr = {
2002 .enable_reg = 0x62008,
2003 .enable_mask = BIT(28),
2004 .hw.init = &(const struct clk_init_data) {
2005 .name = "gcc_qupv3_wrap1_s6_clk",
2006 .parent_hws = (const struct clk_hw*[]) {
2007 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2008 },
2009 .num_parents = 1,
2010 .flags = CLK_SET_RATE_PARENT,
2011 .ops = &clk_branch2_ops,
2012 },
2013 },
2014 };
2015
2016 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2017 .halt_reg = 0x289b8,
2018 .halt_check = BRANCH_HALT_VOTED,
2019 .clkr = {
2020 .enable_reg = 0x62008,
2021 .enable_mask = BIT(29),
2022 .hw.init = &(const struct clk_init_data) {
2023 .name = "gcc_qupv3_wrap1_s7_clk",
2024 .parent_hws = (const struct clk_hw*[]) {
2025 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2026 },
2027 .num_parents = 1,
2028 .flags = CLK_SET_RATE_PARENT,
2029 .ops = &clk_branch2_ops,
2030 },
2031 },
2032 };
2033
2034 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2035 .halt_reg = 0x27004,
2036 .halt_check = BRANCH_HALT_VOTED,
2037 .hwcg_reg = 0x27004,
2038 .hwcg_bit = 1,
2039 .clkr = {
2040 .enable_reg = 0x62008,
2041 .enable_mask = BIT(6),
2042 .hw.init = &(const struct clk_init_data) {
2043 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2044 .ops = &clk_branch2_ops,
2045 },
2046 },
2047 };
2048
2049 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2050 .halt_reg = 0x27008,
2051 .halt_check = BRANCH_HALT_VOTED,
2052 .hwcg_reg = 0x27008,
2053 .hwcg_bit = 1,
2054 .clkr = {
2055 .enable_reg = 0x62008,
2056 .enable_mask = BIT(7),
2057 .hw.init = &(const struct clk_init_data) {
2058 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062 };
2063
2064 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2065 .halt_reg = 0x28004,
2066 .halt_check = BRANCH_HALT_VOTED,
2067 .hwcg_reg = 0x28004,
2068 .hwcg_bit = 1,
2069 .clkr = {
2070 .enable_reg = 0x62008,
2071 .enable_mask = BIT(20),
2072 .hw.init = &(const struct clk_init_data) {
2073 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2074 .ops = &clk_branch2_ops,
2075 },
2076 },
2077 };
2078
2079 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2080 .halt_reg = 0x28008,
2081 .halt_check = BRANCH_HALT_VOTED,
2082 .hwcg_reg = 0x28008,
2083 .hwcg_bit = 1,
2084 .clkr = {
2085 .enable_reg = 0x62008,
2086 .enable_mask = BIT(21),
2087 .hw.init = &(const struct clk_init_data) {
2088 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2089 .ops = &clk_branch2_ops,
2090 },
2091 },
2092 };
2093
2094 static struct clk_branch gcc_sdcc5_ahb_clk = {
2095 .halt_reg = 0x3b00c,
2096 .halt_check = BRANCH_HALT,
2097 .clkr = {
2098 .enable_reg = 0x3b00c,
2099 .enable_mask = BIT(0),
2100 .hw.init = &(const struct clk_init_data) {
2101 .name = "gcc_sdcc5_ahb_clk",
2102 .ops = &clk_branch2_ops,
2103 },
2104 },
2105 };
2106
2107 static struct clk_branch gcc_sdcc5_apps_clk = {
2108 .halt_reg = 0x3b004,
2109 .halt_check = BRANCH_HALT,
2110 .clkr = {
2111 .enable_reg = 0x3b004,
2112 .enable_mask = BIT(0),
2113 .hw.init = &(const struct clk_init_data) {
2114 .name = "gcc_sdcc5_apps_clk",
2115 .parent_hws = (const struct clk_hw*[]) {
2116 &gcc_sdcc5_apps_clk_src.clkr.hw,
2117 },
2118 .num_parents = 1,
2119 .flags = CLK_SET_RATE_PARENT,
2120 .ops = &clk_branch2_ops,
2121 },
2122 },
2123 };
2124
2125 static struct clk_branch gcc_sdcc5_ice_core_clk = {
2126 .halt_reg = 0x3b010,
2127 .halt_check = BRANCH_HALT,
2128 .clkr = {
2129 .enable_reg = 0x3b010,
2130 .enable_mask = BIT(0),
2131 .hw.init = &(const struct clk_init_data) {
2132 .name = "gcc_sdcc5_ice_core_clk",
2133 .parent_hws = (const struct clk_hw*[]) {
2134 &gcc_sdcc5_ice_core_clk_src.clkr.hw,
2135 },
2136 .num_parents = 1,
2137 .flags = CLK_SET_RATE_PARENT,
2138 .ops = &clk_branch2_ops,
2139 },
2140 },
2141 };
2142
2143 static struct clk_branch gcc_sm_bus_ahb_clk = {
2144 .halt_reg = 0x5b004,
2145 .halt_check = BRANCH_HALT,
2146 .clkr = {
2147 .enable_reg = 0x5b004,
2148 .enable_mask = BIT(0),
2149 .hw.init = &(const struct clk_init_data) {
2150 .name = "gcc_sm_bus_ahb_clk",
2151 .ops = &clk_branch2_ops,
2152 },
2153 },
2154 };
2155
2156 static struct clk_branch gcc_sm_bus_xo_clk = {
2157 .halt_reg = 0x5b008,
2158 .halt_check = BRANCH_HALT,
2159 .clkr = {
2160 .enable_reg = 0x5b008,
2161 .enable_mask = BIT(0),
2162 .hw.init = &(const struct clk_init_data) {
2163 .name = "gcc_sm_bus_xo_clk",
2164 .parent_hws = (const struct clk_hw*[]) {
2165 &gcc_sm_bus_xo_clk_src.clkr.hw,
2166 },
2167 .num_parents = 1,
2168 .flags = CLK_SET_RATE_PARENT,
2169 .ops = &clk_branch2_ops,
2170 },
2171 },
2172 };
2173
2174 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_qx_clk = {
2175 .halt_reg = 0x9200c,
2176 .halt_check = BRANCH_HALT_SKIP,
2177 .hwcg_reg = 0x9200c,
2178 .hwcg_bit = 1,
2179 .clkr = {
2180 .enable_reg = 0x62000,
2181 .enable_mask = BIT(11),
2182 .hw.init = &(const struct clk_init_data) {
2183 .name = "gcc_snoc_cnoc_gemnoc_pcie_qx_clk",
2184 .ops = &clk_branch2_ops,
2185 },
2186 },
2187 };
2188
2189 static struct clk_branch gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk = {
2190 .halt_reg = 0x92010,
2191 .halt_check = BRANCH_HALT_SKIP,
2192 .hwcg_reg = 0x92010,
2193 .hwcg_bit = 1,
2194 .clkr = {
2195 .enable_reg = 0x62000,
2196 .enable_mask = BIT(12),
2197 .hw.init = &(const struct clk_init_data) {
2198 .name = "gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk",
2199 .ops = &clk_branch2_ops,
2200 },
2201 },
2202 };
2203
2204 static struct clk_branch gcc_snoc_cnoc_pcie_qx_clk = {
2205 .halt_reg = 0x84030,
2206 .halt_check = BRANCH_HALT,
2207 .clkr = {
2208 .enable_reg = 0x84030,
2209 .enable_mask = BIT(0),
2210 .hw.init = &(const struct clk_init_data) {
2211 .name = "gcc_snoc_cnoc_pcie_qx_clk",
2212 .ops = &clk_branch2_ops,
2213 },
2214 },
2215 };
2216
2217 static struct clk_branch gcc_snoc_pcie_sf_center_qx_clk = {
2218 .halt_reg = 0x92014,
2219 .halt_check = BRANCH_HALT_SKIP,
2220 .hwcg_reg = 0x92014,
2221 .hwcg_bit = 1,
2222 .clkr = {
2223 .enable_reg = 0x62000,
2224 .enable_mask = BIT(19),
2225 .hw.init = &(const struct clk_init_data) {
2226 .name = "gcc_snoc_pcie_sf_center_qx_clk",
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230 };
2231
2232 static struct clk_branch gcc_snoc_pcie_sf_south_qx_clk = {
2233 .halt_reg = 0x92018,
2234 .halt_check = BRANCH_HALT_SKIP,
2235 .hwcg_reg = 0x92018,
2236 .hwcg_bit = 1,
2237 .clkr = {
2238 .enable_reg = 0x62000,
2239 .enable_mask = BIT(22),
2240 .hw.init = &(const struct clk_init_data) {
2241 .name = "gcc_snoc_pcie_sf_south_qx_clk",
2242 .ops = &clk_branch2_ops,
2243 },
2244 },
2245 };
2246
2247 static struct clk_branch gcc_tsc_cfg_ahb_clk = {
2248 .halt_reg = 0x5700c,
2249 .halt_check = BRANCH_HALT,
2250 .clkr = {
2251 .enable_reg = 0x5700c,
2252 .enable_mask = BIT(0),
2253 .hw.init = &(const struct clk_init_data) {
2254 .name = "gcc_tsc_cfg_ahb_clk",
2255 .ops = &clk_branch2_ops,
2256 },
2257 },
2258 };
2259
2260 static struct clk_branch gcc_tsc_cntr_clk = {
2261 .halt_reg = 0x57004,
2262 .halt_check = BRANCH_HALT,
2263 .clkr = {
2264 .enable_reg = 0x57004,
2265 .enable_mask = BIT(0),
2266 .hw.init = &(const struct clk_init_data) {
2267 .name = "gcc_tsc_cntr_clk",
2268 .parent_hws = (const struct clk_hw*[]) {
2269 &gcc_tsc_clk_src.clkr.hw,
2270 },
2271 .num_parents = 1,
2272 .flags = CLK_SET_RATE_PARENT,
2273 .ops = &clk_branch2_ops,
2274 },
2275 },
2276 };
2277
2278 static struct clk_branch gcc_tsc_etu_clk = {
2279 .halt_reg = 0x57008,
2280 .halt_check = BRANCH_HALT,
2281 .clkr = {
2282 .enable_reg = 0x57008,
2283 .enable_mask = BIT(0),
2284 .hw.init = &(const struct clk_init_data) {
2285 .name = "gcc_tsc_etu_clk",
2286 .parent_hws = (const struct clk_hw*[]) {
2287 &gcc_tsc_clk_src.clkr.hw,
2288 },
2289 .num_parents = 1,
2290 .flags = CLK_SET_RATE_PARENT,
2291 .ops = &clk_branch2_ops,
2292 },
2293 },
2294 };
2295
2296 static struct clk_branch gcc_usb2_clkref_en = {
2297 .halt_reg = 0x9c008,
2298 .halt_check = BRANCH_HALT,
2299 .clkr = {
2300 .enable_reg = 0x9c008,
2301 .enable_mask = BIT(0),
2302 .hw.init = &(const struct clk_init_data) {
2303 .name = "gcc_usb2_clkref_en",
2304 .ops = &clk_branch2_ops,
2305 },
2306 },
2307 };
2308
2309 static struct clk_branch gcc_usb30_prim_master_clk = {
2310 .halt_reg = 0x49018,
2311 .halt_check = BRANCH_HALT,
2312 .clkr = {
2313 .enable_reg = 0x49018,
2314 .enable_mask = BIT(0),
2315 .hw.init = &(const struct clk_init_data) {
2316 .name = "gcc_usb30_prim_master_clk",
2317 .parent_hws = (const struct clk_hw*[]) {
2318 &gcc_usb30_prim_master_clk_src.clkr.hw,
2319 },
2320 .num_parents = 1,
2321 .flags = CLK_SET_RATE_PARENT,
2322 .ops = &clk_branch2_ops,
2323 },
2324 },
2325 };
2326
2327 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2328 .halt_reg = 0x49024,
2329 .halt_check = BRANCH_HALT,
2330 .clkr = {
2331 .enable_reg = 0x49024,
2332 .enable_mask = BIT(0),
2333 .hw.init = &(const struct clk_init_data) {
2334 .name = "gcc_usb30_prim_mock_utmi_clk",
2335 .parent_hws = (const struct clk_hw*[]) {
2336 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2337 },
2338 .num_parents = 1,
2339 .flags = CLK_SET_RATE_PARENT,
2340 .ops = &clk_branch2_ops,
2341 },
2342 },
2343 };
2344
2345 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2346 .halt_reg = 0x49020,
2347 .halt_check = BRANCH_HALT,
2348 .clkr = {
2349 .enable_reg = 0x49020,
2350 .enable_mask = BIT(0),
2351 .hw.init = &(const struct clk_init_data) {
2352 .name = "gcc_usb30_prim_sleep_clk",
2353 .ops = &clk_branch2_ops,
2354 },
2355 },
2356 };
2357
2358 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2359 .halt_reg = 0x49060,
2360 .halt_check = BRANCH_HALT,
2361 .clkr = {
2362 .enable_reg = 0x49060,
2363 .enable_mask = BIT(0),
2364 .hw.init = &(const struct clk_init_data) {
2365 .name = "gcc_usb3_prim_phy_aux_clk",
2366 .parent_hws = (const struct clk_hw*[]) {
2367 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2368 },
2369 .num_parents = 1,
2370 .flags = CLK_SET_RATE_PARENT,
2371 .ops = &clk_branch2_ops,
2372 },
2373 },
2374 };
2375
2376 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2377 .halt_reg = 0x49064,
2378 .halt_check = BRANCH_HALT,
2379 .clkr = {
2380 .enable_reg = 0x49064,
2381 .enable_mask = BIT(0),
2382 .hw.init = &(const struct clk_init_data) {
2383 .name = "gcc_usb3_prim_phy_com_aux_clk",
2384 .parent_hws = (const struct clk_hw*[]) {
2385 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2386 },
2387 .num_parents = 1,
2388 .flags = CLK_SET_RATE_PARENT,
2389 .ops = &clk_branch2_ops,
2390 },
2391 },
2392 };
2393
2394 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2395 .halt_reg = 0x49068,
2396 .halt_check = BRANCH_HALT_DELAY,
2397 .hwcg_reg = 0x49068,
2398 .hwcg_bit = 1,
2399 .clkr = {
2400 .enable_reg = 0x49068,
2401 .enable_mask = BIT(0),
2402 .hw.init = &(const struct clk_init_data) {
2403 .name = "gcc_usb3_prim_phy_pipe_clk",
2404 .parent_hws = (const struct clk_hw*[]) {
2405 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2406 },
2407 .num_parents = 1,
2408 .flags = CLK_SET_RATE_PARENT,
2409 .ops = &clk_branch2_ops,
2410 },
2411 },
2412 };
2413
2414 static struct gdsc pcie_0_gdsc = {
2415 .gdscr = 0x9d004,
2416 .en_rest_wait_val = 0x2,
2417 .en_few_wait_val = 0x2,
2418 .clk_dis_wait_val = 0xf,
2419 .pd = {
2420 .name = "gcc_pcie_0_gdsc",
2421 },
2422 .pwrsts = PWRSTS_OFF_ON,
2423 };
2424
2425 static struct gdsc pcie_0_phy_gdsc = {
2426 .gdscr = 0x7c004,
2427 .en_rest_wait_val = 0x2,
2428 .en_few_wait_val = 0x2,
2429 .clk_dis_wait_val = 0x2,
2430 .pd = {
2431 .name = "gcc_pcie_0_phy_gdsc",
2432 },
2433 .pwrsts = PWRSTS_OFF_ON,
2434 };
2435
2436 static struct gdsc usb30_prim_gdsc = {
2437 .gdscr = 0x49004,
2438 .en_rest_wait_val = 0x2,
2439 .en_few_wait_val = 0x2,
2440 .clk_dis_wait_val = 0xf,
2441 .pd = {
2442 .name = "gcc_usb30_prim_gdsc",
2443 },
2444 .pwrsts = PWRSTS_OFF_ON,
2445 };
2446
2447 static struct clk_regmap *gcc_qdu1000_clocks[] = {
2448 [GCC_AGGRE_NOC_ECPRI_DMA_CLK] = &gcc_aggre_noc_ecpri_dma_clk.clkr,
2449 [GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC] = &gcc_aggre_noc_ecpri_dma_clk_src.clkr,
2450 [GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC] = &gcc_aggre_noc_ecpri_gsi_clk_src.clkr,
2451 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2452 [GCC_CFG_NOC_ECPRI_CC_AHB_CLK] = &gcc_cfg_noc_ecpri_cc_ahb_clk.clkr,
2453 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2454 [GCC_DDRSS_ECPRI_DMA_CLK] = &gcc_ddrss_ecpri_dma_clk.clkr,
2455 [GCC_ECPRI_AHB_CLK] = &gcc_ecpri_ahb_clk.clkr,
2456 [GCC_ECPRI_CC_GPLL0_CLK_SRC] = &gcc_ecpri_cc_gpll0_clk_src.clkr,
2457 [GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll1_even_clk_src.clkr,
2458 [GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll2_even_clk_src.clkr,
2459 [GCC_ECPRI_CC_GPLL3_CLK_SRC] = &gcc_ecpri_cc_gpll3_clk_src.clkr,
2460 [GCC_ECPRI_CC_GPLL4_CLK_SRC] = &gcc_ecpri_cc_gpll4_clk_src.clkr,
2461 [GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC] = &gcc_ecpri_cc_gpll5_even_clk_src.clkr,
2462 [GCC_ECPRI_XO_CLK] = &gcc_ecpri_xo_clk.clkr,
2463 [GCC_ETH_DBG_SNOC_AXI_CLK] = &gcc_eth_dbg_snoc_axi_clk.clkr,
2464 [GCC_GEMNOC_PCIE_QX_CLK] = &gcc_gemnoc_pcie_qx_clk.clkr,
2465 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2466 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2467 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2468 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2469 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2470 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2471 [GCC_GPLL0] = &gcc_gpll0.clkr,
2472 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
2473 [GCC_GPLL1] = &gcc_gpll1.clkr,
2474 [GCC_GPLL2] = &gcc_gpll2.clkr,
2475 [GCC_GPLL2_OUT_EVEN] = &gcc_gpll2_out_even.clkr,
2476 [GCC_GPLL3] = &gcc_gpll3.clkr,
2477 [GCC_GPLL4] = &gcc_gpll4.clkr,
2478 [GCC_GPLL5] = &gcc_gpll5.clkr,
2479 [GCC_GPLL5_OUT_EVEN] = &gcc_gpll5_out_even.clkr,
2480 [GCC_GPLL6] = &gcc_gpll6.clkr,
2481 [GCC_GPLL7] = &gcc_gpll7.clkr,
2482 [GCC_GPLL8] = &gcc_gpll8.clkr,
2483 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2484 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
2485 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2486 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
2487 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2488 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr,
2489 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
2490 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
2491 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2492 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2493 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
2494 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2495 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2496 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2497 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2498 [GCC_QMIP_ANOC_PCIE_CLK] = &gcc_qmip_anoc_pcie_clk.clkr,
2499 [GCC_QMIP_ECPRI_DMA0_CLK] = &gcc_qmip_ecpri_dma0_clk.clkr,
2500 [GCC_QMIP_ECPRI_DMA1_CLK] = &gcc_qmip_ecpri_dma1_clk.clkr,
2501 [GCC_QMIP_ECPRI_GSI_CLK] = &gcc_qmip_ecpri_gsi_clk.clkr,
2502 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2503 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2504 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2505 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2506 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2507 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2508 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2509 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2510 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2511 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2512 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2513 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2514 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2515 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2516 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
2517 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
2518 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
2519 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
2520 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2521 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2522 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2523 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2524 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2525 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2526 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2527 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2528 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2529 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2530 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2531 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2532 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2533 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2534 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
2535 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
2536 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
2537 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
2538 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2539 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2540 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2541 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2542 [GCC_SDCC5_AHB_CLK] = &gcc_sdcc5_ahb_clk.clkr,
2543 [GCC_SDCC5_APPS_CLK] = &gcc_sdcc5_apps_clk.clkr,
2544 [GCC_SDCC5_APPS_CLK_SRC] = &gcc_sdcc5_apps_clk_src.clkr,
2545 [GCC_SDCC5_ICE_CORE_CLK] = &gcc_sdcc5_ice_core_clk.clkr,
2546 [GCC_SDCC5_ICE_CORE_CLK_SRC] = &gcc_sdcc5_ice_core_clk_src.clkr,
2547 [GCC_SM_BUS_AHB_CLK] = &gcc_sm_bus_ahb_clk.clkr,
2548 [GCC_SM_BUS_XO_CLK] = &gcc_sm_bus_xo_clk.clkr,
2549 [GCC_SM_BUS_XO_CLK_SRC] = &gcc_sm_bus_xo_clk_src.clkr,
2550 [GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_qx_clk.clkr,
2551 [GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK] = &gcc_snoc_cnoc_gemnoc_pcie_south_qx_clk.clkr,
2552 [GCC_SNOC_CNOC_PCIE_QX_CLK] = &gcc_snoc_cnoc_pcie_qx_clk.clkr,
2553 [GCC_SNOC_PCIE_SF_CENTER_QX_CLK] = &gcc_snoc_pcie_sf_center_qx_clk.clkr,
2554 [GCC_SNOC_PCIE_SF_SOUTH_QX_CLK] = &gcc_snoc_pcie_sf_south_qx_clk.clkr,
2555 [GCC_TSC_CFG_AHB_CLK] = &gcc_tsc_cfg_ahb_clk.clkr,
2556 [GCC_TSC_CLK_SRC] = &gcc_tsc_clk_src.clkr,
2557 [GCC_TSC_CNTR_CLK] = &gcc_tsc_cntr_clk.clkr,
2558 [GCC_TSC_ETU_CLK] = &gcc_tsc_etu_clk.clkr,
2559 [GCC_USB2_CLKREF_EN] = &gcc_usb2_clkref_en.clkr,
2560 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2561 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2562 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2563 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2564 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
2565 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2566 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2567 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2568 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2569 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2570 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
2571 [GCC_ETH_100G_C2C_HM_APB_CLK] = &gcc_eth_100g_c2c_hm_apb_clk.clkr,
2572 [GCC_ETH_100G_FH_HM_APB_0_CLK] = &gcc_eth_100g_fh_hm_apb_0_clk.clkr,
2573 [GCC_ETH_100G_FH_HM_APB_1_CLK] = &gcc_eth_100g_fh_hm_apb_1_clk.clkr,
2574 [GCC_ETH_100G_FH_HM_APB_2_CLK] = &gcc_eth_100g_fh_hm_apb_2_clk.clkr,
2575 [GCC_ETH_DBG_C2C_HM_APB_CLK] = &gcc_eth_dbg_c2c_hm_apb_clk.clkr,
2576 [GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
2577 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
2578 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
2579 [GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
2580 [GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
2581 };
2582
2583 static struct gdsc *gcc_qdu1000_gdscs[] = {
2584 [PCIE_0_GDSC] = &pcie_0_gdsc,
2585 [PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
2586 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2587 };
2588
2589 static const struct qcom_reset_map gcc_qdu1000_resets[] = {
2590 [GCC_ECPRI_CC_BCR] = { 0x3e000 },
2591 [GCC_ECPRI_SS_BCR] = { 0x3a000 },
2592 [GCC_ETH_WRAPPER_BCR] = { 0x39000 },
2593 [GCC_PCIE_0_BCR] = { 0x9d000 },
2594 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x9e014 },
2595 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x9e020 },
2596 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 },
2597 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
2598 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
2599 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
2600 [GCC_PDM_BCR] = { 0x43000 },
2601 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
2602 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
2603 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
2604 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
2605 [GCC_SDCC5_BCR] = { 0x3b000 },
2606 [GCC_TSC_BCR] = { 0x57000 },
2607 [GCC_USB30_PRIM_BCR] = { 0x49000 },
2608 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
2609 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
2610 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
2611 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
2612 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
2613 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
2614 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
2615 };
2616
2617 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2618 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2619 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2620 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2621 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2622 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2623 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2624 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
2625 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
2626 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2627 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2628 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2629 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2630 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2631 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2632 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
2633 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
2634 };
2635
2636 static const struct regmap_config gcc_qdu1000_regmap_config = {
2637 .reg_bits = 32,
2638 .reg_stride = 4,
2639 .val_bits = 32,
2640 .max_register = 0x1f41f0,
2641 .fast_io = true,
2642 };
2643
2644 static const struct qcom_cc_desc gcc_qdu1000_desc = {
2645 .config = &gcc_qdu1000_regmap_config,
2646 .clks = gcc_qdu1000_clocks,
2647 .num_clks = ARRAY_SIZE(gcc_qdu1000_clocks),
2648 .resets = gcc_qdu1000_resets,
2649 .num_resets = ARRAY_SIZE(gcc_qdu1000_resets),
2650 .gdscs = gcc_qdu1000_gdscs,
2651 .num_gdscs = ARRAY_SIZE(gcc_qdu1000_gdscs),
2652 };
2653
2654 static const struct of_device_id gcc_qdu1000_match_table[] = {
2655 { .compatible = "qcom,qdu1000-gcc" },
2656 { }
2657 };
2658 MODULE_DEVICE_TABLE(of, gcc_qdu1000_match_table);
2659
2660 static int gcc_qdu1000_probe(struct platform_device *pdev)
2661 {
2662 struct regmap *regmap;
2663 int ret;
2664
2665 regmap = qcom_cc_map(pdev, &gcc_qdu1000_desc);
2666 if (IS_ERR(regmap))
2667 return PTR_ERR(regmap);
2668
2669 /* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */
2670 regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14));
2671
2672 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2673 ARRAY_SIZE(gcc_dfs_clocks));
2674 if (ret)
2675 return ret;
2676
2677 ret = qcom_cc_really_probe(&pdev->dev, &gcc_qdu1000_desc, regmap);
2678 if (ret)
2679 return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n");
2680
2681 return ret;
2682 }
2683
2684 static struct platform_driver gcc_qdu1000_driver = {
2685 .probe = gcc_qdu1000_probe,
2686 .driver = {
2687 .name = "gcc-qdu1000",
2688 .of_match_table = gcc_qdu1000_match_table,
2689 },
2690 };
2691
2692 static int __init gcc_qdu1000_init(void)
2693 {
2694 return platform_driver_register(&gcc_qdu1000_driver);
2695 }
2696 subsys_initcall(gcc_qdu1000_init);
2697
2698 static void __exit gcc_qdu1000_exit(void)
2699 {
2700 platform_driver_unregister(&gcc_qdu1000_driver);
2701 }
2702 module_exit(gcc_qdu1000_exit);
2703
2704 MODULE_DESCRIPTION("QTI GCC QDU1000 Driver");
2705 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes