drivers/clk/qcom/gcc-sdx65.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/err.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/regmap.h>
  13
  14 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
  15
  16 #include "clk-alpha-pll.h"
  17 #include "clk-branch.h"
  18 #include "clk-rcg.h"
  19 #include "clk-regmap.h"
  20 #include "clk-regmap-divider.h"
  21 #include "clk-regmap-mux.h"
  22 #include "common.h"
  23 #include "gdsc.h"
  24 #include "reset.h"
  25
  26 enum {
  27         P_BI_TCXO,
  28         P_GPLL0_OUT_EVEN,
  29         P_GPLL0_OUT_MAIN,
  30         P_PCIE_PIPE_CLK,
  31         P_SLEEP_CLK,
  32         P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  33 };
  34
  35 static struct clk_alpha_pll gpll0 = {
  36         .offset = 0x0,
  37         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  38         .clkr = {
  39                 .enable_reg = 0x6d000,
  40                 .enable_mask = BIT(0),
  41                 .hw.init = &(struct clk_init_data){
  42                         .name = "gpll0",
  43                         .parent_data = &(const struct clk_parent_data){
  44                                 .fw_name = "bi_tcxo",
  45                         },
  46                         .num_parents = 1,
  47                         .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
  48                 },
  49         },
  50 };
  51
  52 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
  53         { 0x1, 2 },
  54         { }
  55 };
  56
  57 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  58         .offset = 0x0,
  59         .post_div_shift = 10,
  60         .post_div_table = post_div_table_gpll0_out_even,
  61         .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
  62         .width = 4,
  63         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  64         .clkr.hw.init = &(struct clk_init_data){
  65                 .name = "gpll0_out_even",
  66                 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
  67                 .num_parents = 1,
  68                 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
  69         },
  70 };
  71
  72 static const struct parent_map gcc_parent_map_0[] = {
  73         { P_BI_TCXO, 0 },
  74         { P_GPLL0_OUT_MAIN, 1 },
  75         { P_GPLL0_OUT_EVEN, 6 },
  76 };
  77
  78 static const struct clk_parent_data gcc_parent_data_0[] = {
  79         { .fw_name = "bi_tcxo" },
  80         { .hw = &gpll0.clkr.hw },
  81         { .hw = &gpll0_out_even.clkr.hw },
  82 };
  83
  84 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
  85         { .fw_name = "bi_tcxo_ao" },
  86         { .hw = &gpll0.clkr.hw },
  87         { .hw = &gpll0_out_even.clkr.hw },
  88 };
  89
  90 static const struct parent_map gcc_parent_map_2[] = {
  91         { P_BI_TCXO, 0 },
  92         { P_GPLL0_OUT_MAIN, 1 },
  93         { P_SLEEP_CLK, 5 },
  94         { P_GPLL0_OUT_EVEN, 6 },
  95 };
  96
  97 static const struct clk_parent_data gcc_parent_data_2[] = {
  98         { .fw_name = "bi_tcxo" },
  99         { .hw = &gpll0.clkr.hw },
 100         { .fw_name = "sleep_clk" },
 101         { .hw = &gpll0_out_even.clkr.hw },
 102 };
 103
 104 static const struct parent_map gcc_parent_map_3[] = {
 105         { P_BI_TCXO, 0 },
 106         { P_SLEEP_CLK, 5 },
 107 };
 108
 109 static const struct clk_parent_data gcc_parent_data_3[] = {
 110         { .fw_name = "bi_tcxo" },
 111         { .fw_name = "sleep_clk" },
 112 };
 113
 114 static const struct parent_map gcc_parent_map_4[] = {
 115         { P_BI_TCXO, 2 },
 116 };
 117
 118 static const struct parent_map gcc_parent_map_5[] = {
 119         { P_PCIE_PIPE_CLK, 0 },
 120         { P_BI_TCXO, 2 },
 121 };
 122
 123 static const struct clk_parent_data gcc_parent_data_5[] = {
 124         { .fw_name = "pcie_pipe_clk"},
 125         { .fw_name = "bi_tcxo"},
 126 };
 127
 128 static const struct parent_map gcc_parent_map_6[] = {
 129         { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 130         { P_BI_TCXO, 2 },
 131 };
 132
 133 static const struct clk_parent_data gcc_parent_data_6[] = {
 134         { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk"},
 135         { .fw_name = "bi_tcxo"},
 136 };
 137
 138 static struct clk_regmap_mux gcc_pcie_aux_clk_src = {
 139         .reg = 0x43060,
 140         .shift = 0,
 141         .width = 2,
 142         .parent_map = gcc_parent_map_4,
 143         .clkr = {
 144                 .hw.init = &(struct clk_init_data){
 145                         .name = "gcc_pcie_aux_clk_src",
 146                         .parent_data = &(const struct clk_parent_data){
 147                                 .fw_name = "bi_tcxo",
 148                         },
 149                         .num_parents = 1,
 150                         .ops = &clk_regmap_mux_closest_ops,
 151                 },
 152         },
 153 };
 154
 155 static struct clk_regmap_mux gcc_pcie_pipe_clk_src = {
 156         .reg = 0x43044,
 157         .shift = 0,
 158         .width = 2,
 159         .parent_map = gcc_parent_map_5,
 160         .clkr = {
 161                 .hw.init = &(struct clk_init_data){
 162                         .name = "gcc_pcie_pipe_clk_src",
 163                         .parent_data = gcc_parent_data_5,
 164                         .num_parents = 2,
 165                         .ops = &clk_regmap_mux_closest_ops,
 166                 },
 167         },
 168 };
 169
 170 static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = {
 171         .reg = 0x1706c,
 172         .shift = 0,
 173         .width = 2,
 174         .parent_map = gcc_parent_map_6,
 175         .clkr = {
 176                 .hw.init = &(struct clk_init_data){
 177                         .name = "gcc_usb3_phy_pipe_clk_src",
 178                         .parent_data = gcc_parent_data_6,
 179                         .num_parents = 2,
 180                         .ops = &clk_regmap_mux_closest_ops,
 181                 },
 182         },
 183 };
 184
 185 static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {
 186         F(9600000, P_BI_TCXO, 2, 0, 0),
 187         F(19200000, P_BI_TCXO, 1, 0, 0),
 188         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 189         { }
 190 };
 191
 192 static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = {
 193         .cmd_rcgr = 0x1c024,
 194         .mnd_width = 8,
 195         .hid_width = 5,
 196         .parent_map = gcc_parent_map_0,
 197         .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
 198         .clkr.hw.init = &(struct clk_init_data){
 199                 .name = "gcc_blsp1_qup1_i2c_apps_clk_src",
 200                 .parent_data = gcc_parent_data_0,
 201                 .num_parents = 3,
 202                 .flags = CLK_SET_RATE_PARENT,
 203                 .ops = &clk_rcg2_ops,
 204         },
 205 };
 206
 207 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
 208         F(960000, P_BI_TCXO, 10, 1, 2),
 209         F(4800000, P_BI_TCXO, 4, 0, 0),
 210         F(9600000, P_BI_TCXO, 2, 0, 0),
 211         F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4),
 212         F(19200000, P_BI_TCXO, 1, 0, 0),
 213         F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2),
 214         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 215         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 216         { }
 217 };
 218
 219 static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
 220         .cmd_rcgr = 0x1c00c,
 221         .mnd_width = 8,
 222         .hid_width = 5,
 223         .parent_map = gcc_parent_map_0,
 224         .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
 225         .clkr.hw.init = &(struct clk_init_data){
 226                 .name = "gcc_blsp1_qup1_spi_apps_clk_src",
 227                 .parent_data = gcc_parent_data_0,
 228                 .num_parents = 3,
 229                 .flags = CLK_SET_RATE_PARENT,
 230                 .ops = &clk_rcg2_ops,
 231         },
 232 };
 233
 234 static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = {
 235         .cmd_rcgr = 0x1e024,
 236         .mnd_width = 8,
 237         .hid_width = 5,
 238         .parent_map = gcc_parent_map_0,
 239         .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
 240         .clkr.hw.init = &(struct clk_init_data){
 241                 .name = "gcc_blsp1_qup2_i2c_apps_clk_src",
 242                 .parent_data = gcc_parent_data_0,
 243                 .num_parents = 3,
 244                 .flags = CLK_SET_RATE_PARENT,
 245                 .ops = &clk_rcg2_ops,
 246         },
 247 };
 248
 249 static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
 250         .cmd_rcgr = 0x1e00c,
 251         .mnd_width = 8,
 252         .hid_width = 5,
 253         .parent_map = gcc_parent_map_0,
 254         .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
 255         .clkr.hw.init = &(struct clk_init_data){
 256                 .name = "gcc_blsp1_qup2_spi_apps_clk_src",
 257                 .parent_data = gcc_parent_data_0,
 258                 .num_parents = 3,
 259                 .flags = CLK_SET_RATE_PARENT,
 260                 .ops = &clk_rcg2_ops,
 261         },
 262 };
 263
 264 static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = {
 265         .cmd_rcgr = 0x20024,
 266         .mnd_width = 8,
 267         .hid_width = 5,
 268         .parent_map = gcc_parent_map_0,
 269         .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
 270         .clkr.hw.init = &(struct clk_init_data){
 271                 .name = "gcc_blsp1_qup3_i2c_apps_clk_src",
 272                 .parent_data = gcc_parent_data_0,
 273                 .num_parents = 3,
 274                 .flags = CLK_SET_RATE_PARENT,
 275                 .ops = &clk_rcg2_ops,
 276         },
 277 };
 278
 279 static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
 280         .cmd_rcgr = 0x2000c,
 281         .mnd_width = 8,
 282         .hid_width = 5,
 283         .parent_map = gcc_parent_map_0,
 284         .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
 285         .clkr.hw.init = &(struct clk_init_data){
 286                 .name = "gcc_blsp1_qup3_spi_apps_clk_src",
 287                 .parent_data = gcc_parent_data_0,
 288                 .num_parents = 3,
 289                 .flags = CLK_SET_RATE_PARENT,
 290                 .ops = &clk_rcg2_ops,
 291         },
 292 };
 293
 294 static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = {
 295         .cmd_rcgr = 0x22024,
 296         .mnd_width = 8,
 297         .hid_width = 5,
 298         .parent_map = gcc_parent_map_0,
 299         .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
 300         .clkr.hw.init = &(struct clk_init_data){
 301                 .name = "gcc_blsp1_qup4_i2c_apps_clk_src",
 302                 .parent_data = gcc_parent_data_0,
 303                 .num_parents = 3,
 304                 .flags = CLK_SET_RATE_PARENT,
 305                 .ops = &clk_rcg2_ops,
 306         },
 307 };
 308
 309 static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = {
 310         .cmd_rcgr = 0x2200c,
 311         .mnd_width = 8,
 312         .hid_width = 5,
 313         .parent_map = gcc_parent_map_0,
 314         .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
 315         .clkr.hw.init = &(struct clk_init_data){
 316                 .name = "gcc_blsp1_qup4_spi_apps_clk_src",
 317                 .parent_data = gcc_parent_data_0,
 318                 .num_parents = 3,
 319                 .flags = CLK_SET_RATE_PARENT,
 320                 .ops = &clk_rcg2_ops,
 321         },
 322 };
 323
 324 static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
 325         F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625),
 326         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 327         F(9600000, P_BI_TCXO, 2, 0, 0),
 328         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 329         F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75),
 330         F(19200000, P_BI_TCXO, 1, 0, 0),
 331         F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2),
 332         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
 333         F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2),
 334         F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2),
 335         F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2),
 336         F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2),
 337         F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
 338         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 339         F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2),
 340         F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2),
 341         F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2),
 342         F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
 343         F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
 344         F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
 345         F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 346         F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
 347         F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
 348         F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
 349         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 350         F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
 351         { }
 352 };
 353
 354 static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
 355         .cmd_rcgr = 0x1d00c,
 356         .mnd_width = 16,
 357         .hid_width = 5,
 358         .parent_map = gcc_parent_map_0,
 359         .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
 360         .clkr.hw.init = &(struct clk_init_data){
 361                 .name = "gcc_blsp1_uart1_apps_clk_src",
 362                 .parent_data = gcc_parent_data_0,
 363                 .num_parents = 3,
 364                 .flags = CLK_SET_RATE_PARENT,
 365                 .ops = &clk_rcg2_ops,
 366         },
 367 };
 368
 369 static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
 370         .cmd_rcgr = 0x1f00c,
 371         .mnd_width = 16,
 372         .hid_width = 5,
 373         .parent_map = gcc_parent_map_0,
 374         .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
 375         .clkr.hw.init = &(struct clk_init_data){
 376                 .name = "gcc_blsp1_uart2_apps_clk_src",
 377                 .parent_data = gcc_parent_data_0,
 378                 .num_parents = 3,
 379                 .flags = CLK_SET_RATE_PARENT,
 380                 .ops = &clk_rcg2_ops,
 381         },
 382 };
 383
 384 static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
 385         .cmd_rcgr = 0x2100c,
 386         .mnd_width = 16,
 387         .hid_width = 5,
 388         .parent_map = gcc_parent_map_0,
 389         .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
 390         .clkr.hw.init = &(struct clk_init_data){
 391                 .name = "gcc_blsp1_uart3_apps_clk_src",
 392                 .parent_data = gcc_parent_data_0,
 393                 .num_parents = 3,
 394                 .flags = CLK_SET_RATE_PARENT,
 395                 .ops = &clk_rcg2_ops,
 396         },
 397 };
 398
 399 static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = {
 400         .cmd_rcgr = 0x2300c,
 401         .mnd_width = 16,
 402         .hid_width = 5,
 403         .parent_map = gcc_parent_map_0,
 404         .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
 405         .clkr.hw.init = &(struct clk_init_data){
 406                 .name = "gcc_blsp1_uart4_apps_clk_src",
 407                 .parent_data = gcc_parent_data_0,
 408                 .num_parents = 3,
 409                 .flags = CLK_SET_RATE_PARENT,
 410                 .ops = &clk_rcg2_ops,
 411         },
 412 };
 413
 414 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 415         F(19200000, P_BI_TCXO, 1, 0, 0),
 416         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 417         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 418         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 419         { }
 420 };
 421
 422 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 423         .cmd_rcgr = 0x3000c,
 424         .mnd_width = 0,
 425         .hid_width = 5,
 426         .parent_map = gcc_parent_map_0,
 427         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 428         .clkr.hw.init = &(struct clk_init_data){
 429                 .name = "gcc_cpuss_ahb_clk_src",
 430                 .parent_data = gcc_parent_data_0_ao,
 431                 .num_parents = 3,
 432                 .flags = CLK_SET_RATE_PARENT,
 433                 .ops = &clk_rcg2_ops,
 434         },
 435 };
 436
 437 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 438         F(19200000, P_BI_TCXO, 1, 0, 0),
 439         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 440         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 441         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 442         { }
 443 };
 444
 445 static struct clk_rcg2 gcc_gp1_clk_src = {
 446         .cmd_rcgr = 0x37004,
 447         .mnd_width = 16,
 448         .hid_width = 5,
 449         .parent_map = gcc_parent_map_2,
 450         .freq_tbl = ftbl_gcc_gp1_clk_src,
 451         .clkr.hw.init = &(struct clk_init_data){
 452                 .name = "gcc_gp1_clk_src",
 453                 .parent_data = gcc_parent_data_2,
 454                 .num_parents = 4,
 455                 .flags = CLK_SET_RATE_PARENT,
 456                 .ops = &clk_rcg2_ops,
 457         },
 458 };
 459
 460 static struct clk_rcg2 gcc_gp2_clk_src = {
 461         .cmd_rcgr = 0x38004,
 462         .mnd_width = 16,
 463         .hid_width = 5,
 464         .parent_map = gcc_parent_map_2,
 465         .freq_tbl = ftbl_gcc_gp1_clk_src,
 466         .clkr.hw.init = &(struct clk_init_data){
 467                 .name = "gcc_gp2_clk_src",
 468                 .parent_data = gcc_parent_data_2,
 469                 .num_parents = 4,
 470                 .flags = CLK_SET_RATE_PARENT,
 471                 .ops = &clk_rcg2_ops,
 472         },
 473 };
 474
 475 static struct clk_rcg2 gcc_gp3_clk_src = {
 476         .cmd_rcgr = 0x39004,
 477         .mnd_width = 16,
 478         .hid_width = 5,
 479         .parent_map = gcc_parent_map_2,
 480         .freq_tbl = ftbl_gcc_gp1_clk_src,
 481         .clkr.hw.init = &(struct clk_init_data){
 482                 .name = "gcc_gp3_clk_src",
 483                 .parent_data = gcc_parent_data_2,
 484                 .num_parents = 4,
 485                 .flags = CLK_SET_RATE_PARENT,
 486                 .ops = &clk_rcg2_ops,
 487         },
 488 };
 489
 490 static const struct freq_tbl ftbl_gcc_pcie_aux_phy_clk_src[] = {
 491         F(19200000, P_BI_TCXO, 1, 0, 0),
 492         { }
 493 };
 494
 495 static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
 496         .cmd_rcgr = 0x43048,
 497         .mnd_width = 16,
 498         .hid_width = 5,
 499         .parent_map = gcc_parent_map_3,
 500         .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src,
 501         .clkr.hw.init = &(struct clk_init_data){
 502                 .name = "gcc_pcie_aux_phy_clk_src",
 503                 .parent_data = gcc_parent_data_3,
 504                 .num_parents = 2,
 505                 .flags = CLK_SET_RATE_PARENT,
 506                 .ops = &clk_rcg2_ops,
 507         },
 508 };
 509
 510 static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = {
 511         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 512         { }
 513 };
 514
 515 static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
 516         .cmd_rcgr = 0x43064,
 517         .mnd_width = 0,
 518         .hid_width = 5,
 519         .parent_map = gcc_parent_map_2,
 520         .freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src,
 521         .clkr.hw.init = &(struct clk_init_data){
 522                 .name = "gcc_pcie_rchng_phy_clk_src",
 523                 .parent_data = gcc_parent_data_2,
 524                 .num_parents = 4,
 525                 .flags = CLK_SET_RATE_PARENT,
 526                 .ops = &clk_rcg2_ops,
 527         },
 528 };
 529
 530 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 531         F(19200000, P_BI_TCXO, 1, 0, 0),
 532         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 533         { }
 534 };
 535
 536 static struct clk_rcg2 gcc_pdm2_clk_src = {
 537         .cmd_rcgr = 0x24010,
 538         .mnd_width = 0,
 539         .hid_width = 5,
 540         .parent_map = gcc_parent_map_0,
 541         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 542         .clkr.hw.init = &(struct clk_init_data){
 543                 .name = "gcc_pdm2_clk_src",
 544                 .parent_data = gcc_parent_data_0,
 545                 .num_parents = 3,
 546                 .flags = CLK_SET_RATE_PARENT,
 547                 .ops = &clk_rcg2_ops,
 548         },
 549 };
 550
 551 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 552         F(400000, P_BI_TCXO, 12, 1, 4),
 553         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 554         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 555         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 556         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 557         { }
 558 };
 559
 560 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 561         .cmd_rcgr = 0x1a010,
 562         .mnd_width = 8,
 563         .hid_width = 5,
 564         .parent_map = gcc_parent_map_0,
 565         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 566         .clkr.hw.init = &(struct clk_init_data){
 567                 .name = "gcc_sdcc1_apps_clk_src",
 568                 .parent_data = gcc_parent_data_0,
 569                 .num_parents = 3,
 570                 .flags = CLK_SET_RATE_PARENT,
 571                 .ops = &clk_rcg2_ops,
 572         },
 573 };
 574
 575 static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
 576         F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
 577         { }
 578 };
 579
 580 static struct clk_rcg2 gcc_usb30_master_clk_src = {
 581         .cmd_rcgr = 0x17030,
 582         .mnd_width = 8,
 583         .hid_width = 5,
 584         .parent_map = gcc_parent_map_0,
 585         .freq_tbl = ftbl_gcc_usb30_master_clk_src,
 586         .clkr.hw.init = &(struct clk_init_data){
 587                 .name = "gcc_usb30_master_clk_src",
 588                 .parent_data = gcc_parent_data_0,
 589                 .num_parents = 3,
 590                 .flags = CLK_SET_RATE_PARENT,
 591                 .ops = &clk_rcg2_ops,
 592         },
 593 };
 594
 595 static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
 596         .cmd_rcgr = 0x17048,
 597         .mnd_width = 0,
 598         .hid_width = 5,
 599         .parent_map = gcc_parent_map_0,
 600         .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src,
 601         .clkr.hw.init = &(struct clk_init_data){
 602                 .name = "gcc_usb30_mock_utmi_clk_src",
 603                 .parent_data = gcc_parent_data_0,
 604                 .num_parents = 3,
 605                 .flags = CLK_SET_RATE_PARENT,
 606                 .ops = &clk_rcg2_ops,
 607         },
 608 };
 609
 610 static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
 611         F(1000000, P_BI_TCXO, 1, 5, 96),
 612         F(19200000, P_BI_TCXO, 1, 0, 0),
 613         { }
 614 };
 615
 616 static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
 617         .cmd_rcgr = 0x17070,
 618         .mnd_width = 16,
 619         .hid_width = 5,
 620         .parent_map = gcc_parent_map_3,
 621         .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
 622         .clkr.hw.init = &(struct clk_init_data){
 623                 .name = "gcc_usb3_phy_aux_clk_src",
 624                 .parent_data = gcc_parent_data_3,
 625                 .num_parents = 2,
 626                 .flags = CLK_SET_RATE_PARENT,
 627                 .ops = &clk_rcg2_ops,
 628         },
 629 };
 630
 631 static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
 632         .reg = 0x30024,
 633         .shift = 0,
 634         .width = 4,
 635         .clkr.hw.init = &(struct clk_init_data) {
 636                 .name = "gcc_cpuss_ahb_postdiv_clk_src",
 637                 .parent_hws = (const struct clk_hw*[]) {
 638                         &gcc_cpuss_ahb_clk_src.clkr.hw,
 639                 },
 640                 .num_parents = 1,
 641                 .flags = CLK_SET_RATE_PARENT,
 642                 .ops = &clk_regmap_div_ro_ops,
 643         },
 644 };
 645
 646 static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = {
 647         .reg = 0x17060,
 648         .shift = 0,
 649         .width = 4,
 650         .clkr.hw.init = &(struct clk_init_data) {
 651                 .name = "gcc_usb30_mock_utmi_postdiv_clk_src",
 652                 .parent_hws = (const struct clk_hw*[]) {
 653                         &gcc_usb30_mock_utmi_clk_src.clkr.hw,
 654                 },
 655                 .num_parents = 1,
 656                 .flags = CLK_SET_RATE_PARENT,
 657                 .ops = &clk_regmap_div_ro_ops,
 658         },
 659 };
 660
 661 static struct clk_branch gcc_ahb_pcie_link_clk = {
 662         .halt_reg = 0x2e004,
 663         .halt_check = BRANCH_HALT,
 664         .clkr = {
 665                 .enable_reg = 0x2e004,
 666                 .enable_mask = BIT(0),
 667                 .hw.init = &(struct clk_init_data){
 668                         .name = "gcc_ahb_pcie_link_clk",
 669                         .ops = &clk_branch2_ops,
 670                 },
 671         },
 672 };
 673
 674 static struct clk_branch gcc_blsp1_ahb_clk = {
 675         .halt_reg = 0x1b004,
 676         .halt_check = BRANCH_HALT_VOTED,
 677         .clkr = {
 678                 .enable_reg = 0x6d008,
 679                 .enable_mask = BIT(14),
 680                 .hw.init = &(struct clk_init_data){
 681                         .name = "gcc_blsp1_ahb_clk",
 682                         .ops = &clk_branch2_ops,
 683                 },
 684         },
 685 };
 686
 687 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 688         .halt_reg = 0x1c008,
 689         .halt_check = BRANCH_HALT,
 690         .clkr = {
 691                 .enable_reg = 0x1c008,
 692                 .enable_mask = BIT(0),
 693                 .hw.init = &(struct clk_init_data){
 694                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
 695                         .parent_hws = (const struct clk_hw*[]) {
 696                                 &gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw,
 697                         },
 698                         .num_parents = 1,
 699                         .flags = CLK_SET_RATE_PARENT,
 700                         .ops = &clk_branch2_ops,
 701                 },
 702         },
 703 };
 704
 705 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 706         .halt_reg = 0x1c004,
 707         .halt_check = BRANCH_HALT,
 708         .clkr = {
 709                 .enable_reg = 0x1c004,
 710                 .enable_mask = BIT(0),
 711                 .hw.init = &(struct clk_init_data){
 712                         .name = "gcc_blsp1_qup1_spi_apps_clk",
 713                         .parent_hws = (const struct clk_hw*[]) {
 714                                 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
 715                         },
 716                         .num_parents = 1,
 717                         .flags = CLK_SET_RATE_PARENT,
 718                         .ops = &clk_branch2_ops,
 719                 },
 720         },
 721 };
 722
 723 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 724         .halt_reg = 0x1e008,
 725         .halt_check = BRANCH_HALT,
 726         .clkr = {
 727                 .enable_reg = 0x1e008,
 728                 .enable_mask = BIT(0),
 729                 .hw.init = &(struct clk_init_data){
 730                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
 731                         .parent_hws = (const struct clk_hw*[]) {
 732                                 &gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw,
 733                         },
 734                         .num_parents = 1,
 735                         .flags = CLK_SET_RATE_PARENT,
 736                         .ops = &clk_branch2_ops,
 737                 },
 738         },
 739 };
 740
 741 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 742         .halt_reg = 0x1e004,
 743         .halt_check = BRANCH_HALT,
 744         .clkr = {
 745                 .enable_reg = 0x1e004,
 746                 .enable_mask = BIT(0),
 747                 .hw.init = &(struct clk_init_data){
 748                         .name = "gcc_blsp1_qup2_spi_apps_clk",
 749                         .parent_hws = (const struct clk_hw*[]) {
 750                                 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
 751                         },
 752                         .num_parents = 1,
 753                         .flags = CLK_SET_RATE_PARENT,
 754                         .ops = &clk_branch2_ops,
 755                 },
 756         },
 757 };
 758
 759 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
 760         .halt_reg = 0x20008,
 761         .halt_check = BRANCH_HALT,
 762         .clkr = {
 763                 .enable_reg = 0x20008,
 764                 .enable_mask = BIT(0),
 765                 .hw.init = &(struct clk_init_data){
 766                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
 767                         .parent_hws = (const struct clk_hw*[]) {
 768                                 &gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw,
 769                         },
 770                         .num_parents = 1,
 771                         .flags = CLK_SET_RATE_PARENT,
 772                         .ops = &clk_branch2_ops,
 773                 },
 774         },
 775 };
 776
 777 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
 778         .halt_reg = 0x20004,
 779         .halt_check = BRANCH_HALT,
 780         .clkr = {
 781                 .enable_reg = 0x20004,
 782                 .enable_mask = BIT(0),
 783                 .hw.init = &(struct clk_init_data){
 784                         .name = "gcc_blsp1_qup3_spi_apps_clk",
 785                         .parent_hws = (const struct clk_hw*[]) {
 786                                 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
 787                         },
 788                         .num_parents = 1,
 789                         .flags = CLK_SET_RATE_PARENT,
 790                         .ops = &clk_branch2_ops,
 791                 },
 792         },
 793 };
 794
 795 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
 796         .halt_reg = 0x22008,
 797         .halt_check = BRANCH_HALT,
 798         .clkr = {
 799                 .enable_reg = 0x22008,
 800                 .enable_mask = BIT(0),
 801                 .hw.init = &(struct clk_init_data){
 802                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
 803                         .parent_hws = (const struct clk_hw*[]) {
 804                                 &gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw,
 805                         },
 806                         .num_parents = 1,
 807                         .flags = CLK_SET_RATE_PARENT,
 808                         .ops = &clk_branch2_ops,
 809                 },
 810         },
 811 };
 812
 813 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
 814         .halt_reg = 0x22004,
 815         .halt_check = BRANCH_HALT,
 816         .clkr = {
 817                 .enable_reg = 0x22004,
 818                 .enable_mask = BIT(0),
 819                 .hw.init = &(struct clk_init_data){
 820                         .name = "gcc_blsp1_qup4_spi_apps_clk",
 821                         .parent_hws = (const struct clk_hw*[]) {
 822                                 &gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw,
 823                         },
 824                         .num_parents = 1,
 825                         .flags = CLK_SET_RATE_PARENT,
 826                         .ops = &clk_branch2_ops,
 827                 },
 828         },
 829 };
 830
 831 static struct clk_branch gcc_blsp1_sleep_clk = {
 832         .halt_reg = 0x1b00c,
 833         .halt_check = BRANCH_HALT_VOTED,
 834         .clkr = {
 835                 .enable_reg = 0x6d008,
 836                 .enable_mask = BIT(15),
 837                 .hw.init = &(struct clk_init_data){
 838                         .name = "gcc_blsp1_sleep_clk",
 839                         .ops = &clk_branch2_ops,
 840                 },
 841         },
 842 };
 843
 844 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
 845         .halt_reg = 0x1d004,
 846         .halt_check = BRANCH_HALT,
 847         .clkr = {
 848                 .enable_reg = 0x1d004,
 849                 .enable_mask = BIT(0),
 850                 .hw.init = &(struct clk_init_data){
 851                         .name = "gcc_blsp1_uart1_apps_clk",
 852                         .parent_hws = (const struct clk_hw*[]) {
 853                                 &gcc_blsp1_uart1_apps_clk_src.clkr.hw,
 854                         },
 855                         .num_parents = 1,
 856                         .flags = CLK_SET_RATE_PARENT,
 857                         .ops = &clk_branch2_ops,
 858                 },
 859         },
 860 };
 861
 862 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 863         .halt_reg = 0x1f004,
 864         .halt_check = BRANCH_HALT,
 865         .clkr = {
 866                 .enable_reg = 0x1f004,
 867                 .enable_mask = BIT(0),
 868                 .hw.init = &(struct clk_init_data){
 869                         .name = "gcc_blsp1_uart2_apps_clk",
 870                         .parent_hws = (const struct clk_hw*[]) {
 871                                 &gcc_blsp1_uart2_apps_clk_src.clkr.hw,
 872                         },
 873                         .num_parents = 1,
 874                         .flags = CLK_SET_RATE_PARENT,
 875                         .ops = &clk_branch2_ops,
 876                 },
 877         },
 878 };
 879
 880 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
 881         .halt_reg = 0x21004,
 882         .halt_check = BRANCH_HALT,
 883         .clkr = {
 884                 .enable_reg = 0x21004,
 885                 .enable_mask = BIT(0),
 886                 .hw.init = &(struct clk_init_data){
 887                         .name = "gcc_blsp1_uart3_apps_clk",
 888                         .parent_hws = (const struct clk_hw*[]) {
 889                                 &gcc_blsp1_uart3_apps_clk_src.clkr.hw,
 890                         },
 891                         .num_parents = 1,
 892                         .flags = CLK_SET_RATE_PARENT,
 893                         .ops = &clk_branch2_ops,
 894                 },
 895         },
 896 };
 897
 898 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
 899         .halt_reg = 0x23004,
 900         .halt_check = BRANCH_HALT,
 901         .clkr = {
 902                 .enable_reg = 0x23004,
 903                 .enable_mask = BIT(0),
 904                 .hw.init = &(struct clk_init_data){
 905                         .name = "gcc_blsp1_uart4_apps_clk",
 906                         .parent_hws = (const struct clk_hw*[]) {
 907                                 &gcc_blsp1_uart4_apps_clk_src.clkr.hw,
 908                         },
 909                         .num_parents = 1,
 910                         .flags = CLK_SET_RATE_PARENT,
 911                         .ops = &clk_branch2_ops,
 912                 },
 913         },
 914 };
 915
 916 static struct clk_branch gcc_boot_rom_ahb_clk = {
 917         .halt_reg = 0x27004,
 918         .halt_check = BRANCH_HALT_VOTED,
 919         .hwcg_reg = 0x27004,
 920         .hwcg_bit = 1,
 921         .clkr = {
 922                 .enable_reg = 0x6d008,
 923                 .enable_mask = BIT(10),
 924                 .hw.init = &(struct clk_init_data){
 925                         .name = "gcc_boot_rom_ahb_clk",
 926                         .ops = &clk_branch2_ops,
 927                 },
 928         },
 929 };
 930
 931 static struct clk_branch gcc_gp1_clk = {
 932         .halt_reg = 0x37000,
 933         .halt_check = BRANCH_HALT,
 934         .clkr = {
 935                 .enable_reg = 0x37000,
 936                 .enable_mask = BIT(0),
 937                 .hw.init = &(struct clk_init_data){
 938                         .name = "gcc_gp1_clk",
 939                         .parent_hws = (const struct clk_hw*[]) {
 940                                 &gcc_gp1_clk_src.clkr.hw,
 941                         },
 942                         .num_parents = 1,
 943                         .flags = CLK_SET_RATE_PARENT,
 944                         .ops = &clk_branch2_ops,
 945                 },
 946         },
 947 };
 948
 949 static struct clk_branch gcc_gp2_clk = {
 950         .halt_reg = 0x38000,
 951         .halt_check = BRANCH_HALT,
 952         .clkr = {
 953                 .enable_reg = 0x38000,
 954                 .enable_mask = BIT(0),
 955                 .hw.init = &(struct clk_init_data){
 956                         .name = "gcc_gp2_clk",
 957                         .parent_hws = (const struct clk_hw*[]) {
 958                                 &gcc_gp2_clk_src.clkr.hw,
 959                         },
 960                         .num_parents = 1,
 961                         .flags = CLK_SET_RATE_PARENT,
 962                         .ops = &clk_branch2_ops,
 963                 },
 964         },
 965 };
 966
 967 static struct clk_branch gcc_gp3_clk = {
 968         .halt_reg = 0x39000,
 969         .halt_check = BRANCH_HALT,
 970         .clkr = {
 971                 .enable_reg = 0x39000,
 972                 .enable_mask = BIT(0),
 973                 .hw.init = &(struct clk_init_data){
 974                         .name = "gcc_gp3_clk",
 975                         .parent_hws = (const struct clk_hw*[]) {
 976                                 &gcc_gp3_clk_src.clkr.hw,
 977                         },
 978                         .num_parents = 1,
 979                         .flags = CLK_SET_RATE_PARENT,
 980                         .ops = &clk_branch2_ops,
 981                 },
 982         },
 983 };
 984
 985 static struct clk_branch gcc_pcie_0_clkref_en = {
 986         .halt_reg = 0x88004,
 987         /*
 988          * The clock controller does not handle the status bit for
 989          * the clocks with gdscs(powerdomains) in hw controlled mode
 990          * and hence avoid checking for the status bit of those clocks
 991          * by setting the BRANCH_HALT_DELAY flag
 992          */
 993         .halt_check = BRANCH_HALT_DELAY,
 994         .clkr = {
 995                 .enable_reg = 0x88004,
 996                 .enable_mask = BIT(0),
 997                 .hw.init = &(struct clk_init_data){
 998                         .name = "gcc_pcie_0_clkref_en",
 999                         .ops = &clk_branch2_ops,
1000                 },
1001         },
1002 };
1003
1004 static struct clk_branch gcc_pcie_aux_clk = {
1005         .halt_reg = 0x43034,
1006         /*
1007          * The clock controller does not handle the status bit for
1008          * the clocks with gdscs(powerdomains) in hw controlled mode
1009          * and hence avoid checking for the status bit of those clocks
1010          * by setting the BRANCH_HALT_DELAY flag
1011          */
1012         .halt_check = BRANCH_HALT_DELAY,
1013         .hwcg_reg = 0x43034,
1014         .hwcg_bit = 1,
1015         .clkr = {
1016                 .enable_reg = 0x6d010,
1017                 .enable_mask = BIT(3),
1018                 .hw.init = &(struct clk_init_data){
1019                         .name = "gcc_pcie_aux_clk",
1020                         .parent_hws = (const struct clk_hw*[]) {
1021                                 &gcc_pcie_aux_clk_src.clkr.hw,
1022                         },
1023                         .num_parents = 1,
1024                         .flags = CLK_SET_RATE_PARENT,
1025                         .ops = &clk_branch2_ops,
1026                 },
1027         },
1028 };
1029
1030 static struct clk_branch gcc_pcie_cfg_ahb_clk = {
1031         .halt_reg = 0x4302c,
1032         .halt_check = BRANCH_HALT_VOTED,
1033         .hwcg_reg = 0x4302c,
1034         .hwcg_bit = 1,
1035         .clkr = {
1036                 .enable_reg = 0x6d010,
1037                 .enable_mask = BIT(2),
1038                 .hw.init = &(struct clk_init_data){
1039                         .name = "gcc_pcie_cfg_ahb_clk",
1040                         .ops = &clk_branch2_ops,
1041                 },
1042         },
1043 };
1044
1045 static struct clk_branch gcc_pcie_mstr_axi_clk = {
1046         .halt_reg = 0x43024,
1047         .halt_check = BRANCH_HALT_VOTED,
1048         .hwcg_reg = 0x43024,
1049         .hwcg_bit = 1,
1050         .clkr = {
1051                 .enable_reg = 0x6d010,
1052                 .enable_mask = BIT(1),
1053                 .hw.init = &(struct clk_init_data){
1054                         .name = "gcc_pcie_mstr_axi_clk",
1055                         .ops = &clk_branch2_ops,
1056                 },
1057         },
1058 };
1059
1060 static struct clk_branch gcc_pcie_pipe_clk = {
1061         .halt_reg = 0x4303c,
1062         /*
1063          * The clock controller does not handle the status bit for
1064          * the clocks with gdscs(powerdomains) in hw controlled mode
1065          * and hence avoid checking for the status bit of those clocks
1066          * by setting the BRANCH_HALT_DELAY flag
1067          */
1068         .halt_check = BRANCH_HALT_DELAY,
1069         .hwcg_reg = 0x4303c,
1070         .hwcg_bit = 1,
1071         .clkr = {
1072                 .enable_reg = 0x6d010,
1073                 .enable_mask = BIT(4),
1074                 .hw.init = &(struct clk_init_data){
1075                         .name = "gcc_pcie_pipe_clk",
1076                         .parent_hws = (const struct clk_hw*[]) {
1077                                 &gcc_pcie_pipe_clk_src.clkr.hw,
1078                         },
1079                         .num_parents = 1,
1080                         .flags = CLK_SET_RATE_PARENT,
1081                         .ops = &clk_branch2_ops,
1082                 },
1083         },
1084 };
1085
1086 static struct clk_branch gcc_pcie_rchng_phy_clk = {
1087         .halt_reg = 0x43030,
1088         .halt_check = BRANCH_HALT_VOTED,
1089         .hwcg_reg = 0x43030,
1090         .hwcg_bit = 1,
1091         .clkr = {
1092                 .enable_reg = 0x6d010,
1093                 .enable_mask = BIT(7),
1094                 .hw.init = &(struct clk_init_data){
1095                         .name = "gcc_pcie_rchng_phy_clk",
1096                         .parent_hws = (const struct clk_hw*[]) {
1097                                 &gcc_pcie_rchng_phy_clk_src.clkr.hw,
1098                         },
1099                         .num_parents = 1,
1100                         .flags = CLK_SET_RATE_PARENT,
1101                         .ops = &clk_branch2_ops,
1102                 },
1103         },
1104 };
1105
1106 static struct clk_branch gcc_pcie_sleep_clk = {
1107         .halt_reg = 0x43038,
1108         .halt_check = BRANCH_HALT_VOTED,
1109         .hwcg_reg = 0x43038,
1110         .hwcg_bit = 1,
1111         .clkr = {
1112                 .enable_reg = 0x6d010,
1113                 .enable_mask = BIT(6),
1114                 .hw.init = &(struct clk_init_data){
1115                         .name = "gcc_pcie_sleep_clk",
1116                         .parent_hws = (const struct clk_hw*[]) {
1117                                 &gcc_pcie_aux_phy_clk_src.clkr.hw,
1118                         },
1119                         .num_parents = 1,
1120                         .flags = CLK_SET_RATE_PARENT,
1121                         .ops = &clk_branch2_ops,
1122                 },
1123         },
1124 };
1125
1126 static struct clk_branch gcc_pcie_slv_axi_clk = {
1127         .halt_reg = 0x4301c,
1128         .halt_check = BRANCH_HALT_VOTED,
1129         .hwcg_reg = 0x4301c,
1130         .hwcg_bit = 1,
1131         .clkr = {
1132                 .enable_reg = 0x6d010,
1133                 .enable_mask = BIT(0),
1134                 .hw.init = &(struct clk_init_data){
1135                         .name = "gcc_pcie_slv_axi_clk",
1136                         .ops = &clk_branch2_ops,
1137                 },
1138         },
1139 };
1140
1141 static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
1142         .halt_reg = 0x43018,
1143         .halt_check = BRANCH_HALT_VOTED,
1144         .hwcg_reg = 0x43018,
1145         .hwcg_bit = 1,
1146         .clkr = {
1147                 .enable_reg = 0x6d010,
1148                 .enable_mask = BIT(5),
1149                 .hw.init = &(struct clk_init_data){
1150                         .name = "gcc_pcie_slv_q2a_axi_clk",
1151                         .ops = &clk_branch2_ops,
1152                 },
1153         },
1154 };
1155
1156 static struct clk_branch gcc_pdm2_clk = {
1157         .halt_reg = 0x2400c,
1158         .halt_check = BRANCH_HALT,
1159         .clkr = {
1160                 .enable_reg = 0x2400c,
1161                 .enable_mask = BIT(0),
1162                 .hw.init = &(struct clk_init_data){
1163                         .name = "gcc_pdm2_clk",
1164                         .parent_hws = (const struct clk_hw*[]) {
1165                                 &gcc_pdm2_clk_src.clkr.hw,
1166                         },
1167                         .num_parents = 1,
1168                         .flags = CLK_SET_RATE_PARENT,
1169                         .ops = &clk_branch2_ops,
1170                 },
1171         },
1172 };
1173
1174 static struct clk_branch gcc_pdm_ahb_clk = {
1175         .halt_reg = 0x24004,
1176         .halt_check = BRANCH_HALT,
1177         .hwcg_reg = 0x24004,
1178         .hwcg_bit = 1,
1179         .clkr = {
1180                 .enable_reg = 0x24004,
1181                 .enable_mask = BIT(0),
1182                 .hw.init = &(struct clk_init_data){
1183                         .name = "gcc_pdm_ahb_clk",
1184                         .ops = &clk_branch2_ops,
1185                 },
1186         },
1187 };
1188
1189 static struct clk_branch gcc_pdm_xo4_clk = {
1190         .halt_reg = 0x24008,
1191         .halt_check = BRANCH_HALT,
1192         .clkr = {
1193                 .enable_reg = 0x24008,
1194                 .enable_mask = BIT(0),
1195                 .hw.init = &(struct clk_init_data){
1196                         .name = "gcc_pdm_xo4_clk",
1197                         .ops = &clk_branch2_ops,
1198                 },
1199         },
1200 };
1201
1202 static struct clk_branch gcc_rx1_usb2_clkref_en = {
1203         .halt_reg = 0x88008,
1204         .halt_check = BRANCH_HALT,
1205         .clkr = {
1206                 .enable_reg = 0x88008,
1207                 .enable_mask = BIT(0),
1208                 .hw.init = &(struct clk_init_data){
1209                         .name = "gcc_rx1_usb2_clkref_en",
1210                         .ops = &clk_branch2_ops,
1211                 },
1212         },
1213 };
1214
1215 static struct clk_branch gcc_sdcc1_ahb_clk = {
1216         .halt_reg = 0x1a00c,
1217         .halt_check = BRANCH_HALT,
1218         .clkr = {
1219                 .enable_reg = 0x1a00c,
1220                 .enable_mask = BIT(0),
1221                 .hw.init = &(struct clk_init_data){
1222                         .name = "gcc_sdcc1_ahb_clk",
1223                         .ops = &clk_branch2_ops,
1224                 },
1225         },
1226 };
1227
1228 static struct clk_branch gcc_sdcc1_apps_clk = {
1229         .halt_reg = 0x1a004,
1230         .halt_check = BRANCH_HALT,
1231         .clkr = {
1232                 .enable_reg = 0x1a004,
1233                 .enable_mask = BIT(0),
1234                 .hw.init = &(struct clk_init_data){
1235                         .name = "gcc_sdcc1_apps_clk",
1236                         .parent_hws = (const struct clk_hw*[]) {
1237                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
1238                         },
1239                         .num_parents = 1,
1240                         .flags = CLK_SET_RATE_PARENT,
1241                         .ops = &clk_branch2_ops,
1242                 },
1243         },
1244 };
1245
1246 static struct clk_branch gcc_usb30_master_clk = {
1247         .halt_reg = 0x17018,
1248         .halt_check = BRANCH_HALT,
1249         .clkr = {
1250                 .enable_reg = 0x17018,
1251                 .enable_mask = BIT(0),
1252                 .hw.init = &(struct clk_init_data){
1253                         .name = "gcc_usb30_master_clk",
1254                         .parent_hws = (const struct clk_hw*[]) {
1255                                 &gcc_usb30_master_clk_src.clkr.hw,
1256                         },
1257                         .num_parents = 1,
1258                         .flags = CLK_SET_RATE_PARENT,
1259                         .ops = &clk_branch2_ops,
1260                 },
1261         },
1262 };
1263
1264 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1265         .halt_reg = 0x1702c,
1266         .halt_check = BRANCH_HALT,
1267         .clkr = {
1268                 .enable_reg = 0x1702c,
1269                 .enable_mask = BIT(0),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "gcc_usb30_mock_utmi_clk",
1272                         .parent_hws = (const struct clk_hw*[]) {
1273                                 &gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,
1274                         },
1275                         .num_parents = 1,
1276                         .flags = CLK_SET_RATE_PARENT,
1277                         .ops = &clk_branch2_ops,
1278                 },
1279         },
1280 };
1281
1282 static struct clk_branch gcc_usb30_mstr_axi_clk = {
1283         .halt_reg = 0x17020,
1284         .halt_check = BRANCH_HALT,
1285         .clkr = {
1286                 .enable_reg = 0x17020,
1287                 .enable_mask = BIT(0),
1288                 .hw.init = &(struct clk_init_data){
1289                         .name = "gcc_usb30_mstr_axi_clk",
1290                         .ops = &clk_branch2_ops,
1291                 },
1292         },
1293 };
1294
1295 static struct clk_branch gcc_usb30_sleep_clk = {
1296         .halt_reg = 0x17028,
1297         .halt_check = BRANCH_HALT,
1298         .clkr = {
1299                 .enable_reg = 0x17028,
1300                 .enable_mask = BIT(0),
1301                 .hw.init = &(struct clk_init_data){
1302                         .name = "gcc_usb30_sleep_clk",
1303                         .ops = &clk_branch2_ops,
1304                 },
1305         },
1306 };
1307
1308 static struct clk_branch gcc_usb30_slv_ahb_clk = {
1309         .halt_reg = 0x17024,
1310         .halt_check = BRANCH_HALT,
1311         .clkr = {
1312                 .enable_reg = 0x17024,
1313                 .enable_mask = BIT(0),
1314                 .hw.init = &(struct clk_init_data){
1315                         .name = "gcc_usb30_slv_ahb_clk",
1316                         .ops = &clk_branch2_ops,
1317                 },
1318         },
1319 };
1320
1321 static struct clk_branch gcc_usb3_phy_aux_clk = {
1322         .halt_reg = 0x17064,
1323         .halt_check = BRANCH_HALT,
1324         .clkr = {
1325                 .enable_reg = 0x17064,
1326                 .enable_mask = BIT(0),
1327                 .hw.init = &(struct clk_init_data){
1328                         .name = "gcc_usb3_phy_aux_clk",
1329                         .parent_hws = (const struct clk_hw*[]) {
1330                                 &gcc_usb3_phy_aux_clk_src.clkr.hw,
1331                         },
1332                         .num_parents = 1,
1333                         .flags = CLK_SET_RATE_PARENT,
1334                         .ops = &clk_branch2_ops,
1335                 },
1336         },
1337 };
1338
1339 static struct gdsc usb30_gdsc = {
1340         .gdscr = 0x17004,
1341         .pd = {
1342                 .name = "usb30_gdsc",
1343         },
1344         .pwrsts = PWRSTS_OFF_ON,
1345 };
1346
1347 static struct gdsc pcie_gdsc = {
1348         .gdscr = 0x43004,
1349         .pd = {
1350                 .name = "pcie_gdsc",
1351         },
1352         .pwrsts = PWRSTS_OFF_ON,
1353 };
1354
1355 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1356         .halt_reg = 0x17068,
1357         /*
1358          * The clock controller does not handle the status bit for
1359          * the clocks with gdscs(powerdomains) in hw controlled mode
1360          * and hence avoid checking for the status bit of those clocks
1361          * by setting the BRANCH_HALT_DELAY flag
1362          */
1363         .halt_check = BRANCH_HALT_DELAY,
1364         .hwcg_reg = 0x17068,
1365         .hwcg_bit = 1,
1366         .clkr = {
1367                 .enable_reg = 0x17068,
1368                 .enable_mask = BIT(0),
1369                 .hw.init = &(struct clk_init_data){
1370                         .name = "gcc_usb3_phy_pipe_clk",
1371                         .parent_hws = (const struct clk_hw*[]) {
1372                                 &gcc_usb3_phy_pipe_clk_src.clkr.hw,
1373                         },
1374                         .num_parents = 1,
1375                         .flags = CLK_SET_RATE_PARENT,
1376                         .ops = &clk_branch2_ops,
1377                 },
1378         },
1379 };
1380
1381 static struct clk_branch gcc_usb3_prim_clkref_en = {
1382         .halt_reg = 0x88000,
1383         .halt_check = BRANCH_HALT,
1384         .clkr = {
1385                 .enable_reg = 0x88000,
1386                 .enable_mask = BIT(0),
1387                 .hw.init = &(struct clk_init_data){
1388                         .name = "gcc_usb3_prim_clkref_en",
1389                         .ops = &clk_branch2_ops,
1390                 },
1391         },
1392 };
1393
1394 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1395         .halt_reg = 0x19008,
1396         .halt_check = BRANCH_HALT,
1397         .hwcg_reg = 0x19008,
1398         .hwcg_bit = 1,
1399         .clkr = {
1400                 .enable_reg = 0x19008,
1401                 .enable_mask = BIT(0),
1402                 .hw.init = &(struct clk_init_data){
1403                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1404                         .ops = &clk_branch2_ops,
1405                 },
1406         },
1407 };
1408
1409 static struct clk_branch gcc_xo_div4_clk = {
1410         .halt_reg = 0x2e010,
1411         .halt_check = BRANCH_HALT,
1412         .clkr = {
1413                 .enable_reg = 0x2e010,
1414                 .enable_mask = BIT(0),
1415                 .hw.init = &(struct clk_init_data){
1416                         .name = "gcc_xo_div4_clk",
1417                         .ops = &clk_branch2_ops,
1418                 },
1419         },
1420 };
1421
1422 static struct clk_branch gcc_xo_pcie_link_clk = {
1423         .halt_reg = 0x2e008,
1424         .halt_check = BRANCH_HALT,
1425         .hwcg_reg = 0x2e008,
1426         .hwcg_bit = 1,
1427         .clkr = {
1428                 .enable_reg = 0x2e008,
1429                 .enable_mask = BIT(0),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "gcc_xo_pcie_link_clk",
1432                         .ops = &clk_branch2_ops,
1433                 },
1434         },
1435 };
1436
1437 static struct clk_regmap *gcc_sdx65_clocks[] = {
1438         [GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
1439         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1440         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1441         [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup1_i2c_apps_clk_src.clkr,
1442         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1443         [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
1444         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1445         [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup2_i2c_apps_clk_src.clkr,
1446         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1447         [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
1448         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
1449         [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup3_i2c_apps_clk_src.clkr,
1450         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
1451         [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
1452         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
1453         [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup4_i2c_apps_clk_src.clkr,
1454         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
1455         [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup4_spi_apps_clk_src.clkr,
1456         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
1457         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1458         [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
1459         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1460         [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
1461         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
1462         [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
1463         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
1464         [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr,
1465         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1466         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
1467         [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
1468         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1469         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
1470         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1471         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
1472         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1473         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
1474         [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
1475         [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
1476         [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
1477         [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
1478         [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
1479         [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
1480         [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
1481         [GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr,
1482         [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
1483         [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
1484         [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
1485         [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
1486         [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
1487         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
1488         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
1489         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
1490         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
1491         [GCC_RX1_USB2_CLKREF_EN] = &gcc_rx1_usb2_clkref_en.clkr,
1492         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1493         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1494         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
1495         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
1496         [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
1497         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
1498         [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
1499         [GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr,
1500         [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
1501         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
1502         [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
1503         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
1504         [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
1505         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
1506         [GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr,
1507         [GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr,
1508         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
1509         [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
1510         [GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr,
1511         [GPLL0] = &gpll0.clkr,
1512         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
1513 };
1514
1515 static const struct qcom_reset_map gcc_sdx65_resets[] = {
1516         [GCC_BLSP1_QUP1_BCR] = { 0x1c000 },
1517         [GCC_BLSP1_QUP2_BCR] = { 0x1e000 },
1518         [GCC_BLSP1_QUP3_BCR] = { 0x20000 },
1519         [GCC_BLSP1_QUP4_BCR] = { 0x22000 },
1520         [GCC_BLSP1_UART1_BCR] = { 0x1d000 },
1521         [GCC_BLSP1_UART2_BCR] = { 0x1f000 },
1522         [GCC_BLSP1_UART3_BCR] = { 0x21000 },
1523         [GCC_BLSP1_UART4_BCR] = { 0x23000 },
1524         [GCC_PCIE_BCR] = { 0x43000 },
1525         [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
1526         [GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x78008 },
1527         [GCC_PCIE_PHY_BCR] = { 0x44000 },
1528         [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x78000 },
1529         [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
1530         [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x7800c },
1531         [GCC_PDM_BCR] = { 0x24000 },
1532         [GCC_QUSB2PHY_BCR] = { 0x19000 },
1533         [GCC_SDCC1_BCR] = { 0x1a000 },
1534         [GCC_TCSR_PCIE_BCR] = { 0x57000 },
1535         [GCC_USB30_BCR] = { 0x17000 },
1536         [GCC_USB3_PHY_BCR] = { 0x18000 },
1537         [GCC_USB3PHY_PHY_BCR] = { 0x18004 },
1538         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x19004 },
1539 };
1540
1541 static struct gdsc *gcc_sdx65_gdscs[] = {
1542         [USB30_GDSC] = &usb30_gdsc,
1543         [PCIE_GDSC] = &pcie_gdsc,
1544 };
1545
1546 static const struct regmap_config gcc_sdx65_regmap_config = {
1547         .reg_bits = 32,
1548         .reg_stride = 4,
1549         .val_bits = 32,
1550         .max_register = 0x1f101c,
1551         .fast_io = true,
1552 };
1553
1554 static const struct qcom_cc_desc gcc_sdx65_desc = {
1555         .config = &gcc_sdx65_regmap_config,
1556         .clks = gcc_sdx65_clocks,
1557         .num_clks = ARRAY_SIZE(gcc_sdx65_clocks),
1558         .resets = gcc_sdx65_resets,
1559         .num_resets = ARRAY_SIZE(gcc_sdx65_resets),
1560         .gdscs = gcc_sdx65_gdscs,
1561         .num_gdscs = ARRAY_SIZE(gcc_sdx65_gdscs),
1562 };
1563
1564 static const struct of_device_id gcc_sdx65_match_table[] = {
1565         { .compatible = "qcom,gcc-sdx65" },
1566         { }
1567 };
1568 MODULE_DEVICE_TABLE(of, gcc_sdx65_match_table);
1569
1570 static int gcc_sdx65_probe(struct platform_device *pdev)
1571 {
1572         struct regmap *regmap;
1573
1574         regmap = qcom_cc_map(pdev, &gcc_sdx65_desc);
1575         if (IS_ERR(regmap))
1576                 return PTR_ERR(regmap);
1577
1578         /* Keep some clocks always-on */
1579         qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */
1580         regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */
1581         regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */
1582
1583         return qcom_cc_really_probe(&pdev->dev, &gcc_sdx65_desc, regmap);
1584 }
1585
1586 static struct platform_driver gcc_sdx65_driver = {
1587         .probe = gcc_sdx65_probe,
1588         .driver = {
1589                 .name = "gcc-sdx65",
1590                 .of_match_table = gcc_sdx65_match_table,
1591         },
1592 };
1593
1594 static int __init gcc_sdx65_init(void)
1595 {
1596         return platform_driver_register(&gcc_sdx65_driver);
1597 }
1598 subsys_initcall(gcc_sdx65_init);
1599
1600 static void __exit gcc_sdx65_exit(void)
1601 {
1602         platform_driver_unregister(&gcc_sdx65_driver);
1603 }
1604 module_exit(gcc_sdx65_exit);
1605
1606 MODULE_DESCRIPTION("QTI GCC SDX65 Driver");
1607 MODULE_LICENSE("GPL v2");