drivers/clk/qcom/gdsc.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef __QCOM_GDSC_H__
   7 #define __QCOM_GDSC_H__
   8
   9 #include <linux/err.h>
  10 #include <linux/pm_domain.h>
  11
  12 struct regmap;
  13 struct regulator;
  14 struct reset_controller_dev;
  15
  16 /**
  17  * struct gdsc - Globally Distributed Switch Controller
  18  * @pd: generic power domain
  19  * @regmap: regmap for MMIO accesses
  20  * @gdscr: gsdc control register
  21  * @collapse_ctrl: APCS collapse-vote register
  22  * @collapse_mask: APCS collapse-vote mask
  23  * @gds_hw_ctrl: gds_hw_ctrl register
  24  * @cxcs: offsets of branch registers to toggle mem/periph bits in
  25  * @cxc_count: number of @cxcs
  26  * @pwrsts: Possible powerdomain power states
  27  * @en_rest_wait_val: transition delay value for receiving enr ack signal
  28  * @en_few_wait_val: transition delay value for receiving enf ack signal
  29  * @clk_dis_wait_val: transition delay value for halting clock
  30  * @resets: ids of resets associated with this gdsc
  31  * @reset_count: number of @resets
  32  * @rcdev: reset controller
  33  */
  34 struct gdsc {
  35         struct generic_pm_domain        pd;
  36         struct generic_pm_domain        *parent;
  37         struct regmap                   *regmap;
  38         unsigned int                    gdscr;
  39         unsigned int                    collapse_ctrl;
  40         unsigned int                    collapse_mask;
  41         unsigned int                    gds_hw_ctrl;
  42         unsigned int                    clamp_io_ctrl;
  43         unsigned int                    *cxcs;
  44         unsigned int                    cxc_count;
  45         unsigned int                    en_rest_wait_val;
  46         unsigned int                    en_few_wait_val;
  47         unsigned int                    clk_dis_wait_val;
  48         const u8                        pwrsts;
  49 /* Powerdomain allowable state bitfields */
  50 #define PWRSTS_OFF              BIT(0)
  51 /*
  52  * There is no SW control to transition a GDSC into
  53  * PWRSTS_RET. This happens in HW when the parent
  54  * domain goes down to a low power state
  55  */
  56 #define PWRSTS_RET              BIT(1)
  57 #define PWRSTS_ON               BIT(2)
  58 #define PWRSTS_OFF_ON           (PWRSTS_OFF | PWRSTS_ON)
  59 #define PWRSTS_RET_ON           (PWRSTS_RET | PWRSTS_ON)
  60         const u16                       flags;
  61 #define VOTABLE         BIT(0)
  62 #define CLAMP_IO        BIT(1)
  63 #define HW_CTRL         BIT(2)
  64 #define SW_RESET        BIT(3)
  65 #define AON_RESET       BIT(4)
  66 #define POLL_CFG_GDSCR  BIT(5)
  67 #define ALWAYS_ON       BIT(6)
  68 #define RETAIN_FF_ENABLE        BIT(7)
  69 #define NO_RET_PERIPH   BIT(8)
  70 #define HW_CTRL_TRIGGER BIT(9)
  71         struct reset_controller_dev     *rcdev;
  72         unsigned int                    *resets;
  73         unsigned int                    reset_count;
  74
  75         const char                      *supply;
  76         struct regulator                *rsupply;
  77 };
  78
  79 struct gdsc_desc {
  80         struct device *dev;
  81         struct gdsc **scs;
  82         size_t num;
  83 };
  84
  85 #ifdef CONFIG_QCOM_GDSC
  86 int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
  87                   struct regmap *);
  88 void gdsc_unregister(struct gdsc_desc *desc);
  89 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
  90 #else
  91 static inline int gdsc_register(struct gdsc_desc *desc,
  92                                 struct reset_controller_dev *rcdev,
  93                                 struct regmap *r)
  94 {
  95         return -ENOSYS;
  96 }
  97
  98 static inline void gdsc_unregister(struct gdsc_desc *desc) {};
  99 #endif /* CONFIG_QCOM_GDSC */
 100 #endif /* __QCOM_GDSC_H__ */