1 // SPDX-License-Identifier: GPL-2.0
3 * EMMA Mobile EV2 common clock framework support
5 * Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
6 * Copyright (C) 2012 Magnus Damm
8 #include <linux/clk-provider.h>
11 #include <linux/of_address.h>
13 /* EMEV2 SMU registers */
14 #define USIAU0_RSTCTRL 0x094
15 #define USIBU1_RSTCTRL 0x0ac
16 #define USIBU2_RSTCTRL 0x0b0
17 #define USIBU3_RSTCTRL 0x0b4
18 #define IIC0_RSTCTRL 0x0dc
19 #define IIC1_RSTCTRL 0x0e0
20 #define STI_RSTCTRL 0x124
21 #define STI_CLKSEL 0x688
23 static DEFINE_SPINLOCK(lock
);
25 /* not pretty, but hey */
26 static void __iomem
*smu_base
;
28 static void __init
emev2_smu_write(unsigned long value
, int offs
)
30 BUG_ON(!smu_base
|| (offs
>= PAGE_SIZE
));
31 writel_relaxed(value
, smu_base
+ offs
);
34 static const struct of_device_id smu_id
[] __initconst
= {
35 { .compatible
= "renesas,emev2-smu", },
39 static void __init
emev2_smu_init(void)
41 struct device_node
*np
;
43 np
= of_find_matching_node(NULL
, smu_id
);
45 smu_base
= of_iomap(np
, 0);
49 /* setup STI timer to run on 32.768 kHz and deassert reset */
50 emev2_smu_write(0, STI_CLKSEL
);
51 emev2_smu_write(1, STI_RSTCTRL
);
53 /* deassert reset for UART0->UART3 */
54 emev2_smu_write(2, USIAU0_RSTCTRL
);
55 emev2_smu_write(2, USIBU1_RSTCTRL
);
56 emev2_smu_write(2, USIBU2_RSTCTRL
);
57 emev2_smu_write(2, USIBU3_RSTCTRL
);
59 /* deassert reset for IIC0->IIC1 */
60 emev2_smu_write(1, IIC0_RSTCTRL
);
61 emev2_smu_write(1, IIC1_RSTCTRL
);
64 static void __init
emev2_smu_clkdiv_init(struct device_node
*np
)
68 const char *parent_name
= of_clk_get_parent_name(np
, 0);
69 if (WARN_ON(of_property_read_u32_array(np
, "reg", reg
, 2)))
73 clk
= clk_register_divider(NULL
, np
->name
, parent_name
, 0,
74 smu_base
+ reg
[0], reg
[1], 8, 0, &lock
);
75 of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
76 pr_debug("## %s %pOFn %p\n", __func__
, np
, clk
);
78 CLK_OF_DECLARE(emev2_smu_clkdiv
, "renesas,emev2-smu-clkdiv",
79 emev2_smu_clkdiv_init
);
81 static void __init
emev2_smu_gclk_init(struct device_node
*np
)
85 const char *parent_name
= of_clk_get_parent_name(np
, 0);
86 if (WARN_ON(of_property_read_u32_array(np
, "reg", reg
, 2)))
90 clk
= clk_register_gate(NULL
, np
->name
, parent_name
, 0,
91 smu_base
+ reg
[0], reg
[1], 0, &lock
);
92 of_clk_add_provider(np
, of_clk_src_simple_get
, clk
);
93 pr_debug("## %s %pOFn %p\n", __func__
, np
, clk
);
95 CLK_OF_DECLARE(emev2_smu_gclk
, "renesas,emev2-smu-gclk", emev2_smu_gclk_init
);