drivers/clk/samsung/clk-pll.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   4  * Copyright (c) 2013 Linaro Ltd.
   5  *
   6  * Common Clock Framework support for all PLL's in Samsung platforms
   7 */
   8
   9 #ifndef __SAMSUNG_CLK_PLL_H
  10 #define __SAMSUNG_CLK_PLL_H
  11
  12 enum samsung_pll_type {
  13         pll_2126,
  14         pll_3000,
  15         pll_35xx,
  16         pll_36xx,
  17         pll_2550,
  18         pll_2650,
  19         pll_4500,
  20         pll_4502,
  21         pll_4508,
  22         pll_4600,
  23         pll_4650,
  24         pll_4650c,
  25         pll_6552,
  26         pll_6552_s3c2416,
  27         pll_6553,
  28         pll_2550x,
  29         pll_2550xx,
  30         pll_2650x,
  31         pll_2650xx,
  32         pll_1417x,
  33         pll_1418x,
  34         pll_1450x,
  35         pll_1451x,
  36         pll_1452x,
  37         pll_1460x,
  38         pll_0818x,
  39         pll_0822x,
  40         pll_0831x,
  41         pll_142xx,
  42         pll_0516x,
  43         pll_0517x,
  44         pll_0518x,
  45         pll_531x,
  46         pll_1051x,
  47         pll_1052x,
  48 };
  49
  50 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
  51         ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s)))
  52 #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \
  53         BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout)))
  54
  55 #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s)                  \
  56         {                                                       \
  57                 .rate   =       PLL_VALID_RATE(_fin, _rate,     \
  58                                 _m, _p, _s, 0, 16),             \
  59                 .mdiv   =       (_m),                           \
  60                 .pdiv   =       (_p),                           \
  61                 .sdiv   =       (_s),                           \
  62         }
  63
  64 #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k)              \
  65         {                                                       \
  66                 .rate   =       PLL_VALID_RATE(_fin, _rate,     \
  67                                 _m, _p, _s, _k, 16),            \
  68                 .mdiv   =       (_m),                           \
  69                 .pdiv   =       (_p),                           \
  70                 .sdiv   =       (_s),                           \
  71                 .kdiv   =       (_k),                           \
  72         }
  73
  74 #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc)            \
  75         {                                                       \
  76                 .rate   =       PLL_VALID_RATE(_fin, _rate,     \
  77                                 _m, _p, _s - 1, 0, 16),         \
  78                 .mdiv   =       (_m),                           \
  79                 .pdiv   =       (_p),                           \
  80                 .sdiv   =       (_s),                           \
  81                 .afc    =       (_afc),                         \
  82         }
  83
  84 #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel)       \
  85         {                                                       \
  86                 .rate   =       PLL_VALID_RATE(_fin, _rate,     \
  87                                 _m, _p, _s, _k, 16),            \
  88                 .mdiv   =       (_m),                           \
  89                 .pdiv   =       (_p),                           \
  90                 .sdiv   =       (_s),                           \
  91                 .kdiv   =       (_k),                           \
  92                 .vsel   =       (_vsel),                        \
  93         }
  94
  95 #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
  96         {                                                       \
  97                 .rate   =       PLL_VALID_RATE(_fin, _rate,     \
  98                                 _m, _p, _s, _k, 10),            \
  99                 .mdiv   =       (_m),                           \
 100                 .pdiv   =       (_p),                           \
 101                 .sdiv   =       (_s),                           \
 102                 .kdiv   =       (_k),                           \
 103                 .mfr    =       (_mfr),                         \
 104                 .mrr    =       (_mrr),                         \
 105                 .vsel   =       (_vsel),                        \
 106         }
 107
 108 /* NOTE: Rate table should be kept sorted in descending order. */
 109
 110 struct samsung_pll_rate_table {
 111         unsigned int rate;
 112         unsigned int pdiv;
 113         unsigned int mdiv;
 114         unsigned int sdiv;
 115         unsigned int kdiv;
 116         unsigned int afc;
 117         unsigned int mfr;
 118         unsigned int mrr;
 119         unsigned int vsel;
 120 };
 121
 122 #endif /* __SAMSUNG_CLK_PLL_H */