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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / cpufreq / amd-pstate.c
blobd7630bab2516f0a9c39a769864f5884046d597a8
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * amd-pstate.c - AMD Processor P-state Frequency Driver
4 *
5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved.
6 *
7 * Author: Huang Rui <ray.huang@amd.com>
8 *
9 * AMD P-State introduces a new CPU performance scaling design for AMD
10 * processors using the ACPI Collaborative Performance and Power Control (CPPC)
11 * feature which works with the AMD SMU firmware providing a finer grained
12 * frequency control range. It is to replace the legacy ACPI P-States control,
13 * allows a flexible, low-latency interface for the Linux kernel to directly
14 * communicate the performance hints to hardware.
15 *
16 * AMD P-State is supported on recent AMD Zen base CPU series include some of
17 * Zen2 and Zen3 processors. _CPC needs to be present in the ACPI tables of AMD
18 * P-State supported system. And there are two types of hardware implementations
19 * for AMD P-State: 1) Full MSR Solution and 2) Shared Memory Solution.
20 * X86_FEATURE_CPPC CPU feature flag is used to distinguish the different types.
21 */
22
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/smp.h>
29 #include <linux/sched.h>
30 #include <linux/cpufreq.h>
31 #include <linux/compiler.h>
32 #include <linux/dmi.h>
33 #include <linux/slab.h>
34 #include <linux/acpi.h>
35 #include <linux/io.h>
36 #include <linux/delay.h>
37 #include <linux/uaccess.h>
38 #include <linux/static_call.h>
39 #include <linux/topology.h>
40
41 #include <acpi/processor.h>
42 #include <acpi/cppc_acpi.h>
43
44 #include <asm/msr.h>
45 #include <asm/processor.h>
46 #include <asm/cpufeature.h>
47 #include <asm/cpu_device_id.h>
48
49 #include "amd-pstate.h"
50 #include "amd-pstate-trace.h"
51
52 #define AMD_PSTATE_TRANSITION_LATENCY 20000
53 #define AMD_PSTATE_TRANSITION_DELAY 1000
54 #define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600
55
56 #define AMD_CPPC_EPP_PERFORMANCE 0x00
57 #define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
58 #define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF
59 #define AMD_CPPC_EPP_POWERSAVE 0xFF
60
61 static const char * const amd_pstate_mode_string[] = {
62 [AMD_PSTATE_UNDEFINED] = "undefined",
63 [AMD_PSTATE_DISABLE] = "disable",
64 [AMD_PSTATE_PASSIVE] = "passive",
65 [AMD_PSTATE_ACTIVE] = "active",
66 [AMD_PSTATE_GUIDED] = "guided",
67 NULL,
68 };
69
70 const char *amd_pstate_get_mode_string(enum amd_pstate_mode mode)
71 {
72 if (mode < 0 || mode >= AMD_PSTATE_MAX)
73 return NULL;
74 return amd_pstate_mode_string[mode];
75 }
76 EXPORT_SYMBOL_GPL(amd_pstate_get_mode_string);
77
78 struct quirk_entry {
79 u32 nominal_freq;
80 u32 lowest_freq;
81 };
82
83 static struct cpufreq_driver *current_pstate_driver;
84 static struct cpufreq_driver amd_pstate_driver;
85 static struct cpufreq_driver amd_pstate_epp_driver;
86 static int cppc_state = AMD_PSTATE_UNDEFINED;
87 static bool cppc_enabled;
88 static bool amd_pstate_prefcore = true;
89 static struct quirk_entry *quirks;
90
91 /*
92 * AMD Energy Preference Performance (EPP)
93 * The EPP is used in the CCLK DPM controller to drive
94 * the frequency that a core is going to operate during
95 * short periods of activity. EPP values will be utilized for
96 * different OS profiles (balanced, performance, power savings)
97 * display strings corresponding to EPP index in the
98 * energy_perf_strings[]
99 * index String
100 *-------------------------------------
101 * 0 default
102 * 1 performance
103 * 2 balance_performance
104 * 3 balance_power
105 * 4 power
106 */
107 enum energy_perf_value_index {
108 EPP_INDEX_DEFAULT = 0,
109 EPP_INDEX_PERFORMANCE,
110 EPP_INDEX_BALANCE_PERFORMANCE,
111 EPP_INDEX_BALANCE_POWERSAVE,
112 EPP_INDEX_POWERSAVE,
113 };
114
115 static const char * const energy_perf_strings[] = {
116 [EPP_INDEX_DEFAULT] = "default",
117 [EPP_INDEX_PERFORMANCE] = "performance",
118 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
119 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
120 [EPP_INDEX_POWERSAVE] = "power",
121 NULL
122 };
123
124 static unsigned int epp_values[] = {
125 [EPP_INDEX_DEFAULT] = 0,
126 [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE,
127 [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE,
128 [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE,
129 [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE,
130 };
131
132 typedef int (*cppc_mode_transition_fn)(int);
133
134 static struct quirk_entry quirk_amd_7k62 = {
135 .nominal_freq = 2600,
136 .lowest_freq = 550,
137 };
138
139 static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi)
140 {
141 /**
142 * match the broken bios for family 17h processor support CPPC V2
143 * broken BIOS lack of nominal_freq and lowest_freq capabilities
144 * definition in ACPI tables
145 */
146 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) {
147 quirks = dmi->driver_data;
148 pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident);
149 return 1;
150 }
151
152 return 0;
153 }
154
155 static const struct dmi_system_id amd_pstate_quirks_table[] __initconst = {
156 {
157 .callback = dmi_matched_7k62_bios_bug,
158 .ident = "AMD EPYC 7K62",
159 .matches = {
160 DMI_MATCH(DMI_BIOS_VERSION, "5.14"),
161 DMI_MATCH(DMI_BIOS_RELEASE, "12/12/2019"),
162 },
163 .driver_data = &quirk_amd_7k62,
164 },
165 {}
166 };
167 MODULE_DEVICE_TABLE(dmi, amd_pstate_quirks_table);
168
169 static inline int get_mode_idx_from_str(const char *str, size_t size)
170 {
171 int i;
172
173 for (i=0; i < AMD_PSTATE_MAX; i++) {
174 if (!strncmp(str, amd_pstate_mode_string[i], size))
175 return i;
176 }
177 return -EINVAL;
178 }
179
180 static DEFINE_MUTEX(amd_pstate_limits_lock);
181 static DEFINE_MUTEX(amd_pstate_driver_lock);
182
183 static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
184 {
185 u64 epp;
186 int ret;
187
188 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
189 if (!cppc_req_cached) {
190 epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
191 &cppc_req_cached);
192 if (epp)
193 return epp;
194 }
195 epp = (cppc_req_cached >> 24) & 0xFF;
196 } else {
197 ret = cppc_get_epp_perf(cpudata->cpu, &epp);
198 if (ret < 0) {
199 pr_debug("Could not retrieve energy perf value (%d)\n", ret);
200 return -EIO;
201 }
202 }
203
204 return (s16)(epp & 0xff);
205 }
206
207 static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata)
208 {
209 s16 epp;
210 int index = -EINVAL;
211
212 epp = amd_pstate_get_epp(cpudata, 0);
213 if (epp < 0)
214 return epp;
215
216 switch (epp) {
217 case AMD_CPPC_EPP_PERFORMANCE:
218 index = EPP_INDEX_PERFORMANCE;
219 break;
220 case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
221 index = EPP_INDEX_BALANCE_PERFORMANCE;
222 break;
223 case AMD_CPPC_EPP_BALANCE_POWERSAVE:
224 index = EPP_INDEX_BALANCE_POWERSAVE;
225 break;
226 case AMD_CPPC_EPP_POWERSAVE:
227 index = EPP_INDEX_POWERSAVE;
228 break;
229 default:
230 break;
231 }
232
233 return index;
234 }
235
236 static void msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
237 u32 des_perf, u32 max_perf, bool fast_switch)
238 {
239 if (fast_switch)
240 wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));
241 else
242 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
243 READ_ONCE(cpudata->cppc_req_cached));
244 }
245
246 DEFINE_STATIC_CALL(amd_pstate_update_perf, msr_update_perf);
247
248 static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
249 u32 min_perf, u32 des_perf,
250 u32 max_perf, bool fast_switch)
251 {
252 static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf,
253 max_perf, fast_switch);
254 }
255
256 static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
257 {
258 int ret;
259 struct cppc_perf_ctrls perf_ctrls;
260
261 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
262 u64 value = READ_ONCE(cpudata->cppc_req_cached);
263
264 value &= ~GENMASK_ULL(31, 24);
265 value |= (u64)epp << 24;
266 WRITE_ONCE(cpudata->cppc_req_cached, value);
267
268 ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
269 if (!ret)
270 cpudata->epp_cached = epp;
271 } else {
272 amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U,
273 cpudata->max_limit_perf, false);
274
275 perf_ctrls.energy_perf = epp;
276 ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
277 if (ret) {
278 pr_debug("failed to set energy perf value (%d)\n", ret);
279 return ret;
280 }
281 cpudata->epp_cached = epp;
282 }
283
284 return ret;
285 }
286
287 static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
288 int pref_index)
289 {
290 int epp = -EINVAL;
291 int ret;
292
293 if (!pref_index)
294 epp = cpudata->epp_default;
295
296 if (epp == -EINVAL)
297 epp = epp_values[pref_index];
298
299 if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
300 pr_debug("EPP cannot be set under performance policy\n");
301 return -EBUSY;
302 }
303
304 ret = amd_pstate_set_epp(cpudata, epp);
305
306 return ret;
307 }
308
309 static inline int msr_cppc_enable(bool enable)
310 {
311 int ret, cpu;
312 unsigned long logical_proc_id_mask = 0;
313
314 /*
315 * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared.
316 */
317 if (!enable)
318 return 0;
319
320 if (enable == cppc_enabled)
321 return 0;
322
323 for_each_present_cpu(cpu) {
324 unsigned long logical_id = topology_logical_package_id(cpu);
325
326 if (test_bit(logical_id, &logical_proc_id_mask))
327 continue;
328
329 set_bit(logical_id, &logical_proc_id_mask);
330
331 ret = wrmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_ENABLE,
332 enable);
333 if (ret)
334 return ret;
335 }
336
337 cppc_enabled = enable;
338 return 0;
339 }
340
341 static int shmem_cppc_enable(bool enable)
342 {
343 int cpu, ret = 0;
344 struct cppc_perf_ctrls perf_ctrls;
345
346 if (enable == cppc_enabled)
347 return 0;
348
349 for_each_present_cpu(cpu) {
350 ret = cppc_set_enable(cpu, enable);
351 if (ret)
352 return ret;
353
354 /* Enable autonomous mode for EPP */
355 if (cppc_state == AMD_PSTATE_ACTIVE) {
356 /* Set desired perf as zero to allow EPP firmware control */
357 perf_ctrls.desired_perf = 0;
358 ret = cppc_set_perf(cpu, &perf_ctrls);
359 if (ret)
360 return ret;
361 }
362 }
363
364 cppc_enabled = enable;
365 return ret;
366 }
367
368 DEFINE_STATIC_CALL(amd_pstate_cppc_enable, msr_cppc_enable);
369
370 static inline int amd_pstate_cppc_enable(bool enable)
371 {
372 return static_call(amd_pstate_cppc_enable)(enable);
373 }
374
375 static int msr_init_perf(struct amd_cpudata *cpudata)
376 {
377 u64 cap1;
378
379 int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
380 &cap1);
381 if (ret)
382 return ret;
383
384 WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
385 WRITE_ONCE(cpudata->max_limit_perf, AMD_CPPC_HIGHEST_PERF(cap1));
386 WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
387 WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
388 WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
389 WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1));
390 WRITE_ONCE(cpudata->min_limit_perf, AMD_CPPC_LOWEST_PERF(cap1));
391 return 0;
392 }
393
394 static int shmem_init_perf(struct amd_cpudata *cpudata)
395 {
396 struct cppc_perf_caps cppc_perf;
397
398 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
399 if (ret)
400 return ret;
401
402 WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf);
403 WRITE_ONCE(cpudata->max_limit_perf, cppc_perf.highest_perf);
404 WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
405 WRITE_ONCE(cpudata->lowest_nonlinear_perf,
406 cppc_perf.lowest_nonlinear_perf);
407 WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
408 WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf);
409 WRITE_ONCE(cpudata->min_limit_perf, cppc_perf.lowest_perf);
410
411 if (cppc_state == AMD_PSTATE_ACTIVE)
412 return 0;
413
414 ret = cppc_get_auto_sel_caps(cpudata->cpu, &cppc_perf);
415 if (ret) {
416 pr_warn("failed to get auto_sel, ret: %d\n", ret);
417 return 0;
418 }
419
420 ret = cppc_set_auto_sel(cpudata->cpu,
421 (cppc_state == AMD_PSTATE_PASSIVE) ? 0 : 1);
422
423 if (ret)
424 pr_warn("failed to set auto_sel, ret: %d\n", ret);
425
426 return ret;
427 }
428
429 DEFINE_STATIC_CALL(amd_pstate_init_perf, msr_init_perf);
430
431 static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata)
432 {
433 return static_call(amd_pstate_init_perf)(cpudata);
434 }
435
436 static void shmem_update_perf(struct amd_cpudata *cpudata,
437 u32 min_perf, u32 des_perf,
438 u32 max_perf, bool fast_switch)
439 {
440 struct cppc_perf_ctrls perf_ctrls;
441
442 perf_ctrls.max_perf = max_perf;
443 perf_ctrls.min_perf = min_perf;
444 perf_ctrls.desired_perf = des_perf;
445
446 cppc_set_perf(cpudata->cpu, &perf_ctrls);
447 }
448
449 static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
450 {
451 u64 aperf, mperf, tsc;
452 unsigned long flags;
453
454 local_irq_save(flags);
455 rdmsrl(MSR_IA32_APERF, aperf);
456 rdmsrl(MSR_IA32_MPERF, mperf);
457 tsc = rdtsc();
458
459 if (cpudata->prev.mperf == mperf || cpudata->prev.tsc == tsc) {
460 local_irq_restore(flags);
461 return false;
462 }
463
464 local_irq_restore(flags);
465
466 cpudata->cur.aperf = aperf;
467 cpudata->cur.mperf = mperf;
468 cpudata->cur.tsc = tsc;
469 cpudata->cur.aperf -= cpudata->prev.aperf;
470 cpudata->cur.mperf -= cpudata->prev.mperf;
471 cpudata->cur.tsc -= cpudata->prev.tsc;
472
473 cpudata->prev.aperf = aperf;
474 cpudata->prev.mperf = mperf;
475 cpudata->prev.tsc = tsc;
476
477 cpudata->freq = div64_u64((cpudata->cur.aperf * cpu_khz), cpudata->cur.mperf);
478
479 return true;
480 }
481
482 static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
483 u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags)
484 {
485 unsigned long max_freq;
486 struct cpufreq_policy *policy = cpufreq_cpu_get(cpudata->cpu);
487 u64 prev = READ_ONCE(cpudata->cppc_req_cached);
488 u32 nominal_perf = READ_ONCE(cpudata->nominal_perf);
489 u64 value = prev;
490
491 min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf,
492 cpudata->max_limit_perf);
493 max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf,
494 cpudata->max_limit_perf);
495 des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
496
497 max_freq = READ_ONCE(cpudata->max_limit_freq);
498 policy->cur = div_u64(des_perf * max_freq, max_perf);
499
500 if ((cppc_state == AMD_PSTATE_GUIDED) && (gov_flags & CPUFREQ_GOV_DYNAMIC_SWITCHING)) {
501 min_perf = des_perf;
502 des_perf = 0;
503 }
504
505 value &= ~AMD_CPPC_MIN_PERF(~0L);
506 value |= AMD_CPPC_MIN_PERF(min_perf);
507
508 value &= ~AMD_CPPC_DES_PERF(~0L);
509 value |= AMD_CPPC_DES_PERF(des_perf);
510
511 /* limit the max perf when core performance boost feature is disabled */
512 if (!cpudata->boost_supported)
513 max_perf = min_t(unsigned long, nominal_perf, max_perf);
514
515 value &= ~AMD_CPPC_MAX_PERF(~0L);
516 value |= AMD_CPPC_MAX_PERF(max_perf);
517
518 if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) {
519 trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq,
520 cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc,
521 cpudata->cpu, (value != prev), fast_switch);
522 }
523
524 if (value == prev)
525 goto cpufreq_policy_put;
526
527 WRITE_ONCE(cpudata->cppc_req_cached, value);
528
529 amd_pstate_update_perf(cpudata, min_perf, des_perf,
530 max_perf, fast_switch);
531
532 cpufreq_policy_put:
533 cpufreq_cpu_put(policy);
534 }
535
536 static int amd_pstate_verify(struct cpufreq_policy_data *policy_data)
537 {
538 /*
539 * Initialize lower frequency limit (i.e.policy->min) with
540 * lowest_nonlinear_frequency which is the most energy efficient
541 * frequency. Override the initial value set by cpufreq core and
542 * amd-pstate qos_requests.
543 */
544 if (policy_data->min == FREQ_QOS_MIN_DEFAULT_VALUE) {
545 struct cpufreq_policy *policy = cpufreq_cpu_get(policy_data->cpu);
546 struct amd_cpudata *cpudata;
547
548 if (!policy)
549 return -EINVAL;
550
551 cpudata = policy->driver_data;
552 policy_data->min = cpudata->lowest_nonlinear_freq;
553 cpufreq_cpu_put(policy);
554 }
555
556 cpufreq_verify_within_cpu_limits(policy_data);
557 pr_debug("policy_max =%d, policy_min=%d\n", policy_data->max, policy_data->min);
558
559 return 0;
560 }
561
562 static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy)
563 {
564 u32 max_limit_perf, min_limit_perf, lowest_perf, max_perf;
565 struct amd_cpudata *cpudata = policy->driver_data;
566
567 if (cpudata->boost_supported && !policy->boost_enabled)
568 max_perf = READ_ONCE(cpudata->nominal_perf);
569 else
570 max_perf = READ_ONCE(cpudata->highest_perf);
571
572 max_limit_perf = div_u64(policy->max * max_perf, policy->cpuinfo.max_freq);
573 min_limit_perf = div_u64(policy->min * max_perf, policy->cpuinfo.max_freq);
574
575 lowest_perf = READ_ONCE(cpudata->lowest_perf);
576 if (min_limit_perf < lowest_perf)
577 min_limit_perf = lowest_perf;
578
579 if (max_limit_perf < min_limit_perf)
580 max_limit_perf = min_limit_perf;
581
582 WRITE_ONCE(cpudata->max_limit_perf, max_limit_perf);
583 WRITE_ONCE(cpudata->min_limit_perf, min_limit_perf);
584 WRITE_ONCE(cpudata->max_limit_freq, policy->max);
585 WRITE_ONCE(cpudata->min_limit_freq, policy->min);
586
587 return 0;
588 }
589
590 static int amd_pstate_update_freq(struct cpufreq_policy *policy,
591 unsigned int target_freq, bool fast_switch)
592 {
593 struct cpufreq_freqs freqs;
594 struct amd_cpudata *cpudata = policy->driver_data;
595 unsigned long max_perf, min_perf, des_perf, cap_perf;
596
597 if (!cpudata->max_freq)
598 return -ENODEV;
599
600 if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq)
601 amd_pstate_update_min_max_limit(policy);
602
603 cap_perf = READ_ONCE(cpudata->highest_perf);
604 min_perf = READ_ONCE(cpudata->lowest_perf);
605 max_perf = cap_perf;
606
607 freqs.old = policy->cur;
608 freqs.new = target_freq;
609
610 des_perf = DIV_ROUND_CLOSEST(target_freq * cap_perf,
611 cpudata->max_freq);
612
613 WARN_ON(fast_switch && !policy->fast_switch_enabled);
614 /*
615 * If fast_switch is desired, then there aren't any registered
616 * transition notifiers. See comment for
617 * cpufreq_enable_fast_switch().
618 */
619 if (!fast_switch)
620 cpufreq_freq_transition_begin(policy, &freqs);
621
622 amd_pstate_update(cpudata, min_perf, des_perf,
623 max_perf, fast_switch, policy->governor->flags);
624
625 if (!fast_switch)
626 cpufreq_freq_transition_end(policy, &freqs, false);
627
628 return 0;
629 }
630
631 static int amd_pstate_target(struct cpufreq_policy *policy,
632 unsigned int target_freq,
633 unsigned int relation)
634 {
635 return amd_pstate_update_freq(policy, target_freq, false);
636 }
637
638 static unsigned int amd_pstate_fast_switch(struct cpufreq_policy *policy,
639 unsigned int target_freq)
640 {
641 if (!amd_pstate_update_freq(policy, target_freq, true))
642 return target_freq;
643 return policy->cur;
644 }
645
646 static void amd_pstate_adjust_perf(unsigned int cpu,
647 unsigned long _min_perf,
648 unsigned long target_perf,
649 unsigned long capacity)
650 {
651 unsigned long max_perf, min_perf, des_perf,
652 cap_perf, lowest_nonlinear_perf;
653 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
654 struct amd_cpudata *cpudata;
655
656 if (!policy)
657 return;
658
659 cpudata = policy->driver_data;
660
661 if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq)
662 amd_pstate_update_min_max_limit(policy);
663
664
665 cap_perf = READ_ONCE(cpudata->highest_perf);
666 lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf);
667
668 des_perf = cap_perf;
669 if (target_perf < capacity)
670 des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity);
671
672 min_perf = READ_ONCE(cpudata->lowest_perf);
673 if (_min_perf < capacity)
674 min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity);
675
676 if (min_perf < lowest_nonlinear_perf)
677 min_perf = lowest_nonlinear_perf;
678
679 max_perf = cap_perf;
680 if (max_perf < min_perf)
681 max_perf = min_perf;
682
683 des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
684
685 amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true,
686 policy->governor->flags);
687 cpufreq_cpu_put(policy);
688 }
689
690 static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on)
691 {
692 struct amd_cpudata *cpudata = policy->driver_data;
693 u32 nominal_freq, max_freq;
694 int ret = 0;
695
696 nominal_freq = READ_ONCE(cpudata->nominal_freq);
697 max_freq = READ_ONCE(cpudata->max_freq);
698
699 if (on)
700 policy->cpuinfo.max_freq = max_freq;
701 else if (policy->cpuinfo.max_freq > nominal_freq * 1000)
702 policy->cpuinfo.max_freq = nominal_freq * 1000;
703
704 policy->max = policy->cpuinfo.max_freq;
705
706 if (cppc_state == AMD_PSTATE_PASSIVE) {
707 ret = freq_qos_update_request(&cpudata->req[1], policy->cpuinfo.max_freq);
708 if (ret < 0)
709 pr_debug("Failed to update freq constraint: CPU%d\n", cpudata->cpu);
710 }
711
712 return ret < 0 ? ret : 0;
713 }
714
715 static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state)
716 {
717 struct amd_cpudata *cpudata = policy->driver_data;
718 int ret;
719
720 if (!cpudata->boost_supported) {
721 pr_err("Boost mode is not supported by this processor or SBIOS\n");
722 return -EOPNOTSUPP;
723 }
724 mutex_lock(&amd_pstate_driver_lock);
725 ret = amd_pstate_cpu_boost_update(policy, state);
726 WRITE_ONCE(cpudata->boost_state, !ret ? state : false);
727 policy->boost_enabled = !ret ? state : false;
728 refresh_frequency_limits(policy);
729 mutex_unlock(&amd_pstate_driver_lock);
730
731 return ret;
732 }
733
734 static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata)
735 {
736 u64 boost_val;
737 int ret = -1;
738
739 /*
740 * If platform has no CPB support or disable it, initialize current driver
741 * boost_enabled state to be false, it is not an error for cpufreq core to handle.
742 */
743 if (!cpu_feature_enabled(X86_FEATURE_CPB)) {
744 pr_debug_once("Boost CPB capabilities not present in the processor\n");
745 ret = 0;
746 goto exit_err;
747 }
748
749 /* at least one CPU supports CPB, even if others fail later on to set up */
750 current_pstate_driver->boost_enabled = true;
751
752 ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val);
753 if (ret) {
754 pr_err_once("failed to read initial CPU boost state!\n");
755 ret = -EIO;
756 goto exit_err;
757 }
758
759 if (!(boost_val & MSR_K7_HWCR_CPB_DIS))
760 cpudata->boost_supported = true;
761
762 return 0;
763
764 exit_err:
765 cpudata->boost_supported = false;
766 return ret;
767 }
768
769 static void amd_perf_ctl_reset(unsigned int cpu)
770 {
771 wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
772 }
773
774 /*
775 * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks
776 * due to locking, so queue the work for later.
777 */
778 static void amd_pstste_sched_prefcore_workfn(struct work_struct *work)
779 {
780 sched_set_itmt_support();
781 }
782 static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn);
783
784 #define CPPC_MAX_PERF U8_MAX
785
786 static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata)
787 {
788 /* user disabled or not detected */
789 if (!amd_pstate_prefcore)
790 return;
791
792 cpudata->hw_prefcore = true;
793
794 /*
795 * The priorities can be set regardless of whether or not
796 * sched_set_itmt_support(true) has been called and it is valid to
797 * update them at any time after it has been called.
798 */
799 sched_set_itmt_core_prio((int)READ_ONCE(cpudata->highest_perf), cpudata->cpu);
800
801 schedule_work(&sched_prefcore_work);
802 }
803
804 static void amd_pstate_update_limits(unsigned int cpu)
805 {
806 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
807 struct amd_cpudata *cpudata;
808 u32 prev_high = 0, cur_high = 0;
809 int ret;
810 bool highest_perf_changed = false;
811
812 if (!policy)
813 return;
814
815 cpudata = policy->driver_data;
816
817 if (!amd_pstate_prefcore)
818 return;
819
820 mutex_lock(&amd_pstate_driver_lock);
821 ret = amd_get_highest_perf(cpu, &cur_high);
822 if (ret)
823 goto free_cpufreq_put;
824
825 prev_high = READ_ONCE(cpudata->prefcore_ranking);
826 highest_perf_changed = (prev_high != cur_high);
827 if (highest_perf_changed) {
828 WRITE_ONCE(cpudata->prefcore_ranking, cur_high);
829
830 if (cur_high < CPPC_MAX_PERF)
831 sched_set_itmt_core_prio((int)cur_high, cpu);
832 }
833
834 free_cpufreq_put:
835 cpufreq_cpu_put(policy);
836
837 if (!highest_perf_changed)
838 cpufreq_update_policy(cpu);
839
840 mutex_unlock(&amd_pstate_driver_lock);
841 }
842
843 /*
844 * Get pstate transition delay time from ACPI tables that firmware set
845 * instead of using hardcode value directly.
846 */
847 static u32 amd_pstate_get_transition_delay_us(unsigned int cpu)
848 {
849 u32 transition_delay_ns;
850
851 transition_delay_ns = cppc_get_transition_latency(cpu);
852 if (transition_delay_ns == CPUFREQ_ETERNAL) {
853 if (cpu_feature_enabled(X86_FEATURE_AMD_FAST_CPPC))
854 return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY;
855 else
856 return AMD_PSTATE_TRANSITION_DELAY;
857 }
858
859 return transition_delay_ns / NSEC_PER_USEC;
860 }
861
862 /*
863 * Get pstate transition latency value from ACPI tables that firmware
864 * set instead of using hardcode value directly.
865 */
866 static u32 amd_pstate_get_transition_latency(unsigned int cpu)
867 {
868 u32 transition_latency;
869
870 transition_latency = cppc_get_transition_latency(cpu);
871 if (transition_latency == CPUFREQ_ETERNAL)
872 return AMD_PSTATE_TRANSITION_LATENCY;
873
874 return transition_latency;
875 }
876
877 /*
878 * amd_pstate_init_freq: Initialize the max_freq, min_freq,
879 * nominal_freq and lowest_nonlinear_freq for
880 * the @cpudata object.
881 *
882 * Requires: highest_perf, lowest_perf, nominal_perf and
883 * lowest_nonlinear_perf members of @cpudata to be
884 * initialized.
885 *
886 * Returns 0 on success, non-zero value on failure.
887 */
888 static int amd_pstate_init_freq(struct amd_cpudata *cpudata)
889 {
890 int ret;
891 u32 min_freq, max_freq;
892 u64 numerator;
893 u32 nominal_perf, nominal_freq;
894 u32 lowest_nonlinear_perf, lowest_nonlinear_freq;
895 u32 boost_ratio, lowest_nonlinear_ratio;
896 struct cppc_perf_caps cppc_perf;
897
898 ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
899 if (ret)
900 return ret;
901
902 if (quirks && quirks->lowest_freq)
903 min_freq = quirks->lowest_freq * 1000;
904 else
905 min_freq = cppc_perf.lowest_freq * 1000;
906
907 if (quirks && quirks->nominal_freq)
908 nominal_freq = quirks->nominal_freq ;
909 else
910 nominal_freq = cppc_perf.nominal_freq;
911
912 nominal_perf = READ_ONCE(cpudata->nominal_perf);
913
914 ret = amd_get_boost_ratio_numerator(cpudata->cpu, &numerator);
915 if (ret)
916 return ret;
917 boost_ratio = div_u64(numerator << SCHED_CAPACITY_SHIFT, nominal_perf);
918 max_freq = (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT) * 1000;
919
920 lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf);
921 lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT,
922 nominal_perf);
923 lowest_nonlinear_freq = (nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT) * 1000;
924
925 WRITE_ONCE(cpudata->min_freq, min_freq);
926 WRITE_ONCE(cpudata->lowest_nonlinear_freq, lowest_nonlinear_freq);
927 WRITE_ONCE(cpudata->nominal_freq, nominal_freq);
928 WRITE_ONCE(cpudata->max_freq, max_freq);
929
930 /**
931 * Below values need to be initialized correctly, otherwise driver will fail to load
932 * max_freq is calculated according to (nominal_freq * highest_perf)/nominal_perf
933 * lowest_nonlinear_freq is a value between [min_freq, nominal_freq]
934 * Check _CPC in ACPI table objects if any values are incorrect
935 */
936 if (min_freq <= 0 || max_freq <= 0 || nominal_freq <= 0 || min_freq > max_freq) {
937 pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect\n",
938 min_freq, max_freq, nominal_freq * 1000);
939 return -EINVAL;
940 }
941
942 if (lowest_nonlinear_freq <= min_freq || lowest_nonlinear_freq > nominal_freq * 1000) {
943 pr_err("lowest_nonlinear_freq(%d) value is out of range [min_freq(%d), nominal_freq(%d)]\n",
944 lowest_nonlinear_freq, min_freq, nominal_freq * 1000);
945 return -EINVAL;
946 }
947
948 return 0;
949 }
950
951 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
952 {
953 int min_freq, max_freq, ret;
954 struct device *dev;
955 struct amd_cpudata *cpudata;
956
957 /*
958 * Resetting PERF_CTL_MSR will put the CPU in P0 frequency,
959 * which is ideal for initialization process.
960 */
961 amd_perf_ctl_reset(policy->cpu);
962 dev = get_cpu_device(policy->cpu);
963 if (!dev)
964 return -ENODEV;
965
966 cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
967 if (!cpudata)
968 return -ENOMEM;
969
970 cpudata->cpu = policy->cpu;
971
972 ret = amd_pstate_init_perf(cpudata);
973 if (ret)
974 goto free_cpudata1;
975
976 amd_pstate_init_prefcore(cpudata);
977
978 ret = amd_pstate_init_freq(cpudata);
979 if (ret)
980 goto free_cpudata1;
981
982 ret = amd_pstate_init_boost_support(cpudata);
983 if (ret)
984 goto free_cpudata1;
985
986 min_freq = READ_ONCE(cpudata->min_freq);
987 max_freq = READ_ONCE(cpudata->max_freq);
988
989 policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu);
990 policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu);
991
992 policy->min = min_freq;
993 policy->max = max_freq;
994
995 policy->cpuinfo.min_freq = min_freq;
996 policy->cpuinfo.max_freq = max_freq;
997
998 policy->boost_enabled = READ_ONCE(cpudata->boost_supported);
999
1000 /* It will be updated by governor */
1001 policy->cur = policy->cpuinfo.min_freq;
1002
1003 if (cpu_feature_enabled(X86_FEATURE_CPPC))
1004 policy->fast_switch_possible = true;
1005
1006 ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0],
1007 FREQ_QOS_MIN, FREQ_QOS_MIN_DEFAULT_VALUE);
1008 if (ret < 0) {
1009 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
1010 goto free_cpudata1;
1011 }
1012
1013 ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1],
1014 FREQ_QOS_MAX, policy->cpuinfo.max_freq);
1015 if (ret < 0) {
1016 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
1017 goto free_cpudata2;
1018 }
1019
1020 cpudata->max_limit_freq = max_freq;
1021 cpudata->min_limit_freq = min_freq;
1022
1023 policy->driver_data = cpudata;
1024
1025 if (!current_pstate_driver->adjust_perf)
1026 current_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
1027
1028 return 0;
1029
1030 free_cpudata2:
1031 freq_qos_remove_request(&cpudata->req[0]);
1032 free_cpudata1:
1033 kfree(cpudata);
1034 return ret;
1035 }
1036
1037 static void amd_pstate_cpu_exit(struct cpufreq_policy *policy)
1038 {
1039 struct amd_cpudata *cpudata = policy->driver_data;
1040
1041 freq_qos_remove_request(&cpudata->req[1]);
1042 freq_qos_remove_request(&cpudata->req[0]);
1043 policy->fast_switch_possible = false;
1044 kfree(cpudata);
1045 }
1046
1047 static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
1048 {
1049 int ret;
1050
1051 ret = amd_pstate_cppc_enable(true);
1052 if (ret)
1053 pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
1054
1055 return ret;
1056 }
1057
1058 static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
1059 {
1060 int ret;
1061
1062 ret = amd_pstate_cppc_enable(false);
1063 if (ret)
1064 pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);
1065
1066 return ret;
1067 }
1068
1069 /* Sysfs attributes */
1070
1071 /*
1072 * This frequency is to indicate the maximum hardware frequency.
1073 * If boost is not active but supported, the frequency will be larger than the
1074 * one in cpuinfo.
1075 */
1076 static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy,
1077 char *buf)
1078 {
1079 int max_freq;
1080 struct amd_cpudata *cpudata = policy->driver_data;
1081
1082 max_freq = READ_ONCE(cpudata->max_freq);
1083 if (max_freq < 0)
1084 return max_freq;
1085
1086 return sysfs_emit(buf, "%u\n", max_freq);
1087 }
1088
1089 static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy,
1090 char *buf)
1091 {
1092 int freq;
1093 struct amd_cpudata *cpudata = policy->driver_data;
1094
1095 freq = READ_ONCE(cpudata->lowest_nonlinear_freq);
1096 if (freq < 0)
1097 return freq;
1098
1099 return sysfs_emit(buf, "%u\n", freq);
1100 }
1101
1102 /*
1103 * In some of ASICs, the highest_perf is not the one in the _CPC table, so we
1104 * need to expose it to sysfs.
1105 */
1106 static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
1107 char *buf)
1108 {
1109 u32 perf;
1110 struct amd_cpudata *cpudata = policy->driver_data;
1111
1112 perf = READ_ONCE(cpudata->highest_perf);
1113
1114 return sysfs_emit(buf, "%u\n", perf);
1115 }
1116
1117 static ssize_t show_amd_pstate_prefcore_ranking(struct cpufreq_policy *policy,
1118 char *buf)
1119 {
1120 u32 perf;
1121 struct amd_cpudata *cpudata = policy->driver_data;
1122
1123 perf = READ_ONCE(cpudata->prefcore_ranking);
1124
1125 return sysfs_emit(buf, "%u\n", perf);
1126 }
1127
1128 static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy,
1129 char *buf)
1130 {
1131 bool hw_prefcore;
1132 struct amd_cpudata *cpudata = policy->driver_data;
1133
1134 hw_prefcore = READ_ONCE(cpudata->hw_prefcore);
1135
1136 return sysfs_emit(buf, "%s\n", str_enabled_disabled(hw_prefcore));
1137 }
1138
1139 static ssize_t show_energy_performance_available_preferences(
1140 struct cpufreq_policy *policy, char *buf)
1141 {
1142 int i = 0;
1143 int offset = 0;
1144 struct amd_cpudata *cpudata = policy->driver_data;
1145
1146 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
1147 return sysfs_emit_at(buf, offset, "%s\n",
1148 energy_perf_strings[EPP_INDEX_PERFORMANCE]);
1149
1150 while (energy_perf_strings[i] != NULL)
1151 offset += sysfs_emit_at(buf, offset, "%s ", energy_perf_strings[i++]);
1152
1153 offset += sysfs_emit_at(buf, offset, "\n");
1154
1155 return offset;
1156 }
1157
1158 static ssize_t store_energy_performance_preference(
1159 struct cpufreq_policy *policy, const char *buf, size_t count)
1160 {
1161 struct amd_cpudata *cpudata = policy->driver_data;
1162 char str_preference[21];
1163 ssize_t ret;
1164
1165 ret = sscanf(buf, "%20s", str_preference);
1166 if (ret != 1)
1167 return -EINVAL;
1168
1169 ret = match_string(energy_perf_strings, -1, str_preference);
1170 if (ret < 0)
1171 return -EINVAL;
1172
1173 mutex_lock(&amd_pstate_limits_lock);
1174 ret = amd_pstate_set_energy_pref_index(cpudata, ret);
1175 mutex_unlock(&amd_pstate_limits_lock);
1176
1177 return ret ?: count;
1178 }
1179
1180 static ssize_t show_energy_performance_preference(
1181 struct cpufreq_policy *policy, char *buf)
1182 {
1183 struct amd_cpudata *cpudata = policy->driver_data;
1184 int preference;
1185
1186 preference = amd_pstate_get_energy_pref_index(cpudata);
1187 if (preference < 0)
1188 return preference;
1189
1190 return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]);
1191 }
1192
1193 static void amd_pstate_driver_cleanup(void)
1194 {
1195 amd_pstate_cppc_enable(false);
1196 cppc_state = AMD_PSTATE_DISABLE;
1197 current_pstate_driver = NULL;
1198 }
1199
1200 static int amd_pstate_set_driver(int mode_idx)
1201 {
1202 if (mode_idx >= AMD_PSTATE_DISABLE && mode_idx < AMD_PSTATE_MAX) {
1203 cppc_state = mode_idx;
1204 if (cppc_state == AMD_PSTATE_DISABLE)
1205 pr_info("driver is explicitly disabled\n");
1206
1207 if (cppc_state == AMD_PSTATE_ACTIVE)
1208 current_pstate_driver = &amd_pstate_epp_driver;
1209
1210 if (cppc_state == AMD_PSTATE_PASSIVE || cppc_state == AMD_PSTATE_GUIDED)
1211 current_pstate_driver = &amd_pstate_driver;
1212
1213 return 0;
1214 }
1215
1216 return -EINVAL;
1217 }
1218
1219 static int amd_pstate_register_driver(int mode)
1220 {
1221 int ret;
1222
1223 ret = amd_pstate_set_driver(mode);
1224 if (ret)
1225 return ret;
1226
1227 cppc_state = mode;
1228
1229 ret = amd_pstate_cppc_enable(true);
1230 if (ret) {
1231 pr_err("failed to enable cppc during amd-pstate driver registration, return %d\n",
1232 ret);
1233 amd_pstate_driver_cleanup();
1234 return ret;
1235 }
1236
1237 ret = cpufreq_register_driver(current_pstate_driver);
1238 if (ret) {
1239 amd_pstate_driver_cleanup();
1240 return ret;
1241 }
1242
1243 return 0;
1244 }
1245
1246 static int amd_pstate_unregister_driver(int dummy)
1247 {
1248 cpufreq_unregister_driver(current_pstate_driver);
1249 amd_pstate_driver_cleanup();
1250 return 0;
1251 }
1252
1253 static int amd_pstate_change_mode_without_dvr_change(int mode)
1254 {
1255 int cpu = 0;
1256
1257 cppc_state = mode;
1258
1259 if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE)
1260 return 0;
1261
1262 for_each_present_cpu(cpu) {
1263 cppc_set_auto_sel(cpu, (cppc_state == AMD_PSTATE_PASSIVE) ? 0 : 1);
1264 }
1265
1266 return 0;
1267 }
1268
1269 static int amd_pstate_change_driver_mode(int mode)
1270 {
1271 int ret;
1272
1273 ret = amd_pstate_unregister_driver(0);
1274 if (ret)
1275 return ret;
1276
1277 ret = amd_pstate_register_driver(mode);
1278 if (ret)
1279 return ret;
1280
1281 return 0;
1282 }
1283
1284 static cppc_mode_transition_fn mode_state_machine[AMD_PSTATE_MAX][AMD_PSTATE_MAX] = {
1285 [AMD_PSTATE_DISABLE] = {
1286 [AMD_PSTATE_DISABLE] = NULL,
1287 [AMD_PSTATE_PASSIVE] = amd_pstate_register_driver,
1288 [AMD_PSTATE_ACTIVE] = amd_pstate_register_driver,
1289 [AMD_PSTATE_GUIDED] = amd_pstate_register_driver,
1290 },
1291 [AMD_PSTATE_PASSIVE] = {
1292 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver,
1293 [AMD_PSTATE_PASSIVE] = NULL,
1294 [AMD_PSTATE_ACTIVE] = amd_pstate_change_driver_mode,
1295 [AMD_PSTATE_GUIDED] = amd_pstate_change_mode_without_dvr_change,
1296 },
1297 [AMD_PSTATE_ACTIVE] = {
1298 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver,
1299 [AMD_PSTATE_PASSIVE] = amd_pstate_change_driver_mode,
1300 [AMD_PSTATE_ACTIVE] = NULL,
1301 [AMD_PSTATE_GUIDED] = amd_pstate_change_driver_mode,
1302 },
1303 [AMD_PSTATE_GUIDED] = {
1304 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver,
1305 [AMD_PSTATE_PASSIVE] = amd_pstate_change_mode_without_dvr_change,
1306 [AMD_PSTATE_ACTIVE] = amd_pstate_change_driver_mode,
1307 [AMD_PSTATE_GUIDED] = NULL,
1308 },
1309 };
1310
1311 static ssize_t amd_pstate_show_status(char *buf)
1312 {
1313 if (!current_pstate_driver)
1314 return sysfs_emit(buf, "disable\n");
1315
1316 return sysfs_emit(buf, "%s\n", amd_pstate_mode_string[cppc_state]);
1317 }
1318
1319 int amd_pstate_update_status(const char *buf, size_t size)
1320 {
1321 int mode_idx;
1322
1323 if (size > strlen("passive") || size < strlen("active"))
1324 return -EINVAL;
1325
1326 mode_idx = get_mode_idx_from_str(buf, size);
1327
1328 if (mode_idx < 0 || mode_idx >= AMD_PSTATE_MAX)
1329 return -EINVAL;
1330
1331 if (mode_state_machine[cppc_state][mode_idx])
1332 return mode_state_machine[cppc_state][mode_idx](mode_idx);
1333
1334 return 0;
1335 }
1336 EXPORT_SYMBOL_GPL(amd_pstate_update_status);
1337
1338 static ssize_t status_show(struct device *dev,
1339 struct device_attribute *attr, char *buf)
1340 {
1341 ssize_t ret;
1342
1343 mutex_lock(&amd_pstate_driver_lock);
1344 ret = amd_pstate_show_status(buf);
1345 mutex_unlock(&amd_pstate_driver_lock);
1346
1347 return ret;
1348 }
1349
1350 static ssize_t status_store(struct device *a, struct device_attribute *b,
1351 const char *buf, size_t count)
1352 {
1353 char *p = memchr(buf, '\n', count);
1354 int ret;
1355
1356 mutex_lock(&amd_pstate_driver_lock);
1357 ret = amd_pstate_update_status(buf, p ? p - buf : count);
1358 mutex_unlock(&amd_pstate_driver_lock);
1359
1360 return ret < 0 ? ret : count;
1361 }
1362
1363 static ssize_t prefcore_show(struct device *dev,
1364 struct device_attribute *attr, char *buf)
1365 {
1366 return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore));
1367 }
1368
1369 cpufreq_freq_attr_ro(amd_pstate_max_freq);
1370 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
1371
1372 cpufreq_freq_attr_ro(amd_pstate_highest_perf);
1373 cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking);
1374 cpufreq_freq_attr_ro(amd_pstate_hw_prefcore);
1375 cpufreq_freq_attr_rw(energy_performance_preference);
1376 cpufreq_freq_attr_ro(energy_performance_available_preferences);
1377 static DEVICE_ATTR_RW(status);
1378 static DEVICE_ATTR_RO(prefcore);
1379
1380 static struct freq_attr *amd_pstate_attr[] = {
1381 &amd_pstate_max_freq,
1382 &amd_pstate_lowest_nonlinear_freq,
1383 &amd_pstate_highest_perf,
1384 &amd_pstate_prefcore_ranking,
1385 &amd_pstate_hw_prefcore,
1386 NULL,
1387 };
1388
1389 static struct freq_attr *amd_pstate_epp_attr[] = {
1390 &amd_pstate_max_freq,
1391 &amd_pstate_lowest_nonlinear_freq,
1392 &amd_pstate_highest_perf,
1393 &amd_pstate_prefcore_ranking,
1394 &amd_pstate_hw_prefcore,
1395 &energy_performance_preference,
1396 &energy_performance_available_preferences,
1397 NULL,
1398 };
1399
1400 static struct attribute *pstate_global_attributes[] = {
1401 &dev_attr_status.attr,
1402 &dev_attr_prefcore.attr,
1403 NULL
1404 };
1405
1406 static const struct attribute_group amd_pstate_global_attr_group = {
1407 .name = "amd_pstate",
1408 .attrs = pstate_global_attributes,
1409 };
1410
1411 static bool amd_pstate_acpi_pm_profile_server(void)
1412 {
1413 switch (acpi_gbl_FADT.preferred_profile) {
1414 case PM_ENTERPRISE_SERVER:
1415 case PM_SOHO_SERVER:
1416 case PM_PERFORMANCE_SERVER:
1417 return true;
1418 }
1419 return false;
1420 }
1421
1422 static bool amd_pstate_acpi_pm_profile_undefined(void)
1423 {
1424 if (acpi_gbl_FADT.preferred_profile == PM_UNSPECIFIED)
1425 return true;
1426 if (acpi_gbl_FADT.preferred_profile >= NR_PM_PROFILES)
1427 return true;
1428 return false;
1429 }
1430
1431 static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
1432 {
1433 int min_freq, max_freq, ret;
1434 struct amd_cpudata *cpudata;
1435 struct device *dev;
1436 u64 value;
1437
1438 /*
1439 * Resetting PERF_CTL_MSR will put the CPU in P0 frequency,
1440 * which is ideal for initialization process.
1441 */
1442 amd_perf_ctl_reset(policy->cpu);
1443 dev = get_cpu_device(policy->cpu);
1444 if (!dev)
1445 return -ENODEV;
1446
1447 cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
1448 if (!cpudata)
1449 return -ENOMEM;
1450
1451 cpudata->cpu = policy->cpu;
1452 cpudata->epp_policy = 0;
1453
1454 ret = amd_pstate_init_perf(cpudata);
1455 if (ret)
1456 goto free_cpudata1;
1457
1458 amd_pstate_init_prefcore(cpudata);
1459
1460 ret = amd_pstate_init_freq(cpudata);
1461 if (ret)
1462 goto free_cpudata1;
1463
1464 ret = amd_pstate_init_boost_support(cpudata);
1465 if (ret)
1466 goto free_cpudata1;
1467
1468 min_freq = READ_ONCE(cpudata->min_freq);
1469 max_freq = READ_ONCE(cpudata->max_freq);
1470
1471 policy->cpuinfo.min_freq = min_freq;
1472 policy->cpuinfo.max_freq = max_freq;
1473 /* It will be updated by governor */
1474 policy->cur = policy->cpuinfo.min_freq;
1475
1476 policy->driver_data = cpudata;
1477
1478 cpudata->epp_cached = cpudata->epp_default = amd_pstate_get_epp(cpudata, 0);
1479
1480 policy->min = policy->cpuinfo.min_freq;
1481 policy->max = policy->cpuinfo.max_freq;
1482
1483 policy->boost_enabled = READ_ONCE(cpudata->boost_supported);
1484
1485 /*
1486 * Set the policy to provide a valid fallback value in case
1487 * the default cpufreq governor is neither powersave nor performance.
1488 */
1489 if (amd_pstate_acpi_pm_profile_server() ||
1490 amd_pstate_acpi_pm_profile_undefined())
1491 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1492 else
1493 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1494
1495 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1496 ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
1497 if (ret)
1498 return ret;
1499 WRITE_ONCE(cpudata->cppc_req_cached, value);
1500
1501 ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value);
1502 if (ret)
1503 return ret;
1504 WRITE_ONCE(cpudata->cppc_cap1_cached, value);
1505 }
1506
1507 current_pstate_driver->adjust_perf = NULL;
1508
1509 return 0;
1510
1511 free_cpudata1:
1512 kfree(cpudata);
1513 return ret;
1514 }
1515
1516 static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy)
1517 {
1518 struct amd_cpudata *cpudata = policy->driver_data;
1519
1520 if (cpudata) {
1521 kfree(cpudata);
1522 policy->driver_data = NULL;
1523 }
1524
1525 pr_debug("CPU %d exiting\n", policy->cpu);
1526 }
1527
1528 static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy)
1529 {
1530 struct amd_cpudata *cpudata = policy->driver_data;
1531 u32 max_perf, min_perf;
1532 u64 value;
1533 s16 epp;
1534
1535 max_perf = READ_ONCE(cpudata->highest_perf);
1536 min_perf = READ_ONCE(cpudata->lowest_perf);
1537 amd_pstate_update_min_max_limit(policy);
1538
1539 max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf,
1540 cpudata->max_limit_perf);
1541 min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf,
1542 cpudata->max_limit_perf);
1543 value = READ_ONCE(cpudata->cppc_req_cached);
1544
1545 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
1546 min_perf = min(cpudata->nominal_perf, max_perf);
1547
1548 /* Initial min/max values for CPPC Performance Controls Register */
1549 value &= ~AMD_CPPC_MIN_PERF(~0L);
1550 value |= AMD_CPPC_MIN_PERF(min_perf);
1551
1552 value &= ~AMD_CPPC_MAX_PERF(~0L);
1553 value |= AMD_CPPC_MAX_PERF(max_perf);
1554
1555 /* CPPC EPP feature require to set zero to the desire perf bit */
1556 value &= ~AMD_CPPC_DES_PERF(~0L);
1557 value |= AMD_CPPC_DES_PERF(0);
1558
1559 cpudata->epp_policy = cpudata->policy;
1560
1561 /* Get BIOS pre-defined epp value */
1562 epp = amd_pstate_get_epp(cpudata, value);
1563 if (epp < 0) {
1564 /**
1565 * This return value can only be negative for shared_memory
1566 * systems where EPP register read/write not supported.
1567 */
1568 return epp;
1569 }
1570
1571 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
1572 epp = 0;
1573
1574 WRITE_ONCE(cpudata->cppc_req_cached, value);
1575 return amd_pstate_set_epp(cpudata, epp);
1576 }
1577
1578 static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
1579 {
1580 struct amd_cpudata *cpudata = policy->driver_data;
1581 int ret;
1582
1583 if (!policy->cpuinfo.max_freq)
1584 return -ENODEV;
1585
1586 pr_debug("set_policy: cpuinfo.max %u policy->max %u\n",
1587 policy->cpuinfo.max_freq, policy->max);
1588
1589 cpudata->policy = policy->policy;
1590
1591 ret = amd_pstate_epp_update_limit(policy);
1592 if (ret)
1593 return ret;
1594
1595 /*
1596 * policy->cur is never updated with the amd_pstate_epp driver, but it
1597 * is used as a stale frequency value. So, keep it within limits.
1598 */
1599 policy->cur = policy->min;
1600
1601 return 0;
1602 }
1603
1604 static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
1605 {
1606 struct cppc_perf_ctrls perf_ctrls;
1607 u64 value, max_perf;
1608 int ret;
1609
1610 ret = amd_pstate_cppc_enable(true);
1611 if (ret)
1612 pr_err("failed to enable amd pstate during resume, return %d\n", ret);
1613
1614 value = READ_ONCE(cpudata->cppc_req_cached);
1615 max_perf = READ_ONCE(cpudata->highest_perf);
1616
1617 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1618 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
1619 } else {
1620 perf_ctrls.max_perf = max_perf;
1621 cppc_set_perf(cpudata->cpu, &perf_ctrls);
1622 perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
1623 cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
1624 }
1625 }
1626
1627 static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
1628 {
1629 struct amd_cpudata *cpudata = policy->driver_data;
1630
1631 pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
1632
1633 if (cppc_state == AMD_PSTATE_ACTIVE) {
1634 amd_pstate_epp_reenable(cpudata);
1635 cpudata->suspended = false;
1636 }
1637
1638 return 0;
1639 }
1640
1641 static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
1642 {
1643 struct amd_cpudata *cpudata = policy->driver_data;
1644 struct cppc_perf_ctrls perf_ctrls;
1645 int min_perf;
1646 u64 value;
1647
1648 min_perf = READ_ONCE(cpudata->lowest_perf);
1649 value = READ_ONCE(cpudata->cppc_req_cached);
1650
1651 mutex_lock(&amd_pstate_limits_lock);
1652 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1653 cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1654
1655 /* Set max perf same as min perf */
1656 value &= ~AMD_CPPC_MAX_PERF(~0L);
1657 value |= AMD_CPPC_MAX_PERF(min_perf);
1658 value &= ~AMD_CPPC_MIN_PERF(~0L);
1659 value |= AMD_CPPC_MIN_PERF(min_perf);
1660 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
1661 } else {
1662 perf_ctrls.desired_perf = 0;
1663 perf_ctrls.min_perf = min_perf;
1664 perf_ctrls.max_perf = min_perf;
1665 cppc_set_perf(cpudata->cpu, &perf_ctrls);
1666 perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
1667 cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
1668 }
1669 mutex_unlock(&amd_pstate_limits_lock);
1670 }
1671
1672 static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
1673 {
1674 struct amd_cpudata *cpudata = policy->driver_data;
1675
1676 pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu);
1677
1678 if (cpudata->suspended)
1679 return 0;
1680
1681 if (cppc_state == AMD_PSTATE_ACTIVE)
1682 amd_pstate_epp_offline(policy);
1683
1684 return 0;
1685 }
1686
1687 static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
1688 {
1689 struct amd_cpudata *cpudata = policy->driver_data;
1690 int ret;
1691
1692 /* avoid suspending when EPP is not enabled */
1693 if (cppc_state != AMD_PSTATE_ACTIVE)
1694 return 0;
1695
1696 /* set this flag to avoid setting core offline*/
1697 cpudata->suspended = true;
1698
1699 /* disable CPPC in lowlevel firmware */
1700 ret = amd_pstate_cppc_enable(false);
1701 if (ret)
1702 pr_err("failed to suspend, return %d\n", ret);
1703
1704 return 0;
1705 }
1706
1707 static int amd_pstate_epp_resume(struct cpufreq_policy *policy)
1708 {
1709 struct amd_cpudata *cpudata = policy->driver_data;
1710
1711 if (cpudata->suspended) {
1712 mutex_lock(&amd_pstate_limits_lock);
1713
1714 /* enable amd pstate from suspend state*/
1715 amd_pstate_epp_reenable(cpudata);
1716
1717 mutex_unlock(&amd_pstate_limits_lock);
1718
1719 cpudata->suspended = false;
1720 }
1721
1722 return 0;
1723 }
1724
1725 static struct cpufreq_driver amd_pstate_driver = {
1726 .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
1727 .verify = amd_pstate_verify,
1728 .target = amd_pstate_target,
1729 .fast_switch = amd_pstate_fast_switch,
1730 .init = amd_pstate_cpu_init,
1731 .exit = amd_pstate_cpu_exit,
1732 .suspend = amd_pstate_cpu_suspend,
1733 .resume = amd_pstate_cpu_resume,
1734 .set_boost = amd_pstate_set_boost,
1735 .update_limits = amd_pstate_update_limits,
1736 .name = "amd-pstate",
1737 .attr = amd_pstate_attr,
1738 };
1739
1740 static struct cpufreq_driver amd_pstate_epp_driver = {
1741 .flags = CPUFREQ_CONST_LOOPS,
1742 .verify = amd_pstate_verify,
1743 .setpolicy = amd_pstate_epp_set_policy,
1744 .init = amd_pstate_epp_cpu_init,
1745 .exit = amd_pstate_epp_cpu_exit,
1746 .offline = amd_pstate_epp_cpu_offline,
1747 .online = amd_pstate_epp_cpu_online,
1748 .suspend = amd_pstate_epp_suspend,
1749 .resume = amd_pstate_epp_resume,
1750 .update_limits = amd_pstate_update_limits,
1751 .set_boost = amd_pstate_set_boost,
1752 .name = "amd-pstate-epp",
1753 .attr = amd_pstate_epp_attr,
1754 };
1755
1756 /*
1757 * CPPC function is not supported for family ID 17H with model_ID ranging from 0x10 to 0x2F.
1758 * show the debug message that helps to check if the CPU has CPPC support for loading issue.
1759 */
1760 static bool amd_cppc_supported(void)
1761 {
1762 struct cpuinfo_x86 *c = &cpu_data(0);
1763 bool warn = false;
1764
1765 if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) {
1766 pr_debug_once("CPPC feature is not supported by the processor\n");
1767 return false;
1768 }
1769
1770 /*
1771 * If the CPPC feature is disabled in the BIOS for processors
1772 * that support MSR-based CPPC, the AMD Pstate driver may not
1773 * function correctly.
1774 *
1775 * For such processors, check the CPPC flag and display a
1776 * warning message if the platform supports CPPC.
1777 *
1778 * Note: The code check below will not abort the driver
1779 * registration process because of the code is added for
1780 * debugging purposes. Besides, it may still be possible for
1781 * the driver to work using the shared-memory mechanism.
1782 */
1783 if (!cpu_feature_enabled(X86_FEATURE_CPPC)) {
1784 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) {
1785 switch (c->x86_model) {
1786 case 0x60 ... 0x6F:
1787 case 0x80 ... 0xAF:
1788 warn = true;
1789 break;
1790 }
1791 } else if (cpu_feature_enabled(X86_FEATURE_ZEN3) ||
1792 cpu_feature_enabled(X86_FEATURE_ZEN4)) {
1793 switch (c->x86_model) {
1794 case 0x10 ... 0x1F:
1795 case 0x40 ... 0xAF:
1796 warn = true;
1797 break;
1798 }
1799 } else if (cpu_feature_enabled(X86_FEATURE_ZEN5)) {
1800 warn = true;
1801 }
1802 }
1803
1804 if (warn)
1805 pr_warn_once("The CPPC feature is supported but currently disabled by the BIOS.\n"
1806 "Please enable it if your BIOS has the CPPC option.\n");
1807 return true;
1808 }
1809
1810 static int __init amd_pstate_init(void)
1811 {
1812 struct device *dev_root;
1813 int ret;
1814
1815 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
1816 return -ENODEV;
1817
1818 /* show debug message only if CPPC is not supported */
1819 if (!amd_cppc_supported())
1820 return -EOPNOTSUPP;
1821
1822 /* show warning message when BIOS broken or ACPI disabled */
1823 if (!acpi_cpc_valid()) {
1824 pr_warn_once("the _CPC object is not present in SBIOS or ACPI disabled\n");
1825 return -ENODEV;
1826 }
1827
1828 /* don't keep reloading if cpufreq_driver exists */
1829 if (cpufreq_get_current_driver())
1830 return -EEXIST;
1831
1832 quirks = NULL;
1833
1834 /* check if this machine need CPPC quirks */
1835 dmi_check_system(amd_pstate_quirks_table);
1836
1837 /*
1838 * determine the driver mode from the command line or kernel config.
1839 * If no command line input is provided, cppc_state will be AMD_PSTATE_UNDEFINED.
1840 * command line options will override the kernel config settings.
1841 */
1842
1843 if (cppc_state == AMD_PSTATE_UNDEFINED) {
1844 /* Disable on the following configs by default:
1845 * 1. Undefined platforms
1846 * 2. Server platforms with CPUs older than Family 0x1A.
1847 */
1848 if (amd_pstate_acpi_pm_profile_undefined() ||
1849 (amd_pstate_acpi_pm_profile_server() && boot_cpu_data.x86 < 0x1A)) {
1850 pr_info("driver load is disabled, boot with specific mode to enable this\n");
1851 return -ENODEV;
1852 }
1853 /* get driver mode from kernel config option [1:4] */
1854 cppc_state = CONFIG_X86_AMD_PSTATE_DEFAULT_MODE;
1855 }
1856
1857 if (cppc_state == AMD_PSTATE_DISABLE) {
1858 pr_info("driver load is disabled, boot with specific mode to enable this\n");
1859 return -ENODEV;
1860 }
1861
1862 /* capability check */
1863 if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
1864 pr_debug("AMD CPPC MSR based functionality is supported\n");
1865 } else {
1866 pr_debug("AMD CPPC shared memory based functionality is supported\n");
1867 static_call_update(amd_pstate_cppc_enable, shmem_cppc_enable);
1868 static_call_update(amd_pstate_init_perf, shmem_init_perf);
1869 static_call_update(amd_pstate_update_perf, shmem_update_perf);
1870 }
1871
1872 ret = amd_pstate_register_driver(cppc_state);
1873 if (ret) {
1874 pr_err("failed to register with return %d\n", ret);
1875 return ret;
1876 }
1877
1878 if (amd_pstate_prefcore) {
1879 ret = amd_detect_prefcore(&amd_pstate_prefcore);
1880 if (ret)
1881 return ret;
1882 }
1883
1884 dev_root = bus_get_dev_root(&cpu_subsys);
1885 if (dev_root) {
1886 ret = sysfs_create_group(&dev_root->kobj, &amd_pstate_global_attr_group);
1887 put_device(dev_root);
1888 if (ret) {
1889 pr_err("sysfs attribute export failed with error %d.\n", ret);
1890 goto global_attr_free;
1891 }
1892 }
1893
1894 return ret;
1895
1896 global_attr_free:
1897 cpufreq_unregister_driver(current_pstate_driver);
1898 amd_pstate_cppc_enable(false);
1899 return ret;
1900 }
1901 device_initcall(amd_pstate_init);
1902
1903 static int __init amd_pstate_param(char *str)
1904 {
1905 size_t size;
1906 int mode_idx;
1907
1908 if (!str)
1909 return -EINVAL;
1910
1911 size = strlen(str);
1912 mode_idx = get_mode_idx_from_str(str, size);
1913
1914 return amd_pstate_set_driver(mode_idx);
1915 }
1916
1917 static int __init amd_prefcore_param(char *str)
1918 {
1919 if (!strcmp(str, "disable"))
1920 amd_pstate_prefcore = false;
1921
1922 return 0;
1923 }
1924
1925 early_param("amd_pstate", amd_pstate_param);
1926 early_param("amd_prefcore", amd_prefcore_param);
1927
1928 MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
1929 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
Kernel DRM miscellaneous fixes and cross-tree changes