drivers/crypto/hisilicon/zip/zip.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2019 HiSilicon Limited. */
   3 #ifndef HISI_ZIP_H
   4 #define HISI_ZIP_H
   5
   6 #undef pr_fmt
   7 #define pr_fmt(fmt)     "hisi_zip: " fmt
   8
   9 #include <linux/list.h>
  10 #include <linux/hisi_acc_qm.h>
  11
  12 enum hisi_zip_error_type {
  13         /* negative compression */
  14         HZIP_NC_ERR = 0x0d,
  15 };
  16
  17 struct hisi_zip_dfx {
  18         atomic64_t send_cnt;
  19         atomic64_t recv_cnt;
  20         atomic64_t send_busy_cnt;
  21         atomic64_t err_bd_cnt;
  22 };
  23
  24 struct hisi_zip_ctrl;
  25
  26 struct hisi_zip {
  27         struct hisi_qm qm;
  28         struct hisi_zip_ctrl *ctrl;
  29         struct hisi_zip_dfx dfx;
  30 };
  31
  32 struct hisi_zip_sqe {
  33         u32 consumed;
  34         u32 produced;
  35         u32 comp_data_length;
  36         /*
  37          * status: 0~7 bits
  38          * rsvd: 8~31 bits
  39          */
  40         u32 dw3;
  41         u32 input_data_length;
  42         u32 dw5;
  43         u32 dw6;
  44         /*
  45          * in_sge_data_offset: 0~23 bits
  46          * rsvd: 24~27 bits
  47          * sqe_type: 29~31 bits
  48          */
  49         u32 dw7;
  50         /*
  51          * out_sge_data_offset: 0~23 bits
  52          * rsvd: 24~31 bits
  53          */
  54         u32 dw8;
  55         /*
  56          * request_type: 0~7 bits
  57          * buffer_type: 8~11 bits
  58          * rsvd: 13~31 bits
  59          */
  60         u32 dw9;
  61         u32 dw10;
  62         u32 dw11;
  63         u32 dw12;
  64         /* tag: in sqe type 0 */
  65         u32 dw13;
  66         u32 dest_avail_out;
  67         u32 dw15;
  68         u32 dw16;
  69         u32 dw17;
  70         u32 source_addr_l;
  71         u32 source_addr_h;
  72         u32 dest_addr_l;
  73         u32 dest_addr_h;
  74         u32 dw22;
  75         u32 dw23;
  76         u32 dw24;
  77         u32 dw25;
  78         /* tag: in sqe type 3 */
  79         u32 dw26;
  80         u32 dw27;
  81         u32 rsvd1[4];
  82 };
  83
  84 enum zip_cap_table_type {
  85         QM_RAS_NFE_TYPE,
  86         QM_RAS_NFE_RESET,
  87         QM_RAS_CE_TYPE,
  88         ZIP_RAS_NFE_TYPE,
  89         ZIP_RAS_NFE_RESET,
  90         ZIP_RAS_CE_TYPE,
  91         ZIP_CORE_INFO,
  92         ZIP_CORE_EN,
  93         ZIP_DRV_ALG_BITMAP_TB,
  94         ZIP_ALG_BITMAP,
  95         ZIP_CORE1_BITMAP,
  96         ZIP_CORE2_BITMAP,
  97         ZIP_CORE3_BITMAP,
  98         ZIP_CORE4_BITMAP,
  99         ZIP_CORE5_BITMAP,
 100 };
 101
 102 int zip_create_qps(struct hisi_qp **qps, int qp_num, int node);
 103 int hisi_zip_register_to_crypto(struct hisi_qm *qm);
 104 void hisi_zip_unregister_from_crypto(struct hisi_qm *qm);
 105 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg);
 106 #endif