drivers/cxl/cxlpci.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */
   3 #ifndef __CXL_PCI_H__
   4 #define __CXL_PCI_H__
   5 #include <linux/pci.h>
   6 #include "cxl.h"
   7
   8 #define CXL_MEMORY_PROGIF       0x10
   9
  10 /*
  11  * See section 8.1 Configuration Space Registers in the CXL 2.0
  12  * Specification. Names are taken straight from the specification with "CXL" and
  13  * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
  14  */
  15 #define PCI_DVSEC_HEADER1_LENGTH_MASK   GENMASK(31, 20)
  16
  17 /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
  18 #define CXL_DVSEC_PCIE_DEVICE                                   0
  19 #define   CXL_DVSEC_CAP_OFFSET          0xA
  20 #define     CXL_DVSEC_MEM_CAPABLE       BIT(2)
  21 #define     CXL_DVSEC_HDM_COUNT_MASK    GENMASK(5, 4)
  22 #define   CXL_DVSEC_CTRL_OFFSET         0xC
  23 #define     CXL_DVSEC_MEM_ENABLE        BIT(2)
  24 #define   CXL_DVSEC_RANGE_SIZE_HIGH(i)  (0x18 + (i * 0x10))
  25 #define   CXL_DVSEC_RANGE_SIZE_LOW(i)   (0x1C + (i * 0x10))
  26 #define     CXL_DVSEC_MEM_INFO_VALID    BIT(0)
  27 #define     CXL_DVSEC_MEM_ACTIVE        BIT(1)
  28 #define     CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28)
  29 #define   CXL_DVSEC_RANGE_BASE_HIGH(i)  (0x20 + (i * 0x10))
  30 #define   CXL_DVSEC_RANGE_BASE_LOW(i)   (0x24 + (i * 0x10))
  31 #define     CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28)
  32
  33 #define CXL_DVSEC_RANGE_MAX             2
  34
  35 /* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
  36 #define CXL_DVSEC_FUNCTION_MAP                                  2
  37
  38 /* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
  39 #define CXL_DVSEC_PORT_EXTENSIONS                               3
  40
  41 /* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
  42 #define CXL_DVSEC_PORT_GPF                                      4
  43
  44 /* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
  45 #define CXL_DVSEC_DEVICE_GPF                                    5
  46
  47 /* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
  48 #define CXL_DVSEC_PCIE_FLEXBUS_PORT                             7
  49
  50 /* CXL 2.0 8.1.9: Register Locator DVSEC */
  51 #define CXL_DVSEC_REG_LOCATOR                                   8
  52 #define   CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET                   0xC
  53 #define     CXL_DVSEC_REG_LOCATOR_BIR_MASK                      GENMASK(2, 0)
  54 #define     CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK                 GENMASK(15, 8)
  55 #define     CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK            GENMASK(31, 16)
  56
  57 /*
  58  * NOTE: Currently all the functions which are enabled for CXL require their
  59  * vectors to be in the first 16.  Use this as the default max.
  60  */
  61 #define CXL_PCI_DEFAULT_MAX_VECTORS 16
  62
  63 /* Register Block Identifier (RBI) */
  64 enum cxl_regloc_type {
  65         CXL_REGLOC_RBI_EMPTY = 0,
  66         CXL_REGLOC_RBI_COMPONENT,
  67         CXL_REGLOC_RBI_VIRT,
  68         CXL_REGLOC_RBI_MEMDEV,
  69         CXL_REGLOC_RBI_PMU,
  70         CXL_REGLOC_RBI_TYPES
  71 };
  72
  73 /*
  74  * Table Access DOE, CDAT Read Entry Response
  75  *
  76  * Spec refs:
  77  *
  78  * CXL 3.1 8.1.11, Table 8-14: Read Entry Response
  79  * CDAT Specification 1.03: 2 CDAT Data Structures
  80  */
  81
  82 struct cdat_header {
  83         __le32 length;
  84         u8 revision;
  85         u8 checksum;
  86         u8 reserved[6];
  87         __le32 sequence;
  88 } __packed;
  89
  90 struct cdat_entry_header {
  91         u8 type;
  92         u8 reserved;
  93         __le16 length;
  94 } __packed;
  95
  96 /*
  97  * The DOE CDAT read response contains a CDAT read entry (either the
  98  * CDAT header or a structure).
  99  */
 100 union cdat_data {
 101         struct cdat_header header;
 102         struct cdat_entry_header entry;
 103 } __packed;
 104
 105 /* There is an additional CDAT response header of 4 bytes. */
 106 struct cdat_doe_rsp {
 107         __le32 doe_header;
 108         u8 data[];
 109 } __packed;
 110
 111 /*
 112  * CXL v3.0 6.2.3 Table 6-4
 113  * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits
 114  * mode, otherwise it's 68B flits mode.
 115  */
 116 static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
 117 {
 118         u16 lnksta2;
 119
 120         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2);
 121         return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
 122 }
 123
 124 int devm_cxl_port_enumerate_dports(struct cxl_port *port);
 125 struct cxl_dev_state;
 126 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
 127                         struct cxl_endpoint_dvsec_info *info);
 128 void read_cdat_data(struct cxl_port *port);
 129 void cxl_cor_error_detected(struct pci_dev *pdev);
 130 pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
 131                                     pci_channel_state_t state);
 132 #endif /* __CXL_PCI_H__ */