drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright 2019 NXP */
   3
   4 #ifndef __DPAA2_QDMA_H
   5 #define __DPAA2_QDMA_H
   6
   7 #define DPAA2_QDMA_STORE_SIZE 16
   8 #define NUM_CH 8
   9 #define DPAA2_QDMA_DEFAULT_PRIORITY 0
  10
  11 struct dpaa2_qdma_sd_d {
  12         u32 rsv:32;
  13         union {
  14                 struct {
  15                         u32 ssd:12; /* source stride distance */
  16                         u32 sss:12; /* source stride size */
  17                         u32 rsv1:8;
  18                 } sdf;
  19                 struct {
  20                         u32 dsd:12; /* Destination stride distance */
  21                         u32 dss:12; /* Destination stride size */
  22                         u32 rsv2:8;
  23                 } ddf;
  24         } df;
  25         u32 rbpcmd;     /* Route-by-port command */
  26         u32 cmd;
  27 } __attribute__((__packed__));
  28
  29 /* Source descriptor command read transaction type for RBP=0: */
  30 /* coherent copy of cacheable memory */
  31 #define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28)
  32 /* Destination descriptor command write transaction type for RBP=0: */
  33 /* coherent copy of cacheable memory */
  34 #define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28)
  35 #define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28)
  36
  37 #define QMAN_FD_FMT_ENABLE      BIT(0) /* frame list table enable */
  38 #define QMAN_FD_BMT_ENABLE      BIT(15) /* bypass memory translation */
  39 #define QMAN_FD_BMT_DISABLE     (0) /* bypass memory translation */
  40 #define QMAN_FD_SL_DISABLE      (0) /* short lengthe disabled */
  41 #define QMAN_FD_SL_ENABLE       BIT(14) /* short lengthe enabled */
  42
  43 #define QDMA_FINAL_BIT_DISABLE  (0) /* final bit disable */
  44 #define QDMA_FINAL_BIT_ENABLE   BIT(31) /* final bit enable */
  45
  46 #define QDMA_FD_SHORT_FORMAT    BIT(11) /* short format */
  47 #define QDMA_FD_LONG_FORMAT     (0) /* long format */
  48 #define QDMA_SER_DISABLE        (8) /* no notification */
  49 #define QDMA_SER_CTX            BIT(8) /* notification by FQD_CTX[fqid] */
  50 #define QDMA_SER_DEST           (2 << 8) /* notification by destination desc */
  51 #define QDMA_SER_BOTH           (3 << 8) /* source and dest notification */
  52 #define QDMA_FD_SPF_ENALBE      BIT(30) /* source prefetch enable */
  53
  54 #define QMAN_FD_VA_ENABLE       BIT(14) /* Address used is virtual address */
  55 #define QMAN_FD_VA_DISABLE      (0)/* Address used is a real address */
  56 /* Flow Context: 49bit physical address */
  57 #define QMAN_FD_CBMT_ENABLE     BIT(15)
  58 #define QMAN_FD_CBMT_DISABLE    (0) /* Flow Context: 64bit virtual address */
  59 #define QMAN_FD_SC_DISABLE      (0) /* stashing control */
  60
  61 #define QDMA_FL_FMT_SBF         (0x0) /* Single buffer frame */
  62 #define QDMA_FL_FMT_SGE         (0x2) /* Scatter gather frame */
  63 #define QDMA_FL_BMT_ENABLE      BIT(15) /* enable bypass memory translation */
  64 #define QDMA_FL_BMT_DISABLE     (0x0) /* enable bypass memory translation */
  65 #define QDMA_FL_SL_LONG         (0x0)/* long length */
  66 #define QDMA_FL_SL_SHORT        (0x1) /* short length */
  67 #define QDMA_FL_F               (0x1)/* last frame list bit */
  68
  69 /*Description of Frame list table structure*/
  70 struct dpaa2_qdma_chan {
  71         struct dpaa2_qdma_engine        *qdma;
  72         struct virt_dma_chan            vchan;
  73         struct virt_dma_desc            vdesc;
  74         enum dma_status                 status;
  75         u32                             fqid;
  76
  77         /* spinlock used by dpaa2 qdma driver */
  78         spinlock_t                      queue_lock;
  79         struct dma_pool                 *fd_pool;
  80         struct dma_pool                 *fl_pool;
  81         struct dma_pool                 *sdd_pool;
  82
  83         struct list_head                comp_used;
  84         struct list_head                comp_free;
  85
  86 };
  87
  88 struct dpaa2_qdma_comp {
  89         dma_addr_t              fd_bus_addr;
  90         dma_addr_t              fl_bus_addr;
  91         dma_addr_t              desc_bus_addr;
  92         struct dpaa2_fd         *fd_virt_addr;
  93         struct dpaa2_fl_entry   *fl_virt_addr;
  94         struct dpaa2_qdma_sd_d  *desc_virt_addr;
  95         struct dpaa2_qdma_chan  *qchan;
  96         struct virt_dma_desc    vdesc;
  97         struct list_head        list;
  98 };
  99
 100 struct dpaa2_qdma_engine {
 101         struct dma_device       dma_dev;
 102         u32                     n_chans;
 103         struct dpaa2_qdma_chan  chans[NUM_CH];
 104         int                     qdma_wrtype_fixup;
 105         int                     desc_allocated;
 106
 107         struct dpaa2_qdma_priv *priv;
 108 };
 109
 110 /*
 111  * dpaa2_qdma_priv - driver private data
 112  */
 113 struct dpaa2_qdma_priv {
 114         int dpqdma_id;
 115
 116         struct iommu_domain     *iommu_domain;
 117         struct dpdmai_attr      dpdmai_attr;
 118         struct device           *dev;
 119         struct fsl_mc_io        *mc_io;
 120         struct fsl_mc_device    *dpdmai_dev;
 121         u8                      num_pairs;
 122
 123         struct dpaa2_qdma_engine        *dpaa2_qdma;
 124         struct dpaa2_qdma_priv_per_prio *ppriv;
 125
 126         struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_MAX_QUEUE_NUM];
 127         struct dpdmai_tx_queue_attr tx_queue_attr[DPDMAI_MAX_QUEUE_NUM];
 128 };
 129
 130 struct dpaa2_qdma_priv_per_prio {
 131         int req_fqid;
 132         int rsp_fqid;
 133         int prio;
 134
 135         struct dpaa2_io_store *store;
 136         struct dpaa2_io_notification_ctx nctx;
 137
 138         struct dpaa2_qdma_priv *priv;
 139 };
 140
 141 static struct soc_device_attribute soc_fixup_tuning[] = {
 142         { .family = "QorIQ LX2160A"},
 143         { /* sentinel */ }
 144 };
 145
 146 /* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */
 147 #define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \
 148                 sizeof(struct dpaa2_fl_entry) * 3 + \
 149                 sizeof(struct dpaa2_qdma_sd_d) * 2)
 150
 151 static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma);
 152 static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan,
 153                                    struct list_head *head);
 154 #endif /* __DPAA2_QDMA_H */