1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCI driver for the High Speed UART DMA
5 * Copyright (C) 2015 Intel Corporation
6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8 * Partially based on the bits found in drivers/tty/serial/mfd.c.
11 #include <linux/bitops.h>
12 #include <linux/device.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
19 #define HSU_PCI_DMASR 0x00
20 #define HSU_PCI_DMAISR 0x04
22 #define HSU_PCI_CHAN_OFFSET 0x100
24 #define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA 0x081e
25 #define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA 0x1192
27 static irqreturn_t
hsu_pci_irq(int irq
, void *dev
)
29 struct hsu_dma_chip
*chip
= dev
;
36 dmaisr
= readl(chip
->regs
+ HSU_PCI_DMAISR
);
37 for_each_set_bit(i
, &dmaisr
, chip
->hsu
->nr_channels
) {
38 err
= hsu_dma_get_status(chip
, i
, &status
);
42 ret
|= hsu_dma_do_irq(chip
, i
, status
);
45 return IRQ_RETVAL(ret
);
48 static void hsu_pci_dma_remove(void *chip
)
53 static int hsu_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
55 struct device
*dev
= &pdev
->dev
;
56 struct hsu_dma_chip
*chip
;
59 ret
= pcim_enable_device(pdev
);
63 ret
= pcim_iomap_regions(pdev
, BIT(0), pci_name(pdev
));
65 dev_err(&pdev
->dev
, "I/O memory remapping failed\n");
70 pci_try_set_mwi(pdev
);
72 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
76 chip
= devm_kzalloc(&pdev
->dev
, sizeof(*chip
), GFP_KERNEL
);
80 ret
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
84 chip
->dev
= &pdev
->dev
;
85 chip
->regs
= pcim_iomap_table(pdev
)[0];
86 chip
->length
= pci_resource_len(pdev
, 0);
87 chip
->offset
= HSU_PCI_CHAN_OFFSET
;
88 chip
->irq
= pci_irq_vector(pdev
, 0);
90 ret
= hsu_dma_probe(chip
);
94 ret
= devm_add_action_or_reset(dev
, hsu_pci_dma_remove
, chip
);
98 ret
= devm_request_irq(dev
, chip
->irq
, hsu_pci_irq
, 0, "hsu_dma_pci", chip
);
103 * On Intel Tangier B0 and Anniedale the interrupt line, disregarding
104 * to have different numbers, is shared between HSU DMA and UART IPs.
105 * Thus on such SoCs we are expecting that IRQ handler is called in
106 * UART driver only. Instead of handling the spurious interrupt
107 * from HSU DMA here and waste CPU time and delay HSU UART interrupt
108 * handling, disable the interrupt entirely.
110 if (pdev
->device
== PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA
)
111 disable_irq_nosync(chip
->irq
);
113 pci_set_drvdata(pdev
, chip
);
118 static const struct pci_device_id hsu_pci_id_table
[] = {
119 { PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA
), 0 },
120 { PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA
), 0 },
123 MODULE_DEVICE_TABLE(pci
, hsu_pci_id_table
);
125 static struct pci_driver hsu_pci_driver
= {
126 .name
= "hsu_dma_pci",
127 .id_table
= hsu_pci_id_table
,
128 .probe
= hsu_pci_probe
,
131 module_pci_driver(hsu_pci_driver
);
133 MODULE_LICENSE("GPL v2");
134 MODULE_DESCRIPTION("High Speed UART DMA PCI driver");
135 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");