drivers/dma/ppc4xx/xor.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * 440SPe's XOR engines support header file
   4  *
   5  * 2006-2009 (C) DENX Software Engineering.
   6  *
   7  * Author: Yuri Tikhonov <yur@emcraft.com>
   8  */
   9
  10 #ifndef _PPC440SPE_XOR_H
  11 #define _PPC440SPE_XOR_H
  12
  13 #include <linux/types.h>
  14
  15 /* Number of XOR engines available on the contoller */
  16 #define XOR_ENGINES_NUM         1
  17
  18 /* Number of operands supported in the h/w */
  19 #define XOR_MAX_OPS             16
  20
  21 /*
  22  * XOR Command Block Control Register bits
  23  */
  24 #define XOR_CBCR_LNK_BIT        (1<<31) /* link present */
  25 #define XOR_CBCR_TGT_BIT        (1<<30) /* target present */
  26 #define XOR_CBCR_CBCE_BIT       (1<<29) /* command block compete enable */
  27 #define XOR_CBCR_RNZE_BIT       (1<<28) /* result not zero enable */
  28 #define XOR_CBCR_XNOR_BIT       (1<<15) /* XOR/XNOR */
  29 #define XOR_CDCR_OAC_MSK        (0x7F)  /* operand address count */
  30
  31 /*
  32  * XORCore Status Register bits
  33  */
  34 #define XOR_SR_XCP_BIT          (1<<31) /* core processing */
  35 #define XOR_SR_ICB_BIT          (1<<17) /* invalid CB */
  36 #define XOR_SR_IC_BIT           (1<<16) /* invalid command */
  37 #define XOR_SR_IPE_BIT          (1<<15) /* internal parity error */
  38 #define XOR_SR_RNZ_BIT          (1<<2)  /* result not Zero */
  39 #define XOR_SR_CBC_BIT          (1<<1)  /* CB complete */
  40 #define XOR_SR_CBLC_BIT         (1<<0)  /* CB list complete */
  41
  42 /*
  43  * XORCore Control Set and Reset Register bits
  44  */
  45 #define XOR_CRSR_XASR_BIT       (1<<31) /* soft reset */
  46 #define XOR_CRSR_XAE_BIT        (1<<30) /* enable */
  47 #define XOR_CRSR_RCBE_BIT       (1<<29) /* refetch CB enable */
  48 #define XOR_CRSR_PAUS_BIT       (1<<28) /* pause */
  49 #define XOR_CRSR_64BA_BIT       (1<<27) /* 64/32 CB format */
  50 #define XOR_CRSR_CLP_BIT        (1<<25) /* continue list processing */
  51
  52 /*
  53  * XORCore Interrupt Enable Register
  54  */
  55 #define XOR_IE_ICBIE_BIT        (1<<17) /* Invalid Command Block IRQ Enable */
  56 #define XOR_IE_ICIE_BIT         (1<<16) /* Invalid Command IRQ Enable */
  57 #define XOR_IE_RPTIE_BIT        (1<<14) /* Read PLB Timeout Error IRQ Enable */
  58 #define XOR_IE_CBCIE_BIT        (1<<1)  /* CB complete interrupt enable */
  59 #define XOR_IE_CBLCI_BIT        (1<<0)  /* CB list complete interrupt enable */
  60
  61 /*
  62  * XOR Accelerator engine Command Block Type
  63  */
  64 struct xor_cb {
  65         /*
  66          * Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf)
  67          */
  68         u32     cbc;            /* control */
  69         u32     cbbc;           /* byte count */
  70         u32     cbs;            /* status */
  71         u8      pad0[4];        /* reserved */
  72         u32     cbtah;          /* target address high */
  73         u32     cbtal;          /* target address low */
  74         u32     cblah;          /* link address high */
  75         u32     cblal;          /* link address low */
  76         struct {
  77                 u32 h;
  78                 u32 l;
  79         } __attribute__ ((packed)) ops[16];
  80 } __attribute__ ((packed));
  81
  82 /*
  83  * XOR hardware registers Table 19-3, UM 1.22
  84  */
  85 struct xor_regs {
  86         u32     op_ar[16][2];   /* operand address[0]-high,[1]-low registers */
  87         u8      pad0[352];      /* reserved */
  88         u32     cbcr;           /* CB control register */
  89         u32     cbbcr;          /* CB byte count register */
  90         u32     cbsr;           /* CB status register */
  91         u8      pad1[4];        /* reserved */
  92         u32     cbtahr;         /* operand target address high register */
  93         u32     cbtalr;         /* operand target address low register */
  94         u32     cblahr;         /* CB link address high register */
  95         u32     cblalr;         /* CB link address low register */
  96         u32     crsr;           /* control set register */
  97         u32     crrr;           /* control reset register */
  98         u32     ccbahr;         /* current CB address high register */
  99         u32     ccbalr;         /* current CB address low register */
 100         u32     plbr;           /* PLB configuration register */
 101         u32     ier;            /* interrupt enable register */
 102         u32     pecr;           /* parity error count register */
 103         u32     sr;             /* status register */
 104         u32     revidr;         /* revision ID register */
 105 };
 106
 107 #endif /* _PPC440SPE_XOR_H */