drivers/firewire/ohci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _FIREWIRE_OHCI_H
   3 #define _FIREWIRE_OHCI_H
   4
   5 /* OHCI register map */
   6
   7 #define OHCI1394_Version                      0x000
   8 #define OHCI1394_GUID_ROM                     0x004
   9 #define OHCI1394_ATRetries                    0x008
  10 #define OHCI1394_CSRData                      0x00C
  11 #define OHCI1394_CSRCompareData               0x010
  12 #define OHCI1394_CSRControl                   0x014
  13 #define OHCI1394_ConfigROMhdr                 0x018
  14 #define OHCI1394_BusID                        0x01C
  15 #define OHCI1394_BusOptions                   0x020
  16 #define OHCI1394_GUIDHi                       0x024
  17 #define OHCI1394_GUIDLo                       0x028
  18 #define OHCI1394_ConfigROMmap                 0x034
  19 #define OHCI1394_PostedWriteAddressLo         0x038
  20 #define OHCI1394_PostedWriteAddressHi         0x03C
  21 #define OHCI1394_VendorID                     0x040
  22 #define OHCI1394_HCControlSet                 0x050
  23 #define OHCI1394_HCControlClear               0x054
  24 #define  OHCI1394_HCControl_BIBimageValid       0x80000000
  25 #define  OHCI1394_HCControl_noByteSwapData      0x40000000
  26 #define  OHCI1394_HCControl_programPhyEnable    0x00800000
  27 #define  OHCI1394_HCControl_aPhyEnhanceEnable   0x00400000
  28 #define  OHCI1394_HCControl_LPS                 0x00080000
  29 #define  OHCI1394_HCControl_postedWriteEnable   0x00040000
  30 #define  OHCI1394_HCControl_linkEnable          0x00020000
  31 #define  OHCI1394_HCControl_softReset           0x00010000
  32 #define OHCI1394_SelfIDBuffer                 0x064
  33 #define OHCI1394_SelfIDCount                  0x068
  34 #define OHCI1394_IRMultiChanMaskHiSet         0x070
  35 #define OHCI1394_IRMultiChanMaskHiClear       0x074
  36 #define OHCI1394_IRMultiChanMaskLoSet         0x078
  37 #define OHCI1394_IRMultiChanMaskLoClear       0x07C
  38 #define OHCI1394_IntEventSet                  0x080
  39 #define OHCI1394_IntEventClear                0x084
  40 #define OHCI1394_IntMaskSet                   0x088
  41 #define OHCI1394_IntMaskClear                 0x08C
  42 #define OHCI1394_IsoXmitIntEventSet           0x090
  43 #define OHCI1394_IsoXmitIntEventClear         0x094
  44 #define OHCI1394_IsoXmitIntMaskSet            0x098
  45 #define OHCI1394_IsoXmitIntMaskClear          0x09C
  46 #define OHCI1394_IsoRecvIntEventSet           0x0A0
  47 #define OHCI1394_IsoRecvIntEventClear         0x0A4
  48 #define OHCI1394_IsoRecvIntMaskSet            0x0A8
  49 #define OHCI1394_IsoRecvIntMaskClear          0x0AC
  50 #define OHCI1394_InitialBandwidthAvailable    0x0B0
  51 #define OHCI1394_InitialChannelsAvailableHi   0x0B4
  52 #define OHCI1394_InitialChannelsAvailableLo   0x0B8
  53 #define OHCI1394_FairnessControl              0x0DC
  54 #define OHCI1394_LinkControlSet               0x0E0
  55 #define OHCI1394_LinkControlClear             0x0E4
  56 #define   OHCI1394_LinkControl_rcvSelfID        (1 << 9)
  57 #define   OHCI1394_LinkControl_rcvPhyPkt        (1 << 10)
  58 #define   OHCI1394_LinkControl_cycleTimerEnable (1 << 20)
  59 #define   OHCI1394_LinkControl_cycleMaster      (1 << 21)
  60 #define   OHCI1394_LinkControl_cycleSource      (1 << 22)
  61 #define OHCI1394_NodeID                       0x0E8
  62 #define   OHCI1394_NodeID_idValid             0x80000000
  63 #define   OHCI1394_NodeID_root                0x40000000
  64 #define   OHCI1394_NodeID_nodeNumber          0x0000003f
  65 #define   OHCI1394_NodeID_busNumber           0x0000ffc0
  66 #define OHCI1394_PhyControl                   0x0EC
  67 #define   OHCI1394_PhyControl_Read(addr)        (((addr) << 8) | 0x00008000)
  68 #define   OHCI1394_PhyControl_ReadDone          0x80000000
  69 #define   OHCI1394_PhyControl_ReadData(r)       (((r) & 0x00ff0000) >> 16)
  70 #define   OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000)
  71 #define   OHCI1394_PhyControl_WritePending      0x00004000
  72 #define OHCI1394_IsochronousCycleTimer        0x0F0
  73 #define OHCI1394_AsReqFilterHiSet             0x100
  74 #define OHCI1394_AsReqFilterHiClear           0x104
  75 #define OHCI1394_AsReqFilterLoSet             0x108
  76 #define OHCI1394_AsReqFilterLoClear           0x10C
  77 #define OHCI1394_PhyReqFilterHiSet            0x110
  78 #define OHCI1394_PhyReqFilterHiClear          0x114
  79 #define OHCI1394_PhyReqFilterLoSet            0x118
  80 #define OHCI1394_PhyReqFilterLoClear          0x11C
  81 #define OHCI1394_PhyUpperBound                0x120
  82
  83 #define OHCI1394_AsReqTrContextBase           0x180
  84 #define OHCI1394_AsReqTrContextControlSet     0x180
  85 #define OHCI1394_AsReqTrContextControlClear   0x184
  86 #define OHCI1394_AsReqTrCommandPtr            0x18C
  87
  88 #define OHCI1394_AsRspTrContextBase           0x1A0
  89 #define OHCI1394_AsRspTrContextControlSet     0x1A0
  90 #define OHCI1394_AsRspTrContextControlClear   0x1A4
  91 #define OHCI1394_AsRspTrCommandPtr            0x1AC
  92
  93 #define OHCI1394_AsReqRcvContextBase          0x1C0
  94 #define OHCI1394_AsReqRcvContextControlSet    0x1C0
  95 #define OHCI1394_AsReqRcvContextControlClear  0x1C4
  96 #define OHCI1394_AsReqRcvCommandPtr           0x1CC
  97
  98 #define OHCI1394_AsRspRcvContextBase          0x1E0
  99 #define OHCI1394_AsRspRcvContextControlSet    0x1E0
 100 #define OHCI1394_AsRspRcvContextControlClear  0x1E4
 101 #define OHCI1394_AsRspRcvCommandPtr           0x1EC
 102
 103 /* Isochronous transmit registers */
 104 #define OHCI1394_IsoXmitContextBase(n)           (0x200 + 16 * (n))
 105 #define OHCI1394_IsoXmitContextControlSet(n)     (0x200 + 16 * (n))
 106 #define OHCI1394_IsoXmitContextControlClear(n)   (0x204 + 16 * (n))
 107 #define OHCI1394_IsoXmitCommandPtr(n)            (0x20C + 16 * (n))
 108
 109 /* Isochronous receive registers */
 110 #define OHCI1394_IsoRcvContextBase(n)         (0x400 + 32 * (n))
 111 #define OHCI1394_IsoRcvContextControlSet(n)   (0x400 + 32 * (n))
 112 #define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
 113 #define OHCI1394_IsoRcvCommandPtr(n)          (0x40C + 32 * (n))
 114 #define OHCI1394_IsoRcvContextMatch(n)        (0x410 + 32 * (n))
 115
 116 /* Interrupts Mask/Events */
 117 #define OHCI1394_reqTxComplete          0x00000001
 118 #define OHCI1394_respTxComplete         0x00000002
 119 #define OHCI1394_ARRQ                   0x00000004
 120 #define OHCI1394_ARRS                   0x00000008
 121 #define OHCI1394_RQPkt                  0x00000010
 122 #define OHCI1394_RSPkt                  0x00000020
 123 #define OHCI1394_isochTx                0x00000040
 124 #define OHCI1394_isochRx                0x00000080
 125 #define OHCI1394_postedWriteErr         0x00000100
 126 #define OHCI1394_lockRespErr            0x00000200
 127 #define OHCI1394_selfIDComplete         0x00010000
 128 #define OHCI1394_busReset               0x00020000
 129 #define OHCI1394_regAccessFail          0x00040000
 130 #define OHCI1394_phy                    0x00080000
 131 #define OHCI1394_cycleSynch             0x00100000
 132 #define OHCI1394_cycle64Seconds         0x00200000
 133 #define OHCI1394_cycleLost              0x00400000
 134 #define OHCI1394_cycleInconsistent      0x00800000
 135 #define OHCI1394_unrecoverableError     0x01000000
 136 #define OHCI1394_cycleTooLong           0x02000000
 137 #define OHCI1394_phyRegRcvd             0x04000000
 138 #define OHCI1394_masterIntEnable        0x80000000
 139
 140 #define OHCI1394_evt_no_status          0x0
 141 #define OHCI1394_evt_long_packet        0x2
 142 #define OHCI1394_evt_missing_ack        0x3
 143 #define OHCI1394_evt_underrun           0x4
 144 #define OHCI1394_evt_overrun            0x5
 145 #define OHCI1394_evt_descriptor_read    0x6
 146 #define OHCI1394_evt_data_read          0x7
 147 #define OHCI1394_evt_data_write         0x8
 148 #define OHCI1394_evt_bus_reset          0x9
 149 #define OHCI1394_evt_timeout            0xa
 150 #define OHCI1394_evt_tcode_err          0xb
 151 #define OHCI1394_evt_reserved_b         0xc
 152 #define OHCI1394_evt_reserved_c         0xd
 153 #define OHCI1394_evt_unknown            0xe
 154 #define OHCI1394_evt_flushed            0xf
 155
 156
 157 // Asynchronous Transmit DMA.
 158 //
 159 // The content of first two quadlets of data for AT DMA is different from the header for IEEE 1394
 160 // asynchronous packet.
 161
 162 #define OHCI1394_AT_DATA_Q0_srcBusID_MASK               0x00800000
 163 #define OHCI1394_AT_DATA_Q0_srcBusID_SHIFT              23
 164 #define OHCI1394_AT_DATA_Q0_spd_MASK                    0x00070000
 165 #define OHCI1394_AT_DATA_Q0_spd_SHIFT                   16
 166 #define OHCI1394_AT_DATA_Q0_tLabel_MASK                 0x0000fc00
 167 #define OHCI1394_AT_DATA_Q0_tLabel_SHIFT                10
 168 #define OHCI1394_AT_DATA_Q0_rt_MASK                     0x00000300
 169 #define OHCI1394_AT_DATA_Q0_rt_SHIFT                    8
 170 #define OHCI1394_AT_DATA_Q0_tCode_MASK                  0x000000f0
 171 #define OHCI1394_AT_DATA_Q0_tCode_SHIFT                 4
 172 #define OHCI1394_AT_DATA_Q1_destinationId_MASK          0xffff0000
 173 #define OHCI1394_AT_DATA_Q1_destinationId_SHIFT         16
 174 #define OHCI1394_AT_DATA_Q1_destinationOffsetHigh_MASK  0x0000ffff
 175 #define OHCI1394_AT_DATA_Q1_destinationOffsetHigh_SHIFT 0
 176 #define OHCI1394_AT_DATA_Q1_rCode_MASK                  0x0000f000
 177 #define OHCI1394_AT_DATA_Q1_rCode_SHIFT                 12
 178
 179 static inline bool ohci1394_at_data_get_src_bus_id(const __le32 *data)
 180 {
 181         return !!((data[0] & OHCI1394_AT_DATA_Q0_srcBusID_MASK) >> OHCI1394_AT_DATA_Q0_srcBusID_SHIFT);
 182 }
 183
 184 static inline void ohci1394_at_data_set_src_bus_id(__le32 *data, bool src_bus_id)
 185 {
 186         data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_srcBusID_MASK);
 187         data[0] |= cpu_to_le32((src_bus_id << OHCI1394_AT_DATA_Q0_srcBusID_SHIFT) & OHCI1394_AT_DATA_Q0_srcBusID_MASK);
 188 }
 189
 190 static inline unsigned int ohci1394_at_data_get_speed(const __le32 *data)
 191 {
 192         return (le32_to_cpu(data[0]) & OHCI1394_AT_DATA_Q0_spd_MASK) >> OHCI1394_AT_DATA_Q0_spd_SHIFT;
 193 }
 194
 195 static inline void ohci1394_at_data_set_speed(__le32 *data, unsigned int scode)
 196 {
 197         data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_spd_MASK);
 198         data[0] |= cpu_to_le32((scode << OHCI1394_AT_DATA_Q0_spd_SHIFT) & OHCI1394_AT_DATA_Q0_spd_MASK);
 199 }
 200
 201 static inline unsigned int ohci1394_at_data_get_tlabel(const __le32 *data)
 202 {
 203         return (le32_to_cpu(data[0]) & OHCI1394_AT_DATA_Q0_tLabel_MASK) >> OHCI1394_AT_DATA_Q0_tLabel_SHIFT;
 204 }
 205
 206 static inline void ohci1394_at_data_set_tlabel(__le32 *data, unsigned int tlabel)
 207 {
 208         data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_tLabel_MASK);
 209         data[0] |= cpu_to_le32((tlabel << OHCI1394_AT_DATA_Q0_tLabel_SHIFT) & OHCI1394_AT_DATA_Q0_tLabel_MASK);
 210 }
 211
 212 static inline unsigned int ohci1394_at_data_get_retry(const __le32 *data)
 213 {
 214         return (le32_to_cpu(data[0]) & OHCI1394_AT_DATA_Q0_rt_MASK) >> OHCI1394_AT_DATA_Q0_rt_SHIFT;
 215 }
 216
 217 static inline void ohci1394_at_data_set_retry(__le32 *data, unsigned int retry)
 218 {
 219         data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_rt_MASK);
 220         data[0] |= cpu_to_le32((retry << OHCI1394_AT_DATA_Q0_rt_SHIFT) & OHCI1394_AT_DATA_Q0_rt_MASK);
 221 }
 222
 223 static inline unsigned int ohci1394_at_data_get_tcode(const __le32 *data)
 224 {
 225         return (le32_to_cpu(data[0]) & OHCI1394_AT_DATA_Q0_tCode_MASK) >> OHCI1394_AT_DATA_Q0_tCode_SHIFT;
 226 }
 227
 228 static inline void ohci1394_at_data_set_tcode(__le32 *data, unsigned int tcode)
 229 {
 230         data[0] &= cpu_to_le32(~OHCI1394_AT_DATA_Q0_tCode_MASK);
 231         data[0] |= cpu_to_le32((tcode << OHCI1394_AT_DATA_Q0_tCode_SHIFT) & OHCI1394_AT_DATA_Q0_tCode_MASK);
 232 }
 233
 234 static inline unsigned int ohci1394_at_data_get_destination_id(const __le32 *data)
 235 {
 236         return (le32_to_cpu(data[1]) & OHCI1394_AT_DATA_Q1_destinationId_MASK) >> OHCI1394_AT_DATA_Q1_destinationId_SHIFT;
 237 }
 238
 239 static inline void ohci1394_at_data_set_destination_id(__le32 *data, unsigned int destination_id)
 240 {
 241         data[1] &= cpu_to_le32(~OHCI1394_AT_DATA_Q1_destinationId_MASK);
 242         data[1] |= cpu_to_le32((destination_id << OHCI1394_AT_DATA_Q1_destinationId_SHIFT) & OHCI1394_AT_DATA_Q1_destinationId_MASK);
 243 }
 244
 245 static inline u64 ohci1394_at_data_get_destination_offset(const __le32 *data)
 246 {
 247         u64 hi = (u64)((le32_to_cpu(data[1]) & OHCI1394_AT_DATA_Q1_destinationOffsetHigh_MASK) >> OHCI1394_AT_DATA_Q1_destinationOffsetHigh_SHIFT);
 248         u64 lo = (u64)le32_to_cpu(data[2]);
 249         return (hi << 32) | lo;
 250 }
 251
 252 static inline void ohci1394_at_data_set_destination_offset(__le32 *data, u64 offset)
 253 {
 254         u32 hi = (u32)(offset >> 32);
 255         u32 lo = (u32)(offset & 0x00000000ffffffff);
 256         data[1] &= cpu_to_le32(~OHCI1394_AT_DATA_Q1_destinationOffsetHigh_MASK);
 257         data[1] |= cpu_to_le32((hi << OHCI1394_AT_DATA_Q1_destinationOffsetHigh_SHIFT) & OHCI1394_AT_DATA_Q1_destinationOffsetHigh_MASK);
 258         data[2] = cpu_to_le32(lo);
 259 }
 260
 261 static inline unsigned int ohci1394_at_data_get_rcode(const __le32 *data)
 262 {
 263         return (le32_to_cpu(data[1]) & OHCI1394_AT_DATA_Q1_rCode_MASK) >> OHCI1394_AT_DATA_Q1_rCode_SHIFT;
 264 }
 265
 266 static inline void ohci1394_at_data_set_rcode(__le32 *data, unsigned int rcode)
 267 {
 268         data[1] &= cpu_to_le32(~OHCI1394_AT_DATA_Q1_rCode_MASK);
 269         data[1] |= cpu_to_le32((rcode << OHCI1394_AT_DATA_Q1_rCode_SHIFT) & OHCI1394_AT_DATA_Q1_rCode_MASK);
 270 }
 271
 272 // Isochronous Transmit DMA.
 273 //
 274 // The content of first two quadlets of data for IT DMA is different from the header for IEEE 1394
 275 // isochronous packet.
 276
 277 #define OHCI1394_IT_DATA_Q0_spd_MASK            0x00070000
 278 #define OHCI1394_IT_DATA_Q0_spd_SHIFT           16
 279 #define OHCI1394_IT_DATA_Q0_tag_MASK            0x0000c000
 280 #define OHCI1394_IT_DATA_Q0_tag_SHIFT           14
 281 #define OHCI1394_IT_DATA_Q0_chanNum_MASK        0x00003f00
 282 #define OHCI1394_IT_DATA_Q0_chanNum_SHIFT       8
 283 #define OHCI1394_IT_DATA_Q0_tcode_MASK          0x000000f0
 284 #define OHCI1394_IT_DATA_Q0_tcode_SHIFT         4
 285 #define OHCI1394_IT_DATA_Q0_sy_MASK             0x0000000f
 286 #define OHCI1394_IT_DATA_Q0_sy_SHIFT            0
 287 #define OHCI1394_IT_DATA_Q1_dataLength_MASK     0xffff0000
 288 #define OHCI1394_IT_DATA_Q1_dataLength_SHIFT    16
 289
 290 static inline unsigned int ohci1394_it_data_get_speed(const __le32 *data)
 291 {
 292         return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_spd_MASK) >> OHCI1394_IT_DATA_Q0_spd_SHIFT;
 293 }
 294
 295 static inline void ohci1394_it_data_set_speed(__le32 *data, unsigned int scode)
 296 {
 297         data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_spd_MASK);
 298         data[0] |= cpu_to_le32((scode << OHCI1394_IT_DATA_Q0_spd_SHIFT) & OHCI1394_IT_DATA_Q0_spd_MASK);
 299 }
 300
 301 static inline unsigned int ohci1394_it_data_get_tag(const __le32 *data)
 302 {
 303         return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_tag_MASK) >> OHCI1394_IT_DATA_Q0_tag_SHIFT;
 304 }
 305
 306 static inline void ohci1394_it_data_set_tag(__le32 *data, unsigned int tag)
 307 {
 308         data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_tag_MASK);
 309         data[0] |= cpu_to_le32((tag << OHCI1394_IT_DATA_Q0_tag_SHIFT) & OHCI1394_IT_DATA_Q0_tag_MASK);
 310 }
 311
 312 static inline unsigned int ohci1394_it_data_get_channel(const __le32 *data)
 313 {
 314         return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_chanNum_MASK) >> OHCI1394_IT_DATA_Q0_chanNum_SHIFT;
 315 }
 316
 317 static inline void ohci1394_it_data_set_channel(__le32 *data, unsigned int channel)
 318 {
 319         data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_chanNum_MASK);
 320         data[0] |= cpu_to_le32((channel << OHCI1394_IT_DATA_Q0_chanNum_SHIFT) & OHCI1394_IT_DATA_Q0_chanNum_MASK);
 321 }
 322
 323 static inline unsigned int ohci1394_it_data_get_tcode(const __le32 *data)
 324 {
 325         return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_tcode_MASK) >> OHCI1394_IT_DATA_Q0_tcode_SHIFT;
 326 }
 327
 328 static inline void ohci1394_it_data_set_tcode(__le32 *data, unsigned int tcode)
 329 {
 330         data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_tcode_MASK);
 331         data[0] |= cpu_to_le32((tcode << OHCI1394_IT_DATA_Q0_tcode_SHIFT) & OHCI1394_IT_DATA_Q0_tcode_MASK);
 332 }
 333
 334 static inline unsigned int ohci1394_it_data_get_sync(const __le32 *data)
 335 {
 336         return (le32_to_cpu(data[0]) & OHCI1394_IT_DATA_Q0_sy_MASK) >> OHCI1394_IT_DATA_Q0_sy_SHIFT;
 337 }
 338
 339 static inline void ohci1394_it_data_set_sync(__le32 *data, unsigned int sync)
 340 {
 341         data[0] &= cpu_to_le32(~OHCI1394_IT_DATA_Q0_sy_MASK);
 342         data[0] |= cpu_to_le32((sync << OHCI1394_IT_DATA_Q0_sy_SHIFT) & OHCI1394_IT_DATA_Q0_sy_MASK);
 343 }
 344
 345 static inline unsigned int ohci1394_it_data_get_data_length(const __le32 *data)
 346 {
 347         return (le32_to_cpu(data[1]) & OHCI1394_IT_DATA_Q1_dataLength_MASK) >> OHCI1394_IT_DATA_Q1_dataLength_SHIFT;
 348 }
 349
 350 static inline void ohci1394_it_data_set_data_length(__le32 *data, unsigned int data_length)
 351 {
 352         data[1] &= cpu_to_le32(~OHCI1394_IT_DATA_Q1_dataLength_MASK);
 353         data[1] |= cpu_to_le32((data_length << OHCI1394_IT_DATA_Q1_dataLength_SHIFT) & OHCI1394_IT_DATA_Q1_dataLength_MASK);
 354 }
 355
 356 // Self-ID DMA.
 357
 358 #define OHCI1394_SelfIDCount_selfIDError_MASK           0x80000000
 359 #define OHCI1394_SelfIDCount_selfIDError_SHIFT          31
 360 #define OHCI1394_SelfIDCount_selfIDGeneration_MASK      0x00ff0000
 361 #define OHCI1394_SelfIDCount_selfIDGeneration_SHIFT     16
 362 #define OHCI1394_SelfIDCount_selfIDSize_MASK            0x000007fc
 363 #define OHCI1394_SelfIDCount_selfIDSize_SHIFT           2
 364
 365 static inline bool ohci1394_self_id_count_is_error(u32 value)
 366 {
 367         return !!((value & OHCI1394_SelfIDCount_selfIDError_MASK) >> OHCI1394_SelfIDCount_selfIDError_SHIFT);
 368 }
 369
 370 static inline u8 ohci1394_self_id_count_get_generation(u32 value)
 371 {
 372         return (value & OHCI1394_SelfIDCount_selfIDGeneration_MASK) >> OHCI1394_SelfIDCount_selfIDGeneration_SHIFT;
 373 }
 374
 375 // In 1394 OHCI specification, the maximum size of self ID stream is 504 quadlets
 376 // (= 63 devices * 4 self ID packets * 2 quadlets). The selfIDSize field accommodates it and its
 377 // additional first quadlet, since the field is 9 bits (0x1ff = 511).
 378 static inline u32 ohci1394_self_id_count_get_size(u32 value)
 379 {
 380         return (value & OHCI1394_SelfIDCount_selfIDSize_MASK) >> OHCI1394_SelfIDCount_selfIDSize_SHIFT;
 381 }
 382
 383 #define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_MASK     0x00ff0000
 384 #define OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_SHIFT    16
 385 #define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_MASK      0x0000ffff
 386 #define OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_SHIFT     0
 387
 388 static inline u8 ohci1394_self_id_receive_q0_get_generation(u32 quadlet0)
 389 {
 390         return (quadlet0 & OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_MASK) >> OHCI1394_SELF_ID_RECEIVE_Q0_GENERATION_SHIFT;
 391 }
 392
 393 static inline u16 ohci1394_self_id_receive_q0_get_timestamp(u32 quadlet0)
 394 {
 395         return (quadlet0 & OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_MASK) >> OHCI1394_SELF_ID_RECEIVE_Q0_TIMESTAMP_SHIFT;
 396 }
 397
 398 #endif /* _FIREWIRE_OHCI_H */