drivers/gpio/gpio-altera.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2013 Altera Corporation
   4  * Based on gpio-mpc8xxx.c
   5  */
   6
   7 #include <linux/bitops.h>
   8 #include <linux/device.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/irq.h>
  12 #include <linux/mod_devicetable.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/property.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/types.h>
  18
  19 #include <linux/gpio/driver.h>
  20
  21 #define ALTERA_GPIO_MAX_NGPIO           32
  22 #define ALTERA_GPIO_DATA                0x0
  23 #define ALTERA_GPIO_DIR                 0x4
  24 #define ALTERA_GPIO_IRQ_MASK            0x8
  25 #define ALTERA_GPIO_EDGE_CAP            0xc
  26
  27 /**
  28 * struct altera_gpio_chip
  29 * @gc                   : GPIO chip structure.
  30 * @regs                 : memory mapped IO address for the controller registers.
  31 * @gpio_lock            : synchronization lock so that new irq/set/get requests
  32 *                         will be blocked until the current one completes.
  33 * @interrupt_trigger    : specifies the hardware configured IRQ trigger type
  34 *                         (rising, falling, both, high)
  35 * @mapped_irq           : kernel mapped irq number.
  36 */
  37 struct altera_gpio_chip {
  38         struct gpio_chip gc;
  39         void __iomem *regs;
  40         raw_spinlock_t gpio_lock;
  41         int interrupt_trigger;
  42         int mapped_irq;
  43 };
  44
  45 static void altera_gpio_irq_unmask(struct irq_data *d)
  46 {
  47         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  48         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
  49         unsigned long flags;
  50         u32 intmask;
  51
  52         gpiochip_enable_irq(gc, irqd_to_hwirq(d));
  53
  54         raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
  55         intmask = readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
  56         /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
  57         intmask |= BIT(irqd_to_hwirq(d));
  58         writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
  59         raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
  60 }
  61
  62 static void altera_gpio_irq_mask(struct irq_data *d)
  63 {
  64         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  65         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
  66         unsigned long flags;
  67         u32 intmask;
  68
  69         raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
  70         intmask = readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
  71         /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
  72         intmask &= ~BIT(irqd_to_hwirq(d));
  73         writel(intmask, altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
  74         raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
  75
  76         gpiochip_disable_irq(gc, irqd_to_hwirq(d));
  77 }
  78
  79 /*
  80  * This controller's IRQ type is synthesized in hardware, so this function
  81  * just checks if the requested set_type matches the synthesized IRQ type
  82  */
  83 static int altera_gpio_irq_set_type(struct irq_data *d,
  84                                    unsigned int type)
  85 {
  86         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  87         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
  88
  89         if (type == IRQ_TYPE_NONE) {
  90                 irq_set_handler_locked(d, handle_bad_irq);
  91                 return 0;
  92         }
  93         if (type == altera_gc->interrupt_trigger) {
  94                 if (type == IRQ_TYPE_LEVEL_HIGH)
  95                         irq_set_handler_locked(d, handle_level_irq);
  96                 else
  97                         irq_set_handler_locked(d, handle_simple_irq);
  98                 return 0;
  99         }
 100         irq_set_handler_locked(d, handle_bad_irq);
 101         return -EINVAL;
 102 }
 103
 104 static unsigned int altera_gpio_irq_startup(struct irq_data *d)
 105 {
 106         altera_gpio_irq_unmask(d);
 107
 108         return 0;
 109 }
 110
 111 static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
 112 {
 113         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
 114
 115         return !!(readl(altera_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
 116 }
 117
 118 static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 119 {
 120         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
 121         unsigned long flags;
 122         unsigned int data_reg;
 123
 124         raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
 125         data_reg = readl(altera_gc->regs + ALTERA_GPIO_DATA);
 126         if (value)
 127                 data_reg |= BIT(offset);
 128         else
 129                 data_reg &= ~BIT(offset);
 130         writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
 131         raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
 132 }
 133
 134 static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
 135 {
 136         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
 137         unsigned long flags;
 138         unsigned int gpio_ddr;
 139
 140         raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
 141         /* Set pin as input, assumes software controlled IP */
 142         gpio_ddr = readl(altera_gc->regs + ALTERA_GPIO_DIR);
 143         gpio_ddr &= ~BIT(offset);
 144         writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
 145         raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
 146
 147         return 0;
 148 }
 149
 150 static int altera_gpio_direction_output(struct gpio_chip *gc,
 151                 unsigned offset, int value)
 152 {
 153         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
 154         unsigned long flags;
 155         unsigned int data_reg, gpio_ddr;
 156
 157         raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
 158         /* Sets the GPIO value */
 159         data_reg = readl(altera_gc->regs + ALTERA_GPIO_DATA);
 160         if (value)
 161                 data_reg |= BIT(offset);
 162         else
 163                 data_reg &= ~BIT(offset);
 164         writel(data_reg, altera_gc->regs + ALTERA_GPIO_DATA);
 165
 166         /* Set pin as output, assumes software controlled IP */
 167         gpio_ddr = readl(altera_gc->regs + ALTERA_GPIO_DIR);
 168         gpio_ddr |= BIT(offset);
 169         writel(gpio_ddr, altera_gc->regs + ALTERA_GPIO_DIR);
 170         raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
 171
 172         return 0;
 173 }
 174
 175 static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
 176 {
 177         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 178         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
 179         struct irq_domain *irqdomain = gc->irq.domain;
 180         struct irq_chip *chip;
 181         unsigned long status;
 182         int i;
 183
 184         chip = irq_desc_get_chip(desc);
 185
 186         chained_irq_enter(chip, desc);
 187
 188         while ((status =
 189                 (readl(altera_gc->regs + ALTERA_GPIO_EDGE_CAP) &
 190                  readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
 191                 writel(status, altera_gc->regs + ALTERA_GPIO_EDGE_CAP);
 192                 for_each_set_bit(i, &status, gc->ngpio)
 193                         generic_handle_domain_irq(irqdomain, i);
 194         }
 195
 196         chained_irq_exit(chip, desc);
 197 }
 198
 199 static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
 200 {
 201         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 202         struct altera_gpio_chip *altera_gc = gpiochip_get_data(gc);
 203         struct irq_domain *irqdomain = gc->irq.domain;
 204         struct irq_chip *chip;
 205         unsigned long status;
 206         int i;
 207
 208         chip = irq_desc_get_chip(desc);
 209
 210         chained_irq_enter(chip, desc);
 211
 212         status = readl(altera_gc->regs + ALTERA_GPIO_DATA);
 213         status &= readl(altera_gc->regs + ALTERA_GPIO_IRQ_MASK);
 214
 215         for_each_set_bit(i, &status, gc->ngpio)
 216                 generic_handle_domain_irq(irqdomain, i);
 217
 218         chained_irq_exit(chip, desc);
 219 }
 220
 221 static const struct irq_chip altera_gpio_irq_chip = {
 222         .name = "altera-gpio",
 223         .irq_mask = altera_gpio_irq_mask,
 224         .irq_unmask = altera_gpio_irq_unmask,
 225         .irq_set_type = altera_gpio_irq_set_type,
 226         .irq_startup  = altera_gpio_irq_startup,
 227         .irq_shutdown = altera_gpio_irq_mask,
 228         .flags = IRQCHIP_IMMUTABLE,
 229         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 230 };
 231
 232 static int altera_gpio_probe(struct platform_device *pdev)
 233 {
 234         struct device *dev = &pdev->dev;
 235         int reg, ret;
 236         struct altera_gpio_chip *altera_gc;
 237         struct gpio_irq_chip *girq;
 238
 239         altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
 240         if (!altera_gc)
 241                 return -ENOMEM;
 242
 243         raw_spin_lock_init(&altera_gc->gpio_lock);
 244
 245         if (device_property_read_u32(dev, "altr,ngpio", &reg))
 246                 /* By default assume maximum ngpio */
 247                 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
 248         else
 249                 altera_gc->gc.ngpio = reg;
 250
 251         if (altera_gc->gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
 252                 dev_warn(&pdev->dev,
 253                         "ngpio is greater than %d, defaulting to %d\n",
 254                         ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
 255                 altera_gc->gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
 256         }
 257
 258         altera_gc->gc.direction_input   = altera_gpio_direction_input;
 259         altera_gc->gc.direction_output  = altera_gpio_direction_output;
 260         altera_gc->gc.get               = altera_gpio_get;
 261         altera_gc->gc.set               = altera_gpio_set;
 262         altera_gc->gc.owner             = THIS_MODULE;
 263         altera_gc->gc.parent            = &pdev->dev;
 264         altera_gc->gc.base              = -1;
 265
 266         altera_gc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev));
 267         if (!altera_gc->gc.label)
 268                 return -ENOMEM;
 269
 270         altera_gc->regs = devm_platform_ioremap_resource(pdev, 0);
 271         if (IS_ERR(altera_gc->regs))
 272                 return dev_err_probe(dev, PTR_ERR(altera_gc->regs), "failed to ioremap memory resource\n");
 273
 274         altera_gc->mapped_irq = platform_get_irq_optional(pdev, 0);
 275         if (altera_gc->mapped_irq < 0)
 276                 goto skip_irq;
 277
 278         if (device_property_read_u32(dev, "altr,interrupt-type", &reg)) {
 279                 dev_err(&pdev->dev,
 280                         "altr,interrupt-type value not set in device tree\n");
 281                 return -EINVAL;
 282         }
 283         altera_gc->interrupt_trigger = reg;
 284
 285         girq = &altera_gc->gc.irq;
 286         gpio_irq_chip_set_chip(girq, &altera_gpio_irq_chip);
 287
 288         if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
 289                 girq->parent_handler = altera_gpio_irq_leveL_high_handler;
 290         else
 291                 girq->parent_handler = altera_gpio_irq_edge_handler;
 292         girq->num_parents = 1;
 293         girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
 294                                      GFP_KERNEL);
 295         if (!girq->parents)
 296                 return -ENOMEM;
 297         girq->default_type = IRQ_TYPE_NONE;
 298         girq->handler = handle_bad_irq;
 299         girq->parents[0] = altera_gc->mapped_irq;
 300
 301 skip_irq:
 302         ret = devm_gpiochip_add_data(dev, &altera_gc->gc, altera_gc);
 303         if (ret) {
 304                 dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
 305                 return ret;
 306         }
 307
 308         return 0;
 309 }
 310
 311 static const struct of_device_id altera_gpio_of_match[] = {
 312         { .compatible = "altr,pio-1.0", },
 313         {},
 314 };
 315 MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
 316
 317 static struct platform_driver altera_gpio_driver = {
 318         .driver = {
 319                 .name   = "altera_gpio",
 320                 .of_match_table = altera_gpio_of_match,
 321         },
 322         .probe          = altera_gpio_probe,
 323 };
 324
 325 static int __init altera_gpio_init(void)
 326 {
 327         return platform_driver_register(&altera_gpio_driver);
 328 }
 329 subsys_initcall(altera_gpio_init);
 330
 331 static void __exit altera_gpio_exit(void)
 332 {
 333         platform_driver_unregister(&altera_gpio_driver);
 334 }
 335 module_exit(altera_gpio_exit);
 336
 337 MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
 338 MODULE_DESCRIPTION("Altera GPIO driver");
 339 MODULE_LICENSE("GPL");