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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / gpio / gpio-brcmstb.c
blob491b529d25f8d35ec33f015f87586d784dcac7c6
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2015-2017 Broadcom
3
4 #include <linux/bitops.h>
5 #include <linux/gpio/driver.h>
6 #include <linux/of.h>
7 #include <linux/module.h>
8 #include <linux/irqdomain.h>
9 #include <linux/irqchip/chained_irq.h>
10 #include <linux/interrupt.h>
11 #include <linux/platform_device.h>
12
13 enum gio_reg_index {
14 GIO_REG_ODEN = 0,
15 GIO_REG_DATA,
16 GIO_REG_IODIR,
17 GIO_REG_EC,
18 GIO_REG_EI,
19 GIO_REG_MASK,
20 GIO_REG_LEVEL,
21 GIO_REG_STAT,
22 NUMBER_OF_GIO_REGISTERS
23 };
24
25 #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
35
36 struct brcmstb_gpio_bank {
37 struct list_head node;
38 int id;
39 struct gpio_chip gc;
40 struct brcmstb_gpio_priv *parent_priv;
41 u32 width;
42 u32 wake_active;
43 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
44 };
45
46 struct brcmstb_gpio_priv {
47 struct list_head bank_list;
48 void __iomem *reg_base;
49 struct platform_device *pdev;
50 struct irq_domain *irq_domain;
51 struct irq_chip irq_chip;
52 int parent_irq;
53 int num_gpios;
54 int parent_wake_irq;
55 };
56
57 #define MAX_GPIO_PER_BANK 32
58 #define GPIO_BANK(gpio) ((gpio) >> 5)
59 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
60 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
61
62 static inline struct brcmstb_gpio_priv *
63 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
64 {
65 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
66 return bank->parent_priv;
67 }
68
69 static unsigned long
70 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
71 {
72 void __iomem *reg_base = bank->parent_priv->reg_base;
73
74 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
75 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
76 }
77
78 static unsigned long
79 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
80 {
81 unsigned long status;
82 unsigned long flags;
83
84 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
85 status = __brcmstb_gpio_get_active_irqs(bank);
86 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
87
88 return status;
89 }
90
91 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
92 struct brcmstb_gpio_bank *bank)
93 {
94 return hwirq - bank->gc.offset;
95 }
96
97 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
98 unsigned int hwirq, bool enable)
99 {
100 struct gpio_chip *gc = &bank->gc;
101 struct brcmstb_gpio_priv *priv = bank->parent_priv;
102 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
103 u32 imask;
104 unsigned long flags;
105
106 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
107 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
108 if (enable)
109 imask |= mask;
110 else
111 imask &= ~mask;
112 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
113 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
114 }
115
116 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
117 {
118 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
119 /* gc_offset is relative to this gpio_chip; want real offset */
120 int hwirq = offset + gc->offset;
121
122 if (hwirq >= priv->num_gpios)
123 return -ENXIO;
124 return irq_create_mapping(priv->irq_domain, hwirq);
125 }
126
127 /* -------------------- IRQ chip functions -------------------- */
128
129 static void brcmstb_gpio_irq_mask(struct irq_data *d)
130 {
131 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
132 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
133
134 brcmstb_gpio_set_imask(bank, d->hwirq, false);
135 }
136
137 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
138 {
139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
141
142 brcmstb_gpio_set_imask(bank, d->hwirq, true);
143 }
144
145 static void brcmstb_gpio_irq_ack(struct irq_data *d)
146 {
147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
148 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
149 struct brcmstb_gpio_priv *priv = bank->parent_priv;
150 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
151
152 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
153 }
154
155 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
156 {
157 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
158 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
159 struct brcmstb_gpio_priv *priv = bank->parent_priv;
160 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
161 u32 edge_insensitive, iedge_insensitive;
162 u32 edge_config, iedge_config;
163 u32 level, ilevel;
164 unsigned long flags;
165
166 switch (type) {
167 case IRQ_TYPE_LEVEL_LOW:
168 level = mask;
169 edge_config = 0;
170 edge_insensitive = 0;
171 break;
172 case IRQ_TYPE_LEVEL_HIGH:
173 level = mask;
174 edge_config = mask;
175 edge_insensitive = 0;
176 break;
177 case IRQ_TYPE_EDGE_FALLING:
178 level = 0;
179 edge_config = 0;
180 edge_insensitive = 0;
181 break;
182 case IRQ_TYPE_EDGE_RISING:
183 level = 0;
184 edge_config = mask;
185 edge_insensitive = 0;
186 break;
187 case IRQ_TYPE_EDGE_BOTH:
188 level = 0;
189 edge_config = 0; /* don't care, but want known value */
190 edge_insensitive = mask;
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
197
198 iedge_config = bank->gc.read_reg(priv->reg_base +
199 GIO_EC(bank->id)) & ~mask;
200 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
201 GIO_EI(bank->id)) & ~mask;
202 ilevel = bank->gc.read_reg(priv->reg_base +
203 GIO_LEVEL(bank->id)) & ~mask;
204
205 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
206 iedge_config | edge_config);
207 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
208 iedge_insensitive | edge_insensitive);
209 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
210 ilevel | level);
211
212 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
213 return 0;
214 }
215
216 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
217 unsigned int enable)
218 {
219 int ret = 0;
220
221 if (enable)
222 ret = enable_irq_wake(priv->parent_wake_irq);
223 else
224 ret = disable_irq_wake(priv->parent_wake_irq);
225 if (ret)
226 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
227 enable ? "enable" : "disable");
228 return ret;
229 }
230
231 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
232 {
233 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
234 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
235 struct brcmstb_gpio_priv *priv = bank->parent_priv;
236 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
237
238 /*
239 * Do not do anything specific for now, suspend/resume callbacks will
240 * configure the interrupt mask appropriately
241 */
242 if (enable)
243 bank->wake_active |= mask;
244 else
245 bank->wake_active &= ~mask;
246
247 return brcmstb_gpio_priv_set_wake(priv, enable);
248 }
249
250 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
251 {
252 struct brcmstb_gpio_priv *priv = data;
253
254 if (!priv || irq != priv->parent_wake_irq)
255 return IRQ_NONE;
256
257 /* Nothing to do */
258 return IRQ_HANDLED;
259 }
260
261 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
262 {
263 struct brcmstb_gpio_priv *priv = bank->parent_priv;
264 struct irq_domain *domain = priv->irq_domain;
265 int hwbase = bank->gc.offset;
266 unsigned long status;
267
268 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
269 unsigned int offset;
270
271 for_each_set_bit(offset, &status, 32) {
272 if (offset >= bank->width)
273 dev_warn(&priv->pdev->dev,
274 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
275 bank->id, offset);
276 generic_handle_domain_irq(domain, hwbase + offset);
277 }
278 }
279 }
280
281 /* Each UPG GIO block has one IRQ for all banks */
282 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
283 {
284 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
285 struct irq_chip *chip = irq_desc_get_chip(desc);
286 struct brcmstb_gpio_bank *bank;
287
288 /* Interrupts weren't properly cleared during probe */
289 BUG_ON(!priv || !chip);
290
291 chained_irq_enter(chip, desc);
292 list_for_each_entry(bank, &priv->bank_list, node)
293 brcmstb_gpio_irq_bank_handler(bank);
294 chained_irq_exit(chip, desc);
295 }
296
297 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
298 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
299 {
300 struct brcmstb_gpio_bank *bank;
301 int i = 0;
302
303 /* banks are in descending order */
304 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
305 i += bank->gc.ngpio;
306 if (hwirq < i)
307 return bank;
308 }
309 return NULL;
310 }
311
312 /*
313 * This lock class tells lockdep that GPIO irqs are in a different
314 * category than their parents, so it won't report false recursion.
315 */
316 static struct lock_class_key brcmstb_gpio_irq_lock_class;
317 static struct lock_class_key brcmstb_gpio_irq_request_class;
318
319
320 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
321 irq_hw_number_t hwirq)
322 {
323 struct brcmstb_gpio_priv *priv = d->host_data;
324 struct brcmstb_gpio_bank *bank =
325 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
326 struct platform_device *pdev = priv->pdev;
327 int ret;
328
329 if (!bank)
330 return -EINVAL;
331
332 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
333 irq, (int)hwirq, bank->id);
334 ret = irq_set_chip_data(irq, &bank->gc);
335 if (ret < 0)
336 return ret;
337 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
338 &brcmstb_gpio_irq_request_class);
339 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
340 irq_set_noprobe(irq);
341 return 0;
342 }
343
344 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
345 {
346 irq_set_chip_and_handler(irq, NULL, NULL);
347 irq_set_chip_data(irq, NULL);
348 }
349
350 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
351 .map = brcmstb_gpio_irq_map,
352 .unmap = brcmstb_gpio_irq_unmap,
353 .xlate = irq_domain_xlate_twocell,
354 };
355
356 /* Make sure that the number of banks matches up between properties */
357 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
358 struct device_node *np, struct resource *res)
359 {
360 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
361 int num_banks =
362 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
363
364 if (res_num_banks != num_banks) {
365 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
366 res_num_banks, num_banks);
367 return -EINVAL;
368 } else {
369 return 0;
370 }
371 }
372
373 static void brcmstb_gpio_remove(struct platform_device *pdev)
374 {
375 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
376 struct brcmstb_gpio_bank *bank;
377 int offset, virq;
378
379 if (priv->parent_irq > 0)
380 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
381
382 /* Remove all IRQ mappings and delete the domain */
383 if (priv->irq_domain) {
384 for (offset = 0; offset < priv->num_gpios; offset++) {
385 virq = irq_find_mapping(priv->irq_domain, offset);
386 irq_dispose_mapping(virq);
387 }
388 irq_domain_remove(priv->irq_domain);
389 }
390
391 /*
392 * You can lose return values below, but we report all errors, and it's
393 * more important to actually perform all of the steps.
394 */
395 list_for_each_entry(bank, &priv->bank_list, node)
396 gpiochip_remove(&bank->gc);
397 }
398
399 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
400 const struct of_phandle_args *gpiospec, u32 *flags)
401 {
402 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
403 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
404 int offset;
405
406 if (gc->of_gpio_n_cells != 2) {
407 WARN_ON(1);
408 return -EINVAL;
409 }
410
411 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
412 return -EINVAL;
413
414 offset = gpiospec->args[0] - bank->gc.offset;
415 if (offset >= gc->ngpio || offset < 0)
416 return -EINVAL;
417
418 if (unlikely(offset >= bank->width)) {
419 dev_warn_ratelimited(&priv->pdev->dev,
420 "Received request for invalid GPIO offset %d\n",
421 gpiospec->args[0]);
422 }
423
424 if (flags)
425 *flags = gpiospec->args[1];
426
427 return offset;
428 }
429
430 /* priv->parent_irq and priv->num_gpios must be set before calling */
431 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
432 struct brcmstb_gpio_priv *priv)
433 {
434 struct device *dev = &pdev->dev;
435 struct device_node *np = dev->of_node;
436 int err;
437
438 priv->irq_domain =
439 irq_domain_add_linear(np, priv->num_gpios,
440 &brcmstb_gpio_irq_domain_ops,
441 priv);
442 if (!priv->irq_domain) {
443 dev_err(dev, "Couldn't allocate IRQ domain\n");
444 return -ENXIO;
445 }
446
447 if (of_property_read_bool(np, "wakeup-source")) {
448 priv->parent_wake_irq = platform_get_irq(pdev, 1);
449 if (priv->parent_wake_irq < 0) {
450 priv->parent_wake_irq = 0;
451 dev_warn(dev,
452 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
453 } else {
454 /*
455 * Set wakeup capability so we can process boot-time
456 * "wakeups" (e.g., from S5 cold boot)
457 */
458 device_set_wakeup_capable(dev, true);
459 device_wakeup_enable(dev);
460 err = devm_request_irq(dev, priv->parent_wake_irq,
461 brcmstb_gpio_wake_irq_handler,
462 IRQF_SHARED,
463 "brcmstb-gpio-wake", priv);
464
465 if (err < 0) {
466 dev_err(dev, "Couldn't request wake IRQ");
467 goto out_free_domain;
468 }
469 }
470 }
471
472 priv->irq_chip.name = dev_name(dev);
473 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
474 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
475 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
476 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
477 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
478
479 if (priv->parent_wake_irq)
480 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
481
482 irq_set_chained_handler_and_data(priv->parent_irq,
483 brcmstb_gpio_irq_handler, priv);
484 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
485
486 return 0;
487
488 out_free_domain:
489 irq_domain_remove(priv->irq_domain);
490
491 return err;
492 }
493
494 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
495 struct brcmstb_gpio_bank *bank)
496 {
497 struct gpio_chip *gc = &bank->gc;
498 unsigned int i;
499
500 for (i = 0; i < GIO_REG_STAT; i++)
501 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
502 GIO_BANK_OFF(bank->id, i));
503 }
504
505 static void brcmstb_gpio_quiesce(struct device *dev, bool save)
506 {
507 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
508 struct brcmstb_gpio_bank *bank;
509 struct gpio_chip *gc;
510 u32 imask;
511
512 /* disable non-wake interrupt */
513 if (priv->parent_irq >= 0)
514 disable_irq(priv->parent_irq);
515
516 list_for_each_entry(bank, &priv->bank_list, node) {
517 gc = &bank->gc;
518
519 if (save)
520 brcmstb_gpio_bank_save(priv, bank);
521
522 /* Unmask GPIOs which have been flagged as wake-up sources */
523 if (priv->parent_wake_irq)
524 imask = bank->wake_active;
525 else
526 imask = 0;
527 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
528 imask);
529 }
530 }
531
532 static void brcmstb_gpio_shutdown(struct platform_device *pdev)
533 {
534 /* Enable GPIO for S5 cold boot */
535 brcmstb_gpio_quiesce(&pdev->dev, false);
536 }
537
538 #ifdef CONFIG_PM_SLEEP
539 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
540 struct brcmstb_gpio_bank *bank)
541 {
542 struct gpio_chip *gc = &bank->gc;
543 unsigned int i;
544
545 for (i = 0; i < GIO_REG_STAT; i++)
546 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
547 bank->saved_regs[i]);
548 }
549
550 static int brcmstb_gpio_suspend(struct device *dev)
551 {
552 brcmstb_gpio_quiesce(dev, true);
553 return 0;
554 }
555
556 static int brcmstb_gpio_resume(struct device *dev)
557 {
558 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
559 struct brcmstb_gpio_bank *bank;
560 bool need_wakeup_event = false;
561
562 list_for_each_entry(bank, &priv->bank_list, node) {
563 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
564 brcmstb_gpio_bank_restore(priv, bank);
565 }
566
567 if (priv->parent_wake_irq && need_wakeup_event)
568 pm_wakeup_event(dev, 0);
569
570 /* enable non-wake interrupt */
571 if (priv->parent_irq >= 0)
572 enable_irq(priv->parent_irq);
573
574 return 0;
575 }
576
577 #else
578 #define brcmstb_gpio_suspend NULL
579 #define brcmstb_gpio_resume NULL
580 #endif /* CONFIG_PM_SLEEP */
581
582 static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
583 .suspend_noirq = brcmstb_gpio_suspend,
584 .resume_noirq = brcmstb_gpio_resume,
585 };
586
587 static int brcmstb_gpio_probe(struct platform_device *pdev)
588 {
589 struct device *dev = &pdev->dev;
590 struct device_node *np = dev->of_node;
591 void __iomem *reg_base;
592 struct brcmstb_gpio_priv *priv;
593 struct resource *res;
594 u32 bank_width;
595 int num_banks = 0;
596 int num_gpios = 0;
597 int err;
598 unsigned long flags = 0;
599 bool need_wakeup_event = false;
600
601 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
602 if (!priv)
603 return -ENOMEM;
604 platform_set_drvdata(pdev, priv);
605 INIT_LIST_HEAD(&priv->bank_list);
606
607 reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
608 if (IS_ERR(reg_base))
609 return PTR_ERR(reg_base);
610
611 priv->reg_base = reg_base;
612 priv->pdev = pdev;
613
614 if (of_property_read_bool(np, "interrupt-controller")) {
615 priv->parent_irq = platform_get_irq(pdev, 0);
616 if (priv->parent_irq <= 0)
617 return -ENOENT;
618 } else {
619 priv->parent_irq = -ENOENT;
620 }
621
622 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
623 return -EINVAL;
624
625 /*
626 * MIPS endianness is configured by boot strap, which also reverses all
627 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
628 * endian I/O).
629 *
630 * Other architectures (e.g., ARM) either do not support big endian, or
631 * else leave I/O in little endian mode.
632 */
633 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
634 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
635 #endif
636
637 of_property_for_each_u32(np, "brcm,gpio-bank-widths", bank_width) {
638 struct brcmstb_gpio_bank *bank;
639 struct gpio_chip *gc;
640
641 /*
642 * If bank_width is 0, then there is an empty bank in the
643 * register block. Special handling for this case.
644 */
645 if (bank_width == 0) {
646 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
647 num_banks);
648 num_banks++;
649 num_gpios += MAX_GPIO_PER_BANK;
650 continue;
651 }
652
653 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
654 if (!bank) {
655 err = -ENOMEM;
656 goto fail;
657 }
658
659 bank->parent_priv = priv;
660 bank->id = num_banks;
661 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
662 dev_err(dev, "Invalid bank width %d\n", bank_width);
663 err = -EINVAL;
664 goto fail;
665 } else {
666 bank->width = bank_width;
667 }
668
669 /*
670 * Regs are 4 bytes wide, have data reg, no set/clear regs,
671 * and direction bits have 0 = output and 1 = input
672 */
673 gc = &bank->gc;
674 err = bgpio_init(gc, dev, 4,
675 reg_base + GIO_DATA(bank->id),
676 NULL, NULL, NULL,
677 reg_base + GIO_IODIR(bank->id), flags);
678 if (err) {
679 dev_err(dev, "bgpio_init() failed\n");
680 goto fail;
681 }
682
683 gc->owner = THIS_MODULE;
684 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
685 if (!gc->label) {
686 err = -ENOMEM;
687 goto fail;
688 }
689 gc->of_gpio_n_cells = 2;
690 gc->of_xlate = brcmstb_gpio_of_xlate;
691 /* not all ngpio lines are valid, will use bank width later */
692 gc->ngpio = MAX_GPIO_PER_BANK;
693 gc->offset = bank->id * MAX_GPIO_PER_BANK;
694 gc->request = gpiochip_generic_request;
695 gc->free = gpiochip_generic_free;
696 if (priv->parent_irq > 0)
697 gc->to_irq = brcmstb_gpio_to_irq;
698
699 /*
700 * Mask all interrupts by default, since wakeup interrupts may
701 * be retained from S5 cold boot
702 */
703 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
704 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
705
706 err = gpiochip_add_data(gc, bank);
707 if (err) {
708 dev_err(dev, "Could not add gpiochip for bank %d\n",
709 bank->id);
710 goto fail;
711 }
712 num_gpios += gc->ngpio;
713
714 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
715 gc->base, gc->ngpio, bank->width);
716
717 /* Everything looks good, so add bank to list */
718 list_add(&bank->node, &priv->bank_list);
719
720 num_banks++;
721 }
722
723 priv->num_gpios = num_gpios;
724 if (priv->parent_irq > 0) {
725 err = brcmstb_gpio_irq_setup(pdev, priv);
726 if (err)
727 goto fail;
728 }
729
730 if (priv->parent_wake_irq && need_wakeup_event)
731 pm_wakeup_event(dev, 0);
732
733 return 0;
734
735 fail:
736 (void) brcmstb_gpio_remove(pdev);
737 return err;
738 }
739
740 static const struct of_device_id brcmstb_gpio_of_match[] = {
741 { .compatible = "brcm,brcmstb-gpio" },
742 {},
743 };
744
745 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
746
747 static struct platform_driver brcmstb_gpio_driver = {
748 .driver = {
749 .name = "brcmstb-gpio",
750 .of_match_table = brcmstb_gpio_of_match,
751 .pm = &brcmstb_gpio_pm_ops,
752 },
753 .probe = brcmstb_gpio_probe,
754 .remove = brcmstb_gpio_remove,
755 .shutdown = brcmstb_gpio_shutdown,
756 };
757 module_platform_driver(brcmstb_gpio_driver);
758
759 MODULE_AUTHOR("Gregory Fong");
760 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
761 MODULE_LICENSE("GPL v2");
Kernel DRM miscellaneous fixes and cross-tree changes