drivers/gpio/gpio-crystalcove.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Crystal Cove GPIO Driver
   4  *
   5  * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
   6  *
   7  * Author: Yang, Bin <bin.yang@intel.com>
   8  */
   9
  10 #include <linux/bitops.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/mfd/intel_soc_pmic.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/regmap.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/types.h>
  19
  20 #define CRYSTALCOVE_GPIO_NUM    16
  21 #define CRYSTALCOVE_VGPIO_NUM   95
  22
  23 #define UPDATE_IRQ_TYPE         BIT(0)
  24 #define UPDATE_IRQ_MASK         BIT(1)
  25
  26 #define GPIO0IRQ                0x0b
  27 #define GPIO1IRQ                0x0c
  28 #define MGPIO0IRQS0             0x19
  29 #define MGPIO1IRQS0             0x1a
  30 #define MGPIO0IRQSX             0x1b
  31 #define MGPIO1IRQSX             0x1c
  32 #define GPIO0P0CTLO             0x2b
  33 #define GPIO0P0CTLI             0x33
  34 #define GPIO1P0CTLO             0x3b
  35 #define GPIO1P0CTLI             0x43
  36 #define GPIOPANELCTL            0x52
  37
  38 #define CTLI_INTCNT_DIS         (0)
  39 #define CTLI_INTCNT_NE          (1 << 1)
  40 #define CTLI_INTCNT_PE          (2 << 1)
  41 #define CTLI_INTCNT_BE          (3 << 1)
  42
  43 #define CTLO_DIR_IN             (0)
  44 #define CTLO_DIR_OUT            (1 << 5)
  45
  46 #define CTLO_DRV_CMOS           (0)
  47 #define CTLO_DRV_OD             (1 << 4)
  48
  49 #define CTLO_DRV_REN            (1 << 3)
  50
  51 #define CTLO_RVAL_2KDW          (0)
  52 #define CTLO_RVAL_2KUP          (1 << 1)
  53 #define CTLO_RVAL_50KDW         (2 << 1)
  54 #define CTLO_RVAL_50KUP         (3 << 1)
  55
  56 #define CTLO_INPUT_SET  (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
  57 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
  58
  59 enum ctrl_register {
  60         CTRL_IN,
  61         CTRL_OUT,
  62 };
  63
  64 /**
  65  * struct crystalcove_gpio - Crystal Cove GPIO controller
  66  * @buslock: for bus lock/sync and unlock.
  67  * @chip: the abstract gpio_chip structure.
  68  * @regmap: the regmap from the parent device.
  69  * @update: pending IRQ setting update, to be written to the chip upon unlock.
  70  * @intcnt_value: the Interrupt Detect value to be written.
  71  * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
  72  */
  73 struct crystalcove_gpio {
  74         struct mutex buslock; /* irq_bus_lock */
  75         struct gpio_chip chip;
  76         struct regmap *regmap;
  77         int update;
  78         int intcnt_value;
  79         bool set_irq_mask;
  80 };
  81
  82 static inline int to_reg(int gpio, enum ctrl_register reg_type)
  83 {
  84         int reg;
  85
  86         if (gpio >= CRYSTALCOVE_GPIO_NUM) {
  87                 /*
  88                  * Virtual GPIO called from ACPI, for now we only support
  89                  * the panel ctl.
  90                  */
  91                 switch (gpio) {
  92                 case 0x5e:
  93                         return GPIOPANELCTL;
  94                 default:
  95                         return -ENOTSUPP;
  96                 }
  97         }
  98
  99         if (reg_type == CTRL_IN) {
 100                 if (gpio < 8)
 101                         reg = GPIO0P0CTLI;
 102                 else
 103                         reg = GPIO1P0CTLI;
 104         } else {
 105                 if (gpio < 8)
 106                         reg = GPIO0P0CTLO;
 107                 else
 108                         reg = GPIO1P0CTLO;
 109         }
 110
 111         return reg + gpio % 8;
 112 }
 113
 114 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
 115 {
 116         u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
 117         int mask = BIT(gpio % 8);
 118
 119         if (cg->set_irq_mask)
 120                 regmap_update_bits(cg->regmap, mirqs0, mask, mask);
 121         else
 122                 regmap_update_bits(cg->regmap, mirqs0, mask, 0);
 123 }
 124
 125 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
 126 {
 127         int reg = to_reg(gpio, CTRL_IN);
 128
 129         regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
 130 }
 131
 132 static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
 133 {
 134         struct crystalcove_gpio *cg = gpiochip_get_data(chip);
 135         int reg = to_reg(gpio, CTRL_OUT);
 136
 137         if (reg < 0)
 138                 return 0;
 139
 140         return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
 141 }
 142
 143 static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
 144 {
 145         struct crystalcove_gpio *cg = gpiochip_get_data(chip);
 146         int reg = to_reg(gpio, CTRL_OUT);
 147
 148         if (reg < 0)
 149                 return 0;
 150
 151         return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
 152 }
 153
 154 static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 155 {
 156         struct crystalcove_gpio *cg = gpiochip_get_data(chip);
 157         unsigned int val;
 158         int ret, reg = to_reg(gpio, CTRL_IN);
 159
 160         if (reg < 0)
 161                 return 0;
 162
 163         ret = regmap_read(cg->regmap, reg, &val);
 164         if (ret)
 165                 return ret;
 166
 167         return val & 0x1;
 168 }
 169
 170 static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
 171 {
 172         struct crystalcove_gpio *cg = gpiochip_get_data(chip);
 173         int reg = to_reg(gpio, CTRL_OUT);
 174
 175         if (reg < 0)
 176                 return;
 177
 178         if (value)
 179                 regmap_update_bits(cg->regmap, reg, 1, 1);
 180         else
 181                 regmap_update_bits(cg->regmap, reg, 1, 0);
 182 }
 183
 184 static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
 185 {
 186         struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
 187         irq_hw_number_t hwirq = irqd_to_hwirq(data);
 188
 189         if (hwirq >= CRYSTALCOVE_GPIO_NUM)
 190                 return 0;
 191
 192         switch (type) {
 193         case IRQ_TYPE_NONE:
 194                 cg->intcnt_value = CTLI_INTCNT_DIS;
 195                 break;
 196         case IRQ_TYPE_EDGE_BOTH:
 197                 cg->intcnt_value = CTLI_INTCNT_BE;
 198                 break;
 199         case IRQ_TYPE_EDGE_RISING:
 200                 cg->intcnt_value = CTLI_INTCNT_PE;
 201                 break;
 202         case IRQ_TYPE_EDGE_FALLING:
 203                 cg->intcnt_value = CTLI_INTCNT_NE;
 204                 break;
 205         default:
 206                 return -EINVAL;
 207         }
 208
 209         cg->update |= UPDATE_IRQ_TYPE;
 210
 211         return 0;
 212 }
 213
 214 static void crystalcove_bus_lock(struct irq_data *data)
 215 {
 216         struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
 217
 218         mutex_lock(&cg->buslock);
 219 }
 220
 221 static void crystalcove_bus_sync_unlock(struct irq_data *data)
 222 {
 223         struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
 224         irq_hw_number_t hwirq = irqd_to_hwirq(data);
 225
 226         if (cg->update & UPDATE_IRQ_TYPE)
 227                 crystalcove_update_irq_ctrl(cg, hwirq);
 228         if (cg->update & UPDATE_IRQ_MASK)
 229                 crystalcove_update_irq_mask(cg, hwirq);
 230         cg->update = 0;
 231
 232         mutex_unlock(&cg->buslock);
 233 }
 234
 235 static void crystalcove_irq_unmask(struct irq_data *data)
 236 {
 237         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 238         struct crystalcove_gpio *cg = gpiochip_get_data(gc);
 239         irq_hw_number_t hwirq = irqd_to_hwirq(data);
 240
 241         if (hwirq >= CRYSTALCOVE_GPIO_NUM)
 242                 return;
 243
 244         gpiochip_enable_irq(gc, hwirq);
 245
 246         cg->set_irq_mask = false;
 247         cg->update |= UPDATE_IRQ_MASK;
 248 }
 249
 250 static void crystalcove_irq_mask(struct irq_data *data)
 251 {
 252         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 253         struct crystalcove_gpio *cg = gpiochip_get_data(gc);
 254         irq_hw_number_t hwirq = irqd_to_hwirq(data);
 255
 256         if (hwirq >= CRYSTALCOVE_GPIO_NUM)
 257                 return;
 258
 259         cg->set_irq_mask = true;
 260         cg->update |= UPDATE_IRQ_MASK;
 261
 262         gpiochip_disable_irq(gc, hwirq);
 263 }
 264
 265 static const struct irq_chip crystalcove_irqchip = {
 266         .name                   = "Crystal Cove",
 267         .irq_mask               = crystalcove_irq_mask,
 268         .irq_unmask             = crystalcove_irq_unmask,
 269         .irq_set_type           = crystalcove_irq_type,
 270         .irq_bus_lock           = crystalcove_bus_lock,
 271         .irq_bus_sync_unlock    = crystalcove_bus_sync_unlock,
 272         .flags                  = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
 273         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 274 };
 275
 276 static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
 277 {
 278         struct crystalcove_gpio *cg = data;
 279         unsigned long pending;
 280         unsigned int p0, p1;
 281         int gpio;
 282         unsigned int virq;
 283
 284         if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
 285             regmap_read(cg->regmap, GPIO1IRQ, &p1))
 286                 return IRQ_NONE;
 287
 288         regmap_write(cg->regmap, GPIO0IRQ, p0);
 289         regmap_write(cg->regmap, GPIO1IRQ, p1);
 290
 291         pending = p0 | p1 << 8;
 292
 293         for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
 294                 virq = irq_find_mapping(cg->chip.irq.domain, gpio);
 295                 handle_nested_irq(virq);
 296         }
 297
 298         return IRQ_HANDLED;
 299 }
 300
 301 static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 302 {
 303         struct crystalcove_gpio *cg = gpiochip_get_data(chip);
 304         int gpio, offset;
 305         unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
 306
 307         for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
 308                 regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
 309                 regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
 310                 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
 311                             &mirqs0);
 312                 regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
 313                             &mirqsx);
 314                 regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
 315                             &irq);
 316
 317                 offset = gpio % 8;
 318                 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
 319                            gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
 320                            ctli & 0x1 ? "hi" : "lo",
 321                            ctli & CTLI_INTCNT_NE ? "fall" : "    ",
 322                            ctli & CTLI_INTCNT_PE ? "rise" : "    ",
 323                            ctlo,
 324                            mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
 325                            mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
 326                            irq & BIT(offset) ? "pending" : "       ");
 327         }
 328 }
 329
 330 static int crystalcove_gpio_probe(struct platform_device *pdev)
 331 {
 332         int irq = platform_get_irq(pdev, 0);
 333         struct crystalcove_gpio *cg;
 334         int retval;
 335         struct device *dev = pdev->dev.parent;
 336         struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
 337         struct gpio_irq_chip *girq;
 338
 339         if (irq < 0)
 340                 return irq;
 341
 342         cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
 343         if (!cg)
 344                 return -ENOMEM;
 345
 346         mutex_init(&cg->buslock);
 347         cg->chip.label = KBUILD_MODNAME;
 348         cg->chip.direction_input = crystalcove_gpio_dir_in;
 349         cg->chip.direction_output = crystalcove_gpio_dir_out;
 350         cg->chip.get = crystalcove_gpio_get;
 351         cg->chip.set = crystalcove_gpio_set;
 352         cg->chip.base = -1;
 353         cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
 354         cg->chip.can_sleep = true;
 355         cg->chip.parent = dev;
 356         cg->chip.dbg_show = crystalcove_gpio_dbg_show;
 357         cg->regmap = pmic->regmap;
 358
 359         girq = &cg->chip.irq;
 360         gpio_irq_chip_set_chip(girq, &crystalcove_irqchip);
 361         /* This will let us handle the parent IRQ in the driver */
 362         girq->parent_handler = NULL;
 363         girq->num_parents = 0;
 364         girq->parents = NULL;
 365         girq->default_type = IRQ_TYPE_NONE;
 366         girq->handler = handle_simple_irq;
 367         girq->threaded = true;
 368
 369         retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 370                                            crystalcove_gpio_irq_handler,
 371                                            IRQF_ONESHOT, KBUILD_MODNAME, cg);
 372         if (retval) {
 373                 dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
 374                 return retval;
 375         }
 376
 377         retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
 378         if (retval)
 379                 return retval;
 380
 381         /* Distuingish IRQ domain from others sharing (MFD) the same fwnode */
 382         irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED);
 383
 384         return 0;
 385 }
 386
 387 static struct platform_driver crystalcove_gpio_driver = {
 388         .probe = crystalcove_gpio_probe,
 389         .driver = {
 390                 .name = "crystal_cove_gpio",
 391         },
 392 };
 393 module_platform_driver(crystalcove_gpio_driver);
 394
 395 MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
 396 MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
 397 MODULE_LICENSE("GPL v2");