drivers/gpio/gpio-ep93xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Generic EP93xx GPIO handling
   4  *
   5  * Copyright (c) 2008 Ryan Mallon
   6  * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
   7  *
   8  * Based on code originally from:
   9  *  linux/arch/arm/mach-ep93xx/core.c
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/slab.h>
  19 #include <linux/gpio/driver.h>
  20 #include <linux/bitops.h>
  21 #include <linux/seq_file.h>
  22
  23 struct ep93xx_gpio_irq_chip {
  24         void __iomem *base;
  25         u8 int_unmasked;
  26         u8 int_enabled;
  27         u8 int_type1;
  28         u8 int_type2;
  29         u8 int_debounce;
  30 };
  31
  32 struct ep93xx_gpio_chip {
  33         void __iomem                    *base;
  34         struct gpio_chip                gc;
  35         struct ep93xx_gpio_irq_chip     *eic;
  36 };
  37
  38 #define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
  39
  40 static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
  41 {
  42         struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
  43
  44         return egc->eic;
  45 }
  46
  47 /*************************************************************************
  48  * Interrupt handling for EP93xx on-chip GPIOs
  49  *************************************************************************/
  50 #define EP93XX_INT_TYPE1_OFFSET         0x00
  51 #define EP93XX_INT_TYPE2_OFFSET         0x04
  52 #define EP93XX_INT_EOI_OFFSET           0x08
  53 #define EP93XX_INT_EN_OFFSET            0x0c
  54 #define EP93XX_INT_STATUS_OFFSET        0x10
  55 #define EP93XX_INT_RAW_STATUS_OFFSET    0x14
  56 #define EP93XX_INT_DEBOUNCE_OFFSET      0x18
  57
  58 static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic)
  59 {
  60         writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET);
  61
  62         writeb_relaxed(eic->int_type2,
  63                        eic->base + EP93XX_INT_TYPE2_OFFSET);
  64
  65         writeb_relaxed(eic->int_type1,
  66                        eic->base + EP93XX_INT_TYPE1_OFFSET);
  67
  68         writeb_relaxed(eic->int_unmasked & eic->int_enabled,
  69                        eic->base + EP93XX_INT_EN_OFFSET);
  70 }
  71
  72 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
  73                                      unsigned int offset, bool enable)
  74 {
  75         struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
  76         int port_mask = BIT(offset);
  77
  78         if (enable)
  79                 eic->int_debounce |= port_mask;
  80         else
  81                 eic->int_debounce &= ~port_mask;
  82
  83         writeb(eic->int_debounce, eic->base + EP93XX_INT_DEBOUNCE_OFFSET);
  84 }
  85
  86 static u32 ep93xx_gpio_ab_irq_handler(struct gpio_chip *gc)
  87 {
  88         struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
  89         unsigned long stat;
  90         int offset;
  91
  92         stat = readb(eic->base + EP93XX_INT_STATUS_OFFSET);
  93         for_each_set_bit(offset, &stat, 8)
  94                 generic_handle_domain_irq(gc->irq.domain, offset);
  95
  96         return stat;
  97 }
  98
  99 static irqreturn_t ep93xx_ab_irq_handler(int irq, void *dev_id)
 100 {
 101         return IRQ_RETVAL(ep93xx_gpio_ab_irq_handler(dev_id));
 102 }
 103
 104 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
 105 {
 106         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 107         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 108         struct gpio_irq_chip *gic = &gc->irq;
 109         unsigned int parent = irq_desc_get_irq(desc);
 110         unsigned int i;
 111
 112         chained_irq_enter(irqchip, desc);
 113         for (i = 0; i < gic->num_parents; i++)
 114                 if (gic->parents[i] == parent)
 115                         break;
 116
 117         if (i < gic->num_parents)
 118                 generic_handle_domain_irq(gc->irq.domain, i);
 119
 120         chained_irq_exit(irqchip, desc);
 121 }
 122
 123 static void ep93xx_gpio_irq_ack(struct irq_data *d)
 124 {
 125         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 126         struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
 127         int port_mask = BIT(irqd_to_hwirq(d));
 128
 129         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
 130                 eic->int_type2 ^= port_mask; /* switch edge direction */
 131                 ep93xx_gpio_update_int_params(eic);
 132         }
 133
 134         writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
 135 }
 136
 137 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
 138 {
 139         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 140         struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
 141         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 142         int port_mask = BIT(hwirq);
 143
 144         if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
 145                 eic->int_type2 ^= port_mask; /* switch edge direction */
 146
 147         eic->int_unmasked &= ~port_mask;
 148         ep93xx_gpio_update_int_params(eic);
 149
 150         writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET);
 151         gpiochip_disable_irq(gc, hwirq);
 152 }
 153
 154 static void ep93xx_gpio_irq_mask(struct irq_data *d)
 155 {
 156         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 157         struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
 158         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 159
 160         eic->int_unmasked &= ~BIT(hwirq);
 161         ep93xx_gpio_update_int_params(eic);
 162         gpiochip_disable_irq(gc, hwirq);
 163 }
 164
 165 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
 166 {
 167         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 168         struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
 169         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 170
 171         gpiochip_enable_irq(gc, hwirq);
 172         eic->int_unmasked |= BIT(hwirq);
 173         ep93xx_gpio_update_int_params(eic);
 174 }
 175
 176 /*
 177  * gpio_int_type1 controls whether the interrupt is level (0) or
 178  * edge (1) triggered, while gpio_int_type2 controls whether it
 179  * triggers on low/falling (0) or high/rising (1).
 180  */
 181 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
 182 {
 183         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 184         struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
 185         irq_hw_number_t hwirq = irqd_to_hwirq(d);
 186         int port_mask = BIT(hwirq);
 187         irq_flow_handler_t handler;
 188
 189         gc->direction_input(gc, hwirq);
 190
 191         switch (type) {
 192         case IRQ_TYPE_EDGE_RISING:
 193                 eic->int_type1 |= port_mask;
 194                 eic->int_type2 |= port_mask;
 195                 handler = handle_edge_irq;
 196                 break;
 197         case IRQ_TYPE_EDGE_FALLING:
 198                 eic->int_type1 |= port_mask;
 199                 eic->int_type2 &= ~port_mask;
 200                 handler = handle_edge_irq;
 201                 break;
 202         case IRQ_TYPE_LEVEL_HIGH:
 203                 eic->int_type1 &= ~port_mask;
 204                 eic->int_type2 |= port_mask;
 205                 handler = handle_level_irq;
 206                 break;
 207         case IRQ_TYPE_LEVEL_LOW:
 208                 eic->int_type1 &= ~port_mask;
 209                 eic->int_type2 &= ~port_mask;
 210                 handler = handle_level_irq;
 211                 break;
 212         case IRQ_TYPE_EDGE_BOTH:
 213                 eic->int_type1 |= port_mask;
 214                 /* set initial polarity based on current input level */
 215                 if (gc->get(gc, hwirq))
 216                         eic->int_type2 &= ~port_mask; /* falling */
 217                 else
 218                         eic->int_type2 |= port_mask; /* rising */
 219                 handler = handle_edge_irq;
 220                 break;
 221         default:
 222                 return -EINVAL;
 223         }
 224
 225         irq_set_handler_locked(d, handler);
 226
 227         eic->int_enabled |= port_mask;
 228
 229         ep93xx_gpio_update_int_params(eic);
 230
 231         return 0;
 232 }
 233
 234 static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
 235                                   unsigned long config)
 236 {
 237         u32 debounce;
 238
 239         if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
 240                 return -ENOTSUPP;
 241
 242         debounce = pinconf_to_config_argument(config);
 243         ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
 244
 245         return 0;
 246 }
 247
 248 static void ep93xx_irq_print_chip(struct irq_data *data, struct seq_file *p)
 249 {
 250         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
 251
 252         seq_puts(p, dev_name(gc->parent));
 253 }
 254
 255 static const struct irq_chip gpio_eic_irq_chip = {
 256         .name                   = "ep93xx-gpio-eic",
 257         .irq_ack                = ep93xx_gpio_irq_ack,
 258         .irq_mask               = ep93xx_gpio_irq_mask,
 259         .irq_unmask             = ep93xx_gpio_irq_unmask,
 260         .irq_mask_ack   = ep93xx_gpio_irq_mask_ack,
 261         .irq_set_type   = ep93xx_gpio_irq_type,
 262         .irq_print_chip = ep93xx_irq_print_chip,
 263         .flags                  = IRQCHIP_IMMUTABLE,
 264         GPIOCHIP_IRQ_RESOURCE_HELPERS,
 265 };
 266
 267 static int ep93xx_setup_irqs(struct platform_device *pdev,
 268                              struct ep93xx_gpio_chip *egc)
 269 {
 270         struct gpio_chip *gc = &egc->gc;
 271         struct device *dev = &pdev->dev;
 272         struct gpio_irq_chip *girq = &gc->irq;
 273         int ret, irq, i;
 274         void __iomem *intr;
 275
 276         intr = devm_platform_ioremap_resource_byname(pdev, "intr");
 277         if (IS_ERR(intr))
 278                 return PTR_ERR(intr);
 279
 280         gc->set_config = ep93xx_gpio_set_config;
 281         egc->eic = devm_kzalloc(dev, sizeof(*egc->eic), GFP_KERNEL);
 282         if (!egc->eic)
 283                 return -ENOMEM;
 284
 285         egc->eic->base = intr;
 286         gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
 287         girq->num_parents = platform_irq_count(pdev);
 288         if (girq->num_parents == 0)
 289                 return -EINVAL;
 290
 291         girq->parents = devm_kcalloc(dev, girq->num_parents, sizeof(*girq->parents),
 292                                      GFP_KERNEL);
 293         if (!girq->parents)
 294                 return -ENOMEM;
 295
 296         if (girq->num_parents == 1) { /* A/B irqchips */
 297                 irq = platform_get_irq(pdev, 0);
 298                 if (irq < 0)
 299                         return irq;
 300
 301                 ret = devm_request_irq(dev, irq, ep93xx_ab_irq_handler,
 302                                        IRQF_SHARED, gc->label, gc);
 303                 if (ret)
 304                         return dev_err_probe(dev, ret, "requesting IRQ: %d\n", irq);
 305
 306                 girq->parents[0] = irq;
 307         } else { /* F irqchip */
 308                 girq->parent_handler = ep93xx_gpio_f_irq_handler;
 309
 310                 for (i = 0; i < girq->num_parents; i++) {
 311                         irq = platform_get_irq_optional(pdev, i);
 312                         if (irq < 0)
 313                                 continue;
 314
 315                         girq->parents[i] = irq;
 316                 }
 317
 318                 girq->map = girq->parents;
 319         }
 320
 321         girq->default_type = IRQ_TYPE_NONE;
 322         /* TODO: replace with handle_bad_irq() once we are fully hierarchical */
 323         girq->handler = handle_simple_irq;
 324
 325         return 0;
 326 }
 327
 328 static int ep93xx_gpio_probe(struct platform_device *pdev)
 329 {
 330         struct ep93xx_gpio_chip *egc;
 331         struct gpio_chip *gc;
 332         void __iomem *data;
 333         void __iomem *dir;
 334         int ret;
 335
 336         egc = devm_kzalloc(&pdev->dev, sizeof(*egc), GFP_KERNEL);
 337         if (!egc)
 338                 return -ENOMEM;
 339
 340         data = devm_platform_ioremap_resource_byname(pdev, "data");
 341         if (IS_ERR(data))
 342                 return PTR_ERR(data);
 343
 344         dir = devm_platform_ioremap_resource_byname(pdev, "dir");
 345         if (IS_ERR(dir))
 346                 return PTR_ERR(dir);
 347
 348         gc = &egc->gc;
 349         ret = bgpio_init(gc, &pdev->dev, 1, data, NULL, NULL, dir, NULL, 0);
 350         if (ret)
 351                 return dev_err_probe(&pdev->dev, ret, "unable to init generic GPIO\n");
 352
 353         gc->label = dev_name(&pdev->dev);
 354         if (platform_irq_count(pdev) > 0) {
 355                 dev_dbg(&pdev->dev, "setting up irqs for %s\n", dev_name(&pdev->dev));
 356                 ret = ep93xx_setup_irqs(pdev, egc);
 357                 if (ret)
 358                         dev_err_probe(&pdev->dev, ret, "setup irqs failed");
 359         }
 360
 361         return devm_gpiochip_add_data(&pdev->dev, gc, egc);
 362 }
 363
 364 static const struct of_device_id ep93xx_gpio_match[] = {
 365         { .compatible = "cirrus,ep9301-gpio" },
 366         { /* sentinel */ }
 367 };
 368
 369 static struct platform_driver ep93xx_gpio_driver = {
 370         .driver         = {
 371                 .name   = "gpio-ep93xx",
 372                 .of_match_table = ep93xx_gpio_match,
 373         },
 374         .probe          = ep93xx_gpio_probe,
 375 };
 376
 377 static int __init ep93xx_gpio_init(void)
 378 {
 379         return platform_driver_register(&ep93xx_gpio_driver);
 380 }
 381 postcore_initcall(ep93xx_gpio_init);
 382
 383 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
 384                 "H Hartley Sweeten <hsweeten@visionengravers.com>");
 385 MODULE_DESCRIPTION("EP93XX GPIO driver");
 386 MODULE_LICENSE("GPL");