drivers/gpio/gpio-pch.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4  */
   5 #include <linux/bits.h>
   6 #include <linux/gpio/driver.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/irq.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13
  14 #define PCH_EDGE_FALLING        0
  15 #define PCH_EDGE_RISING         1
  16 #define PCH_LEVEL_L             2
  17 #define PCH_LEVEL_H             3
  18 #define PCH_EDGE_BOTH           4
  19 #define PCH_IM_MASK             GENMASK(2, 0)
  20
  21 #define PCH_IRQ_BASE            24
  22
  23 struct pch_regs {
  24         u32     ien;
  25         u32     istatus;
  26         u32     idisp;
  27         u32     iclr;
  28         u32     imask;
  29         u32     imaskclr;
  30         u32     po;
  31         u32     pi;
  32         u32     pm;
  33         u32     im0;
  34         u32     im1;
  35         u32     reserved[3];
  36         u32     gpio_use_sel;
  37         u32     reset;
  38 };
  39
  40 #define PCI_DEVICE_ID_INTEL_EG20T_PCH           0x8803
  41 #define PCI_DEVICE_ID_ROHM_ML7223m_IOH          0x8014
  42 #define PCI_DEVICE_ID_ROHM_ML7223n_IOH          0x8043
  43 #define PCI_DEVICE_ID_ROHM_EG20T_PCH            0x8803
  44
  45 enum pch_type_t {
  46         INTEL_EG20T_PCH,
  47         OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
  48         OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
  49 };
  50
  51 /* Specifies number of GPIO PINS */
  52 static int gpio_pins[] = {
  53         [INTEL_EG20T_PCH] = 12,
  54         [OKISEMI_ML7223m_IOH] = 8,
  55         [OKISEMI_ML7223n_IOH] = 8,
  56 };
  57
  58 /**
  59  * struct pch_gpio_reg_data - The register store data.
  60  * @ien_reg:    To store contents of IEN register.
  61  * @imask_reg:  To store contents of IMASK register.
  62  * @po_reg:     To store contents of PO register.
  63  * @pm_reg:     To store contents of PM register.
  64  * @im0_reg:    To store contents of IM0 register.
  65  * @im1_reg:    To store contents of IM1 register.
  66  * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
  67  *                     (Only ML7223 Bus-n)
  68  */
  69 struct pch_gpio_reg_data {
  70         u32 ien_reg;
  71         u32 imask_reg;
  72         u32 po_reg;
  73         u32 pm_reg;
  74         u32 im0_reg;
  75         u32 im1_reg;
  76         u32 gpio_use_sel_reg;
  77 };
  78
  79 /**
  80  * struct pch_gpio - GPIO private data structure.
  81  * @base:                       PCI base address of Memory mapped I/O register.
  82  * @reg:                        Memory mapped PCH GPIO register list.
  83  * @dev:                        Pointer to device structure.
  84  * @gpio:                       Data for GPIO infrastructure.
  85  * @pch_gpio_reg:               Memory mapped Register data is saved here
  86  *                              when suspend.
  87  * @irq_base:           Save base of IRQ number for interrupt
  88  * @ioh:                IOH ID
  89  * @spinlock:           Used for register access protection
  90  */
  91 struct pch_gpio {
  92         void __iomem *base;
  93         struct pch_regs __iomem *reg;
  94         struct device *dev;
  95         struct gpio_chip gpio;
  96         struct pch_gpio_reg_data pch_gpio_reg;
  97         int irq_base;
  98         enum pch_type_t ioh;
  99         spinlock_t spinlock;
 100 };
 101
 102 static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
 103 {
 104         u32 reg_val;
 105         struct pch_gpio *chip = gpiochip_get_data(gpio);
 106         unsigned long flags;
 107
 108         spin_lock_irqsave(&chip->spinlock, flags);
 109         reg_val = ioread32(&chip->reg->po);
 110         if (val)
 111                 reg_val |= BIT(nr);
 112         else
 113                 reg_val &= ~BIT(nr);
 114
 115         iowrite32(reg_val, &chip->reg->po);
 116         spin_unlock_irqrestore(&chip->spinlock, flags);
 117 }
 118
 119 static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
 120 {
 121         struct pch_gpio *chip = gpiochip_get_data(gpio);
 122
 123         return !!(ioread32(&chip->reg->pi) & BIT(nr));
 124 }
 125
 126 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
 127                                      int val)
 128 {
 129         struct pch_gpio *chip = gpiochip_get_data(gpio);
 130         u32 pm;
 131         u32 reg_val;
 132         unsigned long flags;
 133
 134         spin_lock_irqsave(&chip->spinlock, flags);
 135
 136         reg_val = ioread32(&chip->reg->po);
 137         if (val)
 138                 reg_val |= BIT(nr);
 139         else
 140                 reg_val &= ~BIT(nr);
 141         iowrite32(reg_val, &chip->reg->po);
 142
 143         pm = ioread32(&chip->reg->pm);
 144         pm &= BIT(gpio_pins[chip->ioh]) - 1;
 145         pm |= BIT(nr);
 146         iowrite32(pm, &chip->reg->pm);
 147
 148         spin_unlock_irqrestore(&chip->spinlock, flags);
 149
 150         return 0;
 151 }
 152
 153 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
 154 {
 155         struct pch_gpio *chip = gpiochip_get_data(gpio);
 156         u32 pm;
 157         unsigned long flags;
 158
 159         spin_lock_irqsave(&chip->spinlock, flags);
 160         pm = ioread32(&chip->reg->pm);
 161         pm &= BIT(gpio_pins[chip->ioh]) - 1;
 162         pm &= ~BIT(nr);
 163         iowrite32(pm, &chip->reg->pm);
 164         spin_unlock_irqrestore(&chip->spinlock, flags);
 165
 166         return 0;
 167 }
 168
 169 /*
 170  * Save register configuration and disable interrupts.
 171  */
 172 static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
 173 {
 174         chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
 175         chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
 176         chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
 177         chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
 178         chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
 179         if (chip->ioh == INTEL_EG20T_PCH)
 180                 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
 181         if (chip->ioh == OKISEMI_ML7223n_IOH)
 182                 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
 183 }
 184
 185 /*
 186  * This function restores the register configuration of the GPIO device.
 187  */
 188 static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
 189 {
 190         iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
 191         iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
 192         /* to store contents of PO register */
 193         iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
 194         /* to store contents of PM register */
 195         iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
 196         iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
 197         if (chip->ioh == INTEL_EG20T_PCH)
 198                 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
 199         if (chip->ioh == OKISEMI_ML7223n_IOH)
 200                 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
 201 }
 202
 203 static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
 204 {
 205         struct pch_gpio *chip = gpiochip_get_data(gpio);
 206
 207         return chip->irq_base + offset;
 208 }
 209
 210 static void pch_gpio_setup(struct pch_gpio *chip)
 211 {
 212         struct gpio_chip *gpio = &chip->gpio;
 213
 214         gpio->label = dev_name(chip->dev);
 215         gpio->parent = chip->dev;
 216         gpio->owner = THIS_MODULE;
 217         gpio->direction_input = pch_gpio_direction_input;
 218         gpio->get = pch_gpio_get;
 219         gpio->direction_output = pch_gpio_direction_output;
 220         gpio->set = pch_gpio_set;
 221         gpio->base = -1;
 222         gpio->ngpio = gpio_pins[chip->ioh];
 223         gpio->can_sleep = false;
 224         gpio->to_irq = pch_gpio_to_irq;
 225 }
 226
 227 static int pch_irq_type(struct irq_data *d, unsigned int type)
 228 {
 229         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 230         struct pch_gpio *chip = gc->private;
 231         u32 im, im_pos, val;
 232         u32 __iomem *im_reg;
 233         unsigned long flags;
 234         int ch, irq = d->irq;
 235
 236         ch = irq - chip->irq_base;
 237         if (irq < chip->irq_base + 8) {
 238                 im_reg = &chip->reg->im0;
 239                 im_pos = ch - 0;
 240         } else {
 241                 im_reg = &chip->reg->im1;
 242                 im_pos = ch - 8;
 243         }
 244         dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
 245
 246         switch (type) {
 247         case IRQ_TYPE_EDGE_RISING:
 248                 val = PCH_EDGE_RISING;
 249                 break;
 250         case IRQ_TYPE_EDGE_FALLING:
 251                 val = PCH_EDGE_FALLING;
 252                 break;
 253         case IRQ_TYPE_EDGE_BOTH:
 254                 val = PCH_EDGE_BOTH;
 255                 break;
 256         case IRQ_TYPE_LEVEL_HIGH:
 257                 val = PCH_LEVEL_H;
 258                 break;
 259         case IRQ_TYPE_LEVEL_LOW:
 260                 val = PCH_LEVEL_L;
 261                 break;
 262         default:
 263                 return 0;
 264         }
 265
 266         spin_lock_irqsave(&chip->spinlock, flags);
 267
 268         /* Set interrupt mode */
 269         im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
 270         iowrite32(im | (val << (im_pos * 4)), im_reg);
 271
 272         /* And the handler */
 273         if (type & IRQ_TYPE_LEVEL_MASK)
 274                 irq_set_handler_locked(d, handle_level_irq);
 275         else if (type & IRQ_TYPE_EDGE_BOTH)
 276                 irq_set_handler_locked(d, handle_edge_irq);
 277
 278         spin_unlock_irqrestore(&chip->spinlock, flags);
 279         return 0;
 280 }
 281
 282 static void pch_irq_unmask(struct irq_data *d)
 283 {
 284         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 285         struct pch_gpio *chip = gc->private;
 286
 287         iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
 288 }
 289
 290 static void pch_irq_mask(struct irq_data *d)
 291 {
 292         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 293         struct pch_gpio *chip = gc->private;
 294
 295         iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
 296 }
 297
 298 static void pch_irq_ack(struct irq_data *d)
 299 {
 300         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 301         struct pch_gpio *chip = gc->private;
 302
 303         iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
 304 }
 305
 306 static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
 307 {
 308         struct pch_gpio *chip = dev_id;
 309         unsigned long reg_val = ioread32(&chip->reg->istatus);
 310         int i;
 311
 312         dev_vdbg(chip->dev, "irq=%d  status=0x%lx\n", irq, reg_val);
 313
 314         reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
 315
 316         for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])
 317                 generic_handle_irq(chip->irq_base + i);
 318
 319         return IRQ_RETVAL(reg_val);
 320 }
 321
 322 static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
 323                                        unsigned int irq_start,
 324                                        unsigned int num)
 325 {
 326         struct irq_chip_generic *gc;
 327         struct irq_chip_type *ct;
 328         int rv;
 329
 330         gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
 331                                          chip->base, handle_simple_irq);
 332         if (!gc)
 333                 return -ENOMEM;
 334
 335         gc->private = chip;
 336         ct = gc->chip_types;
 337
 338         ct->chip.irq_ack = pch_irq_ack;
 339         ct->chip.irq_mask = pch_irq_mask;
 340         ct->chip.irq_unmask = pch_irq_unmask;
 341         ct->chip.irq_set_type = pch_irq_type;
 342
 343         rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
 344                                          IRQ_GC_INIT_MASK_CACHE,
 345                                          IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 346
 347         return rv;
 348 }
 349
 350 static int pch_gpio_probe(struct pci_dev *pdev,
 351                                     const struct pci_device_id *id)
 352 {
 353         struct device *dev = &pdev->dev;
 354         s32 ret;
 355         struct pch_gpio *chip;
 356         int irq_base;
 357
 358         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
 359         if (chip == NULL)
 360                 return -ENOMEM;
 361
 362         chip->dev = dev;
 363         ret = pcim_enable_device(pdev);
 364         if (ret)
 365                 return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
 366
 367         ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
 368         if (ret)
 369                 return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n");
 370
 371         chip->base = pcim_iomap_table(pdev)[1];
 372         chip->ioh = id->driver_data;
 373         chip->reg = chip->base;
 374         pci_set_drvdata(pdev, chip);
 375         spin_lock_init(&chip->spinlock);
 376         pch_gpio_setup(chip);
 377
 378         ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
 379         if (ret)
 380                 return dev_err_probe(dev, ret, "Failed to register GPIO\n");
 381
 382         irq_base = devm_irq_alloc_descs(dev, -1, 0,
 383                                         gpio_pins[chip->ioh], NUMA_NO_NODE);
 384         if (irq_base < 0) {
 385                 dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n");
 386                 chip->irq_base = -1;
 387                 return 0;
 388         }
 389         chip->irq_base = irq_base;
 390
 391         /* Mask all interrupts, but enable them */
 392         iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
 393         iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
 394
 395         ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
 396                                IRQF_SHARED, KBUILD_MODNAME, chip);
 397         if (ret)
 398                 return dev_err_probe(dev, ret, "Failed to request IRQ\n");
 399
 400         return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
 401 }
 402
 403 static int __maybe_unused pch_gpio_suspend(struct device *dev)
 404 {
 405         struct pch_gpio *chip = dev_get_drvdata(dev);
 406         unsigned long flags;
 407
 408         spin_lock_irqsave(&chip->spinlock, flags);
 409         pch_gpio_save_reg_conf(chip);
 410         spin_unlock_irqrestore(&chip->spinlock, flags);
 411
 412         return 0;
 413 }
 414
 415 static int __maybe_unused pch_gpio_resume(struct device *dev)
 416 {
 417         struct pch_gpio *chip = dev_get_drvdata(dev);
 418         unsigned long flags;
 419
 420         spin_lock_irqsave(&chip->spinlock, flags);
 421         iowrite32(0x01, &chip->reg->reset);
 422         iowrite32(0x00, &chip->reg->reset);
 423         pch_gpio_restore_reg_conf(chip);
 424         spin_unlock_irqrestore(&chip->spinlock, flags);
 425
 426         return 0;
 427 }
 428
 429 static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
 430
 431 static const struct pci_device_id pch_gpio_pcidev_id[] = {
 432         { PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) },
 433         { PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) },
 434         { PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) },
 435         { PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) },
 436         { }
 437 };
 438 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
 439
 440 static struct pci_driver pch_gpio_driver = {
 441         .name = "pch_gpio",
 442         .id_table = pch_gpio_pcidev_id,
 443         .probe = pch_gpio_probe,
 444         .driver = {
 445                 .pm = &pch_gpio_pm_ops,
 446         },
 447 };
 448
 449 module_pci_driver(pch_gpio_driver);
 450
 451 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
 452 MODULE_LICENSE("GPL v2");