drivers/gpio/gpio-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * arch/arm/mach-tegra/gpio.c
   4  *
   5  * Copyright (c) 2010 Google, Inc
   6  * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
   7  *
   8  * Author:
   9  *      Erik Gilling <konkers@google.com>
  10  */
  11
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/gpio/driver.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/module.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/irqchip/chained_irq.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pm.h>
  25 #include <linux/property.h>
  26 #include <linux/seq_file.h>
  27
  28 #define GPIO_BANK(x)            ((x) >> 5)
  29 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  30 #define GPIO_BIT(x)             ((x) & 0x7)
  31
  32 #define GPIO_REG(tgi, x)        (GPIO_BANK(x) * tgi->soc->bank_stride + \
  33                                         GPIO_PORT(x) * 4)
  34
  35 #define GPIO_CNF(t, x)          (GPIO_REG(t, x) + 0x00)
  36 #define GPIO_OE(t, x)           (GPIO_REG(t, x) + 0x10)
  37 #define GPIO_OUT(t, x)          (GPIO_REG(t, x) + 0X20)
  38 #define GPIO_IN(t, x)           (GPIO_REG(t, x) + 0x30)
  39 #define GPIO_INT_STA(t, x)      (GPIO_REG(t, x) + 0x40)
  40 #define GPIO_INT_ENB(t, x)      (GPIO_REG(t, x) + 0x50)
  41 #define GPIO_INT_LVL(t, x)      (GPIO_REG(t, x) + 0x60)
  42 #define GPIO_INT_CLR(t, x)      (GPIO_REG(t, x) + 0x70)
  43 #define GPIO_DBC_CNT(t, x)      (GPIO_REG(t, x) + 0xF0)
  44
  45
  46 #define GPIO_MSK_CNF(t, x)      (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
  47 #define GPIO_MSK_OE(t, x)       (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
  48 #define GPIO_MSK_OUT(t, x)      (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
  49 #define GPIO_MSK_DBC_EN(t, x)   (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
  50 #define GPIO_MSK_INT_STA(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
  51 #define GPIO_MSK_INT_ENB(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
  52 #define GPIO_MSK_INT_LVL(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
  53
  54 #define GPIO_INT_LVL_MASK               0x010101
  55 #define GPIO_INT_LVL_EDGE_RISING        0x000101
  56 #define GPIO_INT_LVL_EDGE_FALLING       0x000100
  57 #define GPIO_INT_LVL_EDGE_BOTH          0x010100
  58 #define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  59 #define GPIO_INT_LVL_LEVEL_LOW          0x000000
  60
  61 struct tegra_gpio_info;
  62
  63 struct tegra_gpio_bank {
  64         unsigned int bank;
  65
  66         /*
  67          * IRQ-core code uses raw locking, and thus, nested locking also
  68          * should be raw in order not to trip spinlock debug warnings.
  69          */
  70         raw_spinlock_t lvl_lock[4];
  71
  72         /* Lock for updating debounce count register */
  73         spinlock_t dbc_lock[4];
  74
  75 #ifdef CONFIG_PM_SLEEP
  76         u32 cnf[4];
  77         u32 out[4];
  78         u32 oe[4];
  79         u32 int_enb[4];
  80         u32 int_lvl[4];
  81         u32 wake_enb[4];
  82         u32 dbc_enb[4];
  83 #endif
  84         u32 dbc_cnt[4];
  85 };
  86
  87 struct tegra_gpio_soc_config {
  88         bool debounce_supported;
  89         u32 bank_stride;
  90         u32 upper_offset;
  91 };
  92
  93 struct tegra_gpio_info {
  94         struct device                           *dev;
  95         void __iomem                            *regs;
  96         struct tegra_gpio_bank                  *bank_info;
  97         const struct tegra_gpio_soc_config      *soc;
  98         struct gpio_chip                        gc;
  99         u32                                     bank_count;
 100         unsigned int                            *irqs;
 101 };
 102
 103 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
 104                                      u32 val, u32 reg)
 105 {
 106         writel_relaxed(val, tgi->regs + reg);
 107 }
 108
 109 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
 110 {
 111         return readl_relaxed(tgi->regs + reg);
 112 }
 113
 114 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
 115                                        unsigned int bit)
 116 {
 117         return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
 118 }
 119
 120 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
 121                                   unsigned int gpio, u32 value)
 122 {
 123         u32 val;
 124
 125         val = 0x100 << GPIO_BIT(gpio);
 126         if (value)
 127                 val |= 1 << GPIO_BIT(gpio);
 128         tegra_gpio_writel(tgi, val, reg);
 129 }
 130
 131 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
 132 {
 133         tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
 134 }
 135
 136 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
 137 {
 138         tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
 139 }
 140
 141 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
 142 {
 143         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 144
 145         pinctrl_gpio_free(chip, offset);
 146         tegra_gpio_disable(tgi, offset);
 147 }
 148
 149 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
 150                            int value)
 151 {
 152         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 153
 154         tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
 155 }
 156
 157 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
 158 {
 159         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 160         unsigned int bval = BIT(GPIO_BIT(offset));
 161
 162         /* If gpio is in output mode then read from the out value */
 163         if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
 164                 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
 165
 166         return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
 167 }
 168
 169 static int tegra_gpio_direction_input(struct gpio_chip *chip,
 170                                       unsigned int offset)
 171 {
 172         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 173         int ret;
 174
 175         tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
 176         tegra_gpio_enable(tgi, offset);
 177
 178         ret = pinctrl_gpio_direction_input(chip, offset);
 179         if (ret < 0)
 180                 dev_err(tgi->dev,
 181                         "Failed to set pinctrl input direction of GPIO %d: %d",
 182                          chip->base + offset, ret);
 183
 184         return ret;
 185 }
 186
 187 static int tegra_gpio_direction_output(struct gpio_chip *chip,
 188                                        unsigned int offset,
 189                                        int value)
 190 {
 191         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 192         int ret;
 193
 194         tegra_gpio_set(chip, offset, value);
 195         tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
 196         tegra_gpio_enable(tgi, offset);
 197
 198         ret = pinctrl_gpio_direction_output(chip, offset);
 199         if (ret < 0)
 200                 dev_err(tgi->dev,
 201                         "Failed to set pinctrl output direction of GPIO %d: %d",
 202                          chip->base + offset, ret);
 203
 204         return ret;
 205 }
 206
 207 static int tegra_gpio_get_direction(struct gpio_chip *chip,
 208                                     unsigned int offset)
 209 {
 210         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 211         u32 pin_mask = BIT(GPIO_BIT(offset));
 212         u32 cnf, oe;
 213
 214         cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
 215         if (!(cnf & pin_mask))
 216                 return -EINVAL;
 217
 218         oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
 219
 220         if (oe & pin_mask)
 221                 return GPIO_LINE_DIRECTION_OUT;
 222
 223         return GPIO_LINE_DIRECTION_IN;
 224 }
 225
 226 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
 227                                    unsigned int debounce)
 228 {
 229         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 230         struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
 231         unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
 232         unsigned long flags;
 233         unsigned int port;
 234
 235         if (!debounce_ms) {
 236                 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
 237                                       offset, 0);
 238                 return 0;
 239         }
 240
 241         debounce_ms = min(debounce_ms, 255U);
 242         port = GPIO_PORT(offset);
 243
 244         /* There is only one debounce count register per port and hence
 245          * set the maximum of current and requested debounce time.
 246          */
 247         spin_lock_irqsave(&bank->dbc_lock[port], flags);
 248         if (bank->dbc_cnt[port] < debounce_ms) {
 249                 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
 250                 bank->dbc_cnt[port] = debounce_ms;
 251         }
 252         spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
 253
 254         tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
 255
 256         return 0;
 257 }
 258
 259 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
 260                                  unsigned long config)
 261 {
 262         u32 debounce;
 263
 264         if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
 265                 return -ENOTSUPP;
 266
 267         debounce = pinconf_to_config_argument(config);
 268         return tegra_gpio_set_debounce(chip, offset, debounce);
 269 }
 270
 271 static void tegra_gpio_irq_ack(struct irq_data *d)
 272 {
 273         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 274         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 275         unsigned int gpio = d->hwirq;
 276
 277         tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
 278 }
 279
 280 static void tegra_gpio_irq_mask(struct irq_data *d)
 281 {
 282         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 283         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 284         unsigned int gpio = d->hwirq;
 285
 286         tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
 287         gpiochip_disable_irq(chip, gpio);
 288 }
 289
 290 static void tegra_gpio_irq_unmask(struct irq_data *d)
 291 {
 292         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 293         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 294         unsigned int gpio = d->hwirq;
 295
 296         gpiochip_enable_irq(chip, gpio);
 297         tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
 298 }
 299
 300 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 301 {
 302         unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
 303         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 304         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 305         struct tegra_gpio_bank *bank;
 306         unsigned long flags;
 307         int ret;
 308         u32 val;
 309
 310         bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
 311
 312         switch (type & IRQ_TYPE_SENSE_MASK) {
 313         case IRQ_TYPE_EDGE_RISING:
 314                 lvl_type = GPIO_INT_LVL_EDGE_RISING;
 315                 break;
 316
 317         case IRQ_TYPE_EDGE_FALLING:
 318                 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 319                 break;
 320
 321         case IRQ_TYPE_EDGE_BOTH:
 322                 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 323                 break;
 324
 325         case IRQ_TYPE_LEVEL_HIGH:
 326                 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 327                 break;
 328
 329         case IRQ_TYPE_LEVEL_LOW:
 330                 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 331                 break;
 332
 333         default:
 334                 return -EINVAL;
 335         }
 336
 337         raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
 338
 339         val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
 340         val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 341         val |= lvl_type << GPIO_BIT(gpio);
 342         tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
 343
 344         raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 345
 346         tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
 347         tegra_gpio_enable(tgi, gpio);
 348
 349         ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
 350         if (ret) {
 351                 dev_err(tgi->dev,
 352                         "unable to lock Tegra GPIO %u as IRQ\n", gpio);
 353                 tegra_gpio_disable(tgi, gpio);
 354                 return ret;
 355         }
 356
 357         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 358                 irq_set_handler_locked(d, handle_level_irq);
 359         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 360                 irq_set_handler_locked(d, handle_edge_irq);
 361
 362         if (d->parent_data)
 363                 ret = irq_chip_set_type_parent(d, type);
 364
 365         return ret;
 366 }
 367
 368 static void tegra_gpio_irq_shutdown(struct irq_data *d)
 369 {
 370         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 371         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 372         unsigned int gpio = d->hwirq;
 373
 374         tegra_gpio_irq_mask(d);
 375         gpiochip_unlock_as_irq(&tgi->gc, gpio);
 376 }
 377
 378 static void tegra_gpio_irq_handler(struct irq_desc *desc)
 379 {
 380         struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc);
 381         struct irq_chip *chip = irq_desc_get_chip(desc);
 382         struct irq_domain *domain = tgi->gc.irq.domain;
 383         unsigned int irq = irq_desc_get_irq(desc);
 384         struct tegra_gpio_bank *bank = NULL;
 385         unsigned int port, pin, gpio, i;
 386         bool unmasked = false;
 387         unsigned long sta;
 388         u32 lvl;
 389
 390         for (i = 0; i < tgi->bank_count; i++) {
 391                 if (tgi->irqs[i] == irq) {
 392                         bank = &tgi->bank_info[i];
 393                         break;
 394                 }
 395         }
 396
 397         if (WARN_ON(bank == NULL))
 398                 return;
 399
 400         chained_irq_enter(chip, desc);
 401
 402         for (port = 0; port < 4; port++) {
 403                 gpio = tegra_gpio_compose(bank->bank, port, 0);
 404                 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
 405                         tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
 406                 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
 407
 408                 for_each_set_bit(pin, &sta, 8) {
 409                         int ret;
 410
 411                         tegra_gpio_writel(tgi, 1 << pin,
 412                                           GPIO_INT_CLR(tgi, gpio));
 413
 414                         /* if gpio is edge triggered, clear condition
 415                          * before executing the handler so that we don't
 416                          * miss edges
 417                          */
 418                         if (!unmasked && lvl & (0x100 << pin)) {
 419                                 unmasked = true;
 420                                 chained_irq_exit(chip, desc);
 421                         }
 422
 423                         ret = generic_handle_domain_irq(domain, gpio + pin);
 424                         WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
 425                 }
 426         }
 427
 428         if (!unmasked)
 429                 chained_irq_exit(chip, desc);
 430 }
 431
 432 static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
 433                                             unsigned int hwirq,
 434                                             unsigned int type,
 435                                             unsigned int *parent_hwirq,
 436                                             unsigned int *parent_type)
 437 {
 438         *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
 439         *parent_type = type;
 440
 441         return 0;
 442 }
 443
 444 static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,
 445                                              union gpio_irq_fwspec *gfwspec,
 446                                              unsigned int parent_hwirq,
 447                                              unsigned int parent_type)
 448 {
 449         struct irq_fwspec *fwspec = &gfwspec->fwspec;
 450
 451         fwspec->fwnode = chip->irq.parent_domain->fwnode;
 452         fwspec->param_count = 3;
 453         fwspec->param[0] = 0;
 454         fwspec->param[1] = parent_hwirq;
 455         fwspec->param[2] = parent_type;
 456
 457         return 0;
 458 }
 459
 460 #ifdef CONFIG_PM_SLEEP
 461 static int tegra_gpio_resume(struct device *dev)
 462 {
 463         struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
 464         unsigned int b, p;
 465
 466         for (b = 0; b < tgi->bank_count; b++) {
 467                 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
 468
 469                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 470                         unsigned int gpio = (b << 5) | (p << 3);
 471
 472                         tegra_gpio_writel(tgi, bank->cnf[p],
 473                                           GPIO_CNF(tgi, gpio));
 474
 475                         if (tgi->soc->debounce_supported) {
 476                                 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
 477                                                   GPIO_DBC_CNT(tgi, gpio));
 478                                 tegra_gpio_writel(tgi, bank->dbc_enb[p],
 479                                                   GPIO_MSK_DBC_EN(tgi, gpio));
 480                         }
 481
 482                         tegra_gpio_writel(tgi, bank->out[p],
 483                                           GPIO_OUT(tgi, gpio));
 484                         tegra_gpio_writel(tgi, bank->oe[p],
 485                                           GPIO_OE(tgi, gpio));
 486                         tegra_gpio_writel(tgi, bank->int_lvl[p],
 487                                           GPIO_INT_LVL(tgi, gpio));
 488                         tegra_gpio_writel(tgi, bank->int_enb[p],
 489                                           GPIO_INT_ENB(tgi, gpio));
 490                 }
 491         }
 492
 493         return 0;
 494 }
 495
 496 static int tegra_gpio_suspend(struct device *dev)
 497 {
 498         struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
 499         unsigned int b, p;
 500
 501         for (b = 0; b < tgi->bank_count; b++) {
 502                 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
 503
 504                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 505                         unsigned int gpio = (b << 5) | (p << 3);
 506
 507                         bank->cnf[p] = tegra_gpio_readl(tgi,
 508                                                         GPIO_CNF(tgi, gpio));
 509                         bank->out[p] = tegra_gpio_readl(tgi,
 510                                                         GPIO_OUT(tgi, gpio));
 511                         bank->oe[p] = tegra_gpio_readl(tgi,
 512                                                        GPIO_OE(tgi, gpio));
 513                         if (tgi->soc->debounce_supported) {
 514                                 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
 515                                                 GPIO_MSK_DBC_EN(tgi, gpio));
 516                                 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
 517                                                         bank->dbc_enb[p];
 518                         }
 519
 520                         bank->int_enb[p] = tegra_gpio_readl(tgi,
 521                                                 GPIO_INT_ENB(tgi, gpio));
 522                         bank->int_lvl[p] = tegra_gpio_readl(tgi,
 523                                                 GPIO_INT_LVL(tgi, gpio));
 524
 525                         /* Enable gpio irq for wake up source */
 526                         tegra_gpio_writel(tgi, bank->wake_enb[p],
 527                                           GPIO_INT_ENB(tgi, gpio));
 528                 }
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 535 {
 536         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 537         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 538         struct tegra_gpio_bank *bank;
 539         unsigned int gpio = d->hwirq;
 540         u32 port, bit, mask;
 541         int err;
 542
 543         bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
 544
 545         port = GPIO_PORT(gpio);
 546         bit = GPIO_BIT(gpio);
 547         mask = BIT(bit);
 548
 549         err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);
 550         if (err)
 551                 return err;
 552
 553         if (d->parent_data) {
 554                 err = irq_chip_set_wake_parent(d, enable);
 555                 if (err) {
 556                         irq_set_irq_wake(tgi->irqs[bank->bank], !enable);
 557                         return err;
 558                 }
 559         }
 560
 561         if (enable)
 562                 bank->wake_enb[port] |= mask;
 563         else
 564                 bank->wake_enb[port] &= ~mask;
 565
 566         return 0;
 567 }
 568 #endif
 569
 570 static int tegra_gpio_irq_set_affinity(struct irq_data *data,
 571                                        const struct cpumask *dest,
 572                                        bool force)
 573 {
 574         if (data->parent_data)
 575                 return irq_chip_set_affinity_parent(data, dest, force);
 576
 577         return -EINVAL;
 578 }
 579
 580 static int tegra_gpio_irq_request_resources(struct irq_data *d)
 581 {
 582         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 583         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 584
 585         tegra_gpio_enable(tgi, d->hwirq);
 586
 587         return gpiochip_reqres_irq(chip, d->hwirq);
 588 }
 589
 590 static void tegra_gpio_irq_release_resources(struct irq_data *d)
 591 {
 592         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 593         struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
 594
 595         gpiochip_relres_irq(chip, d->hwirq);
 596         tegra_gpio_enable(tgi, d->hwirq);
 597 }
 598
 599 static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s)
 600 {
 601         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
 602
 603         seq_puts(s, dev_name(chip->parent));
 604 }
 605
 606 static const struct irq_chip tegra_gpio_irq_chip = {
 607         .irq_shutdown           = tegra_gpio_irq_shutdown,
 608         .irq_ack                = tegra_gpio_irq_ack,
 609         .irq_mask               = tegra_gpio_irq_mask,
 610         .irq_unmask             = tegra_gpio_irq_unmask,
 611         .irq_set_type           = tegra_gpio_irq_set_type,
 612 #ifdef CONFIG_PM_SLEEP
 613         .irq_set_wake           = tegra_gpio_irq_set_wake,
 614 #endif
 615         .irq_print_chip         = tegra_gpio_irq_print_chip,
 616         .irq_request_resources  = tegra_gpio_irq_request_resources,
 617         .irq_release_resources  = tegra_gpio_irq_release_resources,
 618         .flags                  = IRQCHIP_IMMUTABLE,
 619 };
 620
 621 static const struct irq_chip tegra210_gpio_irq_chip = {
 622         .irq_shutdown           = tegra_gpio_irq_shutdown,
 623         .irq_ack                = tegra_gpio_irq_ack,
 624         .irq_mask               = tegra_gpio_irq_mask,
 625         .irq_unmask             = tegra_gpio_irq_unmask,
 626         .irq_set_affinity       = tegra_gpio_irq_set_affinity,
 627         .irq_set_type           = tegra_gpio_irq_set_type,
 628 #ifdef CONFIG_PM_SLEEP
 629         .irq_set_wake           = tegra_gpio_irq_set_wake,
 630 #endif
 631         .irq_print_chip         = tegra_gpio_irq_print_chip,
 632         .irq_request_resources  = tegra_gpio_irq_request_resources,
 633         .irq_release_resources  = tegra_gpio_irq_release_resources,
 634         .flags                  = IRQCHIP_IMMUTABLE,
 635 };
 636
 637 #ifdef  CONFIG_DEBUG_FS
 638
 639 #include <linux/debugfs.h>
 640
 641 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
 642 {
 643         struct tegra_gpio_info *tgi = dev_get_drvdata(s->private);
 644         unsigned int i, j;
 645
 646         for (i = 0; i < tgi->bank_count; i++) {
 647                 for (j = 0; j < 4; j++) {
 648                         unsigned int gpio = tegra_gpio_compose(i, j, 0);
 649
 650                         seq_printf(s,
 651                                 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
 652                                 i, j,
 653                                 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
 654                                 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
 655                                 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
 656                                 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
 657                                 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
 658                                 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
 659                                 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
 660                 }
 661         }
 662         return 0;
 663 }
 664
 665 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
 666 {
 667         debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL,
 668                                     tegra_dbg_gpio_show);
 669 }
 670
 671 #else
 672
 673 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
 674 {
 675 }
 676
 677 #endif
 678
 679 static const struct dev_pm_ops tegra_gpio_pm_ops = {
 680         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
 681 };
 682
 683 static const struct of_device_id tegra_pmc_of_match[] = {
 684         { .compatible = "nvidia,tegra210-pmc", },
 685         { /* sentinel */ },
 686 };
 687
 688 static int tegra_gpio_probe(struct platform_device *pdev)
 689 {
 690         struct tegra_gpio_bank *bank;
 691         struct tegra_gpio_info *tgi;
 692         struct gpio_irq_chip *irq;
 693         struct device_node *np;
 694         unsigned int i, j;
 695         int ret;
 696
 697         tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
 698         if (!tgi)
 699                 return -ENODEV;
 700
 701         tgi->soc = of_device_get_match_data(&pdev->dev);
 702         tgi->dev = &pdev->dev;
 703
 704         ret = platform_irq_count(pdev);
 705         if (ret < 0)
 706                 return ret;
 707
 708         tgi->bank_count = ret;
 709
 710         if (!tgi->bank_count) {
 711                 dev_err(&pdev->dev, "Missing IRQ resource\n");
 712                 return -ENODEV;
 713         }
 714
 715         tgi->gc.label                   = "tegra-gpio";
 716         tgi->gc.request                 = pinctrl_gpio_request;
 717         tgi->gc.free                    = tegra_gpio_free;
 718         tgi->gc.direction_input         = tegra_gpio_direction_input;
 719         tgi->gc.get                     = tegra_gpio_get;
 720         tgi->gc.direction_output        = tegra_gpio_direction_output;
 721         tgi->gc.set                     = tegra_gpio_set;
 722         tgi->gc.get_direction           = tegra_gpio_get_direction;
 723         tgi->gc.base                    = 0;
 724         tgi->gc.ngpio                   = tgi->bank_count * 32;
 725         tgi->gc.parent                  = &pdev->dev;
 726
 727         platform_set_drvdata(pdev, tgi);
 728
 729         if (tgi->soc->debounce_supported)
 730                 tgi->gc.set_config = tegra_gpio_set_config;
 731
 732         tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
 733                                       sizeof(*tgi->bank_info), GFP_KERNEL);
 734         if (!tgi->bank_info)
 735                 return -ENOMEM;
 736
 737         tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count,
 738                                  sizeof(*tgi->irqs), GFP_KERNEL);
 739         if (!tgi->irqs)
 740                 return -ENOMEM;
 741
 742         for (i = 0; i < tgi->bank_count; i++) {
 743                 ret = platform_get_irq(pdev, i);
 744                 if (ret < 0)
 745                         return ret;
 746
 747                 bank = &tgi->bank_info[i];
 748                 bank->bank = i;
 749
 750                 tgi->irqs[i] = ret;
 751
 752                 for (j = 0; j < 4; j++) {
 753                         raw_spin_lock_init(&bank->lvl_lock[j]);
 754                         spin_lock_init(&bank->dbc_lock[j]);
 755                 }
 756         }
 757
 758         irq = &tgi->gc.irq;
 759         irq->fwnode = dev_fwnode(&pdev->dev);
 760         irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq;
 761         irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec;
 762         irq->handler = handle_simple_irq;
 763         irq->default_type = IRQ_TYPE_NONE;
 764         irq->parent_handler = tegra_gpio_irq_handler;
 765         irq->parent_handler_data = tgi;
 766         irq->num_parents = tgi->bank_count;
 767         irq->parents = tgi->irqs;
 768
 769         np = of_find_matching_node(NULL, tegra_pmc_of_match);
 770         if (np) {
 771                 irq->parent_domain = irq_find_host(np);
 772                 of_node_put(np);
 773
 774                 if (!irq->parent_domain)
 775                         return -EPROBE_DEFER;
 776
 777                 gpio_irq_chip_set_chip(irq, &tegra210_gpio_irq_chip);
 778         } else {
 779                 gpio_irq_chip_set_chip(irq, &tegra_gpio_irq_chip);
 780         }
 781
 782         tgi->regs = devm_platform_ioremap_resource(pdev, 0);
 783         if (IS_ERR(tgi->regs))
 784                 return PTR_ERR(tgi->regs);
 785
 786         for (i = 0; i < tgi->bank_count; i++) {
 787                 for (j = 0; j < 4; j++) {
 788                         int gpio = tegra_gpio_compose(i, j, 0);
 789
 790                         tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
 791                 }
 792         }
 793
 794         ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
 795         if (ret < 0)
 796                 return ret;
 797
 798         tegra_gpio_debuginit(tgi);
 799
 800         return 0;
 801 }
 802
 803 static const struct tegra_gpio_soc_config tegra20_gpio_config = {
 804         .bank_stride = 0x80,
 805         .upper_offset = 0x800,
 806 };
 807
 808 static const struct tegra_gpio_soc_config tegra30_gpio_config = {
 809         .bank_stride = 0x100,
 810         .upper_offset = 0x80,
 811 };
 812
 813 static const struct tegra_gpio_soc_config tegra210_gpio_config = {
 814         .debounce_supported = true,
 815         .bank_stride = 0x100,
 816         .upper_offset = 0x80,
 817 };
 818
 819 static const struct of_device_id tegra_gpio_of_match[] = {
 820         { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
 821         { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
 822         { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
 823         { },
 824 };
 825 MODULE_DEVICE_TABLE(of, tegra_gpio_of_match);
 826
 827 static struct platform_driver tegra_gpio_driver = {
 828         .driver = {
 829                 .name = "tegra-gpio",
 830                 .pm = &tegra_gpio_pm_ops,
 831                 .of_match_table = tegra_gpio_of_match,
 832         },
 833         .probe = tegra_gpio_probe,
 834 };
 835 module_platform_driver(tegra_gpio_driver);
 836
 837 MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver");
 838 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
 839 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 840 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
 841 MODULE_AUTHOR("Erik Gilling <konkers@google.com>");
 842 MODULE_LICENSE("GPL v2");