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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / iio / addac / ad74115.c
bloba7e480f2472db972536de3d77d4aabefb8353027
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2022 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/crc8.h>
10 #include <linux/device.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/spi/spi.h>
17 #include <linux/units.h>
18
19 #include <linux/unaligned.h>
20
21 #include <linux/iio/buffer.h>
22 #include <linux/iio/iio.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26
27 #define AD74115_NAME "ad74115"
28
29 #define AD74115_CH_FUNC_SETUP_REG 0x01
30
31 #define AD74115_ADC_CONFIG_REG 0x02
32 #define AD74115_ADC_CONFIG_CONV2_RATE_MASK GENMASK(15, 13)
33 #define AD74115_ADC_CONFIG_CONV1_RATE_MASK GENMASK(12, 10)
34 #define AD74115_ADC_CONFIG_CONV2_RANGE_MASK GENMASK(9, 7)
35 #define AD74115_ADC_CONFIG_CONV1_RANGE_MASK GENMASK(6, 4)
36
37 #define AD74115_PWR_OPTIM_CONFIG_REG 0x03
38
39 #define AD74115_DIN_CONFIG1_REG 0x04
40 #define AD74115_DIN_COMPARATOR_EN_MASK BIT(13)
41 #define AD74115_DIN_SINK_MASK GENMASK(11, 7)
42 #define AD74115_DIN_DEBOUNCE_MASK GENMASK(4, 0)
43
44 #define AD74115_DIN_CONFIG2_REG 0x05
45 #define AD74115_COMP_THRESH_MASK GENMASK(6, 0)
46
47 #define AD74115_OUTPUT_CONFIG_REG 0x06
48 #define AD74115_OUTPUT_SLEW_EN_MASK GENMASK(6, 5)
49 #define AD74115_OUTPUT_SLEW_LIN_STEP_MASK GENMASK(4, 3)
50 #define AD74115_OUTPUT_SLEW_LIN_RATE_MASK GENMASK(2, 1)
51
52 #define AD74115_RTD3W4W_CONFIG_REG 0x07
53
54 #define AD74115_BURNOUT_CONFIG_REG 0x0a
55 #define AD74115_BURNOUT_EXT2_EN_MASK BIT(10)
56 #define AD74115_BURNOUT_EXT1_EN_MASK BIT(5)
57 #define AD74115_BURNOUT_VIOUT_EN_MASK BIT(0)
58
59 #define AD74115_DAC_CODE_REG 0x0b
60
61 #define AD74115_DAC_ACTIVE_REG 0x0d
62
63 #define AD74115_GPIO_CONFIG_X_REG(x) (0x35 + (x))
64 #define AD74115_GPIO_CONFIG_GPI_DATA BIT(5)
65 #define AD74115_GPIO_CONFIG_GPO_DATA BIT(4)
66 #define AD74115_GPIO_CONFIG_SELECT_MASK GENMASK(2, 0)
67
68 #define AD74115_CHARGE_PUMP_REG 0x3a
69
70 #define AD74115_ADC_CONV_CTRL_REG 0x3b
71 #define AD74115_ADC_CONV_SEQ_MASK GENMASK(13, 12)
72
73 #define AD74115_DIN_COMP_OUT_REG 0x40
74
75 #define AD74115_LIVE_STATUS_REG 0x42
76 #define AD74115_ADC_DATA_RDY_MASK BIT(3)
77
78 #define AD74115_READ_SELECT_REG 0x64
79
80 #define AD74115_CMD_KEY_REG 0x78
81 #define AD74115_CMD_KEY_RESET1 0x15fa
82 #define AD74115_CMD_KEY_RESET2 0xaf51
83
84 #define AD74115_CRC_POLYNOMIAL 0x7
85 DECLARE_CRC8_TABLE(ad74115_crc8_table);
86
87 #define AD74115_ADC_CODE_MAX ((int)GENMASK(15, 0))
88 #define AD74115_ADC_CODE_HALF (AD74115_ADC_CODE_MAX / 2)
89
90 #define AD74115_DAC_VOLTAGE_MAX 12000
91 #define AD74115_DAC_CURRENT_MAX 25
92 #define AD74115_DAC_CODE_MAX ((int)GENMASK(13, 0))
93 #define AD74115_DAC_CODE_HALF (AD74115_DAC_CODE_MAX / 2)
94
95 #define AD74115_COMP_THRESH_MAX 98
96
97 #define AD74115_SENSE_RESISTOR_OHMS 100
98 #define AD74115_REF_RESISTOR_OHMS 2100
99
100 #define AD74115_DIN_SINK_LOW_STEP 120
101 #define AD74115_DIN_SINK_HIGH_STEP 240
102 #define AD74115_DIN_SINK_MAX 31
103
104 #define AD74115_FRAME_SIZE 4
105 #define AD74115_GPIO_NUM 4
106
107 #define AD74115_CONV_TIME_US 1000000
108
109 enum ad74115_dac_ch {
110 AD74115_DAC_CH_MAIN,
111 AD74115_DAC_CH_COMPARATOR,
112 };
113
114 enum ad74115_adc_ch {
115 AD74115_ADC_CH_CONV1,
116 AD74115_ADC_CH_CONV2,
117 AD74115_ADC_CH_NUM
118 };
119
120 enum ad74115_ch_func {
121 AD74115_CH_FUNC_HIGH_IMPEDANCE,
122 AD74115_CH_FUNC_VOLTAGE_OUTPUT,
123 AD74115_CH_FUNC_CURRENT_OUTPUT,
124 AD74115_CH_FUNC_VOLTAGE_INPUT,
125 AD74115_CH_FUNC_CURRENT_INPUT_EXT_POWER,
126 AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER,
127 AD74115_CH_FUNC_2_WIRE_RESISTANCE_INPUT,
128 AD74115_CH_FUNC_3_4_WIRE_RESISTANCE_INPUT,
129 AD74115_CH_FUNC_DIGITAL_INPUT_LOGIC,
130 AD74115_CH_FUNC_DIGITAL_INPUT_LOOP_POWER,
131 AD74115_CH_FUNC_CURRENT_OUTPUT_HART,
132 AD74115_CH_FUNC_CURRENT_INPUT_EXT_POWER_HART,
133 AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART,
134 AD74115_CH_FUNC_MAX = AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART,
135 AD74115_CH_FUNC_NUM
136 };
137
138 enum ad74115_adc_range {
139 AD74115_ADC_RANGE_12V,
140 AD74115_ADC_RANGE_12V_BIPOLAR,
141 AD74115_ADC_RANGE_2_5V_BIPOLAR,
142 AD74115_ADC_RANGE_2_5V_NEG,
143 AD74115_ADC_RANGE_2_5V,
144 AD74115_ADC_RANGE_0_625V,
145 AD74115_ADC_RANGE_104MV_BIPOLAR,
146 AD74115_ADC_RANGE_12V_OTHER,
147 AD74115_ADC_RANGE_MAX = AD74115_ADC_RANGE_12V_OTHER,
148 AD74115_ADC_RANGE_NUM
149 };
150
151 enum ad74115_adc_conv_seq {
152 AD74115_ADC_CONV_SEQ_STANDBY = 0b00,
153 AD74115_ADC_CONV_SEQ_SINGLE = 0b01,
154 AD74115_ADC_CONV_SEQ_CONTINUOUS = 0b10,
155 };
156
157 enum ad74115_din_threshold_mode {
158 AD74115_DIN_THRESHOLD_MODE_AVDD,
159 AD74115_DIN_THRESHOLD_MODE_FIXED,
160 AD74115_DIN_THRESHOLD_MODE_MAX = AD74115_DIN_THRESHOLD_MODE_FIXED,
161 };
162
163 enum ad74115_slew_mode {
164 AD74115_SLEW_MODE_DISABLED,
165 AD74115_SLEW_MODE_LINEAR,
166 AD74115_SLEW_MODE_HART,
167 };
168
169 enum ad74115_slew_step {
170 AD74115_SLEW_STEP_0_8_PERCENT,
171 AD74115_SLEW_STEP_1_5_PERCENT,
172 AD74115_SLEW_STEP_6_1_PERCENT,
173 AD74115_SLEW_STEP_22_2_PERCENT,
174 };
175
176 enum ad74115_slew_rate {
177 AD74115_SLEW_RATE_4KHZ,
178 AD74115_SLEW_RATE_64KHZ,
179 AD74115_SLEW_RATE_150KHZ,
180 AD74115_SLEW_RATE_240KHZ,
181 };
182
183 enum ad74115_gpio_config {
184 AD74115_GPIO_CONFIG_OUTPUT_BUFFERED = 0b010,
185 AD74115_GPIO_CONFIG_INPUT = 0b011,
186 };
187
188 enum ad74115_gpio_mode {
189 AD74115_GPIO_MODE_LOGIC = 1,
190 AD74115_GPIO_MODE_SPECIAL = 2,
191 };
192
193 struct ad74115_channels {
194 const struct iio_chan_spec *channels;
195 unsigned int num_channels;
196 };
197
198 struct ad74115_state {
199 struct spi_device *spi;
200 struct regmap *regmap;
201 struct iio_trigger *trig;
202
203 /*
204 * Synchronize consecutive operations when doing a one-shot
205 * conversion and when updating the ADC samples SPI message.
206 */
207 struct mutex lock;
208 struct gpio_chip gc;
209 struct gpio_chip comp_gc;
210 int irq;
211
212 unsigned int avdd_mv;
213 unsigned long gpio_valid_mask;
214 bool dac_bipolar;
215 bool dac_hart_slew;
216 bool rtd_mode_4_wire;
217 enum ad74115_ch_func ch_func;
218 enum ad74115_din_threshold_mode din_threshold_mode;
219
220 struct completion adc_data_completion;
221 struct spi_message adc_samples_msg;
222 struct spi_transfer adc_samples_xfer[AD74115_ADC_CH_NUM + 1];
223
224 /*
225 * DMA (thus cache coherency maintenance) requires the
226 * transfer buffers to live in their own cache lines.
227 */
228 u8 reg_tx_buf[AD74115_FRAME_SIZE] __aligned(IIO_DMA_MINALIGN);
229 u8 reg_rx_buf[AD74115_FRAME_SIZE];
230 u8 adc_samples_tx_buf[AD74115_FRAME_SIZE * AD74115_ADC_CH_NUM];
231 u8 adc_samples_rx_buf[AD74115_FRAME_SIZE * AD74115_ADC_CH_NUM];
232 };
233
234 struct ad74115_fw_prop {
235 const char *name;
236 bool is_boolean;
237 bool negate;
238 unsigned int max;
239 unsigned int reg;
240 unsigned int mask;
241 const unsigned int *lookup_tbl;
242 unsigned int lookup_tbl_len;
243 };
244
245 #define AD74115_FW_PROP(_name, _max, _reg, _mask) \
246 { \
247 .name = (_name), \
248 .max = (_max), \
249 .reg = (_reg), \
250 .mask = (_mask), \
251 }
252
253 #define AD74115_FW_PROP_TBL(_name, _tbl, _reg, _mask) \
254 { \
255 .name = (_name), \
256 .reg = (_reg), \
257 .mask = (_mask), \
258 .lookup_tbl = (_tbl), \
259 .lookup_tbl_len = ARRAY_SIZE(_tbl), \
260 }
261
262 #define AD74115_FW_PROP_BOOL(_name, _reg, _mask) \
263 { \
264 .name = (_name), \
265 .is_boolean = true, \
266 .reg = (_reg), \
267 .mask = (_mask), \
268 }
269
270 #define AD74115_FW_PROP_BOOL_NEG(_name, _reg, _mask) \
271 { \
272 .name = (_name), \
273 .is_boolean = true, \
274 .negate = true, \
275 .reg = (_reg), \
276 .mask = (_mask), \
277 }
278
279 static const int ad74115_dac_rate_tbl[] = {
280 0,
281 4 * 8,
282 4 * 15,
283 4 * 61,
284 4 * 222,
285 64 * 8,
286 64 * 15,
287 64 * 61,
288 64 * 222,
289 150 * 8,
290 150 * 15,
291 150 * 61,
292 150 * 222,
293 240 * 8,
294 240 * 15,
295 240 * 61,
296 240 * 222,
297 };
298
299 static const unsigned int ad74115_dac_rate_step_tbl[][3] = {
300 { AD74115_SLEW_MODE_DISABLED },
301 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_0_8_PERCENT, AD74115_SLEW_RATE_4KHZ },
302 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_1_5_PERCENT, AD74115_SLEW_RATE_4KHZ },
303 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_6_1_PERCENT, AD74115_SLEW_RATE_4KHZ },
304 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_22_2_PERCENT, AD74115_SLEW_RATE_4KHZ },
305 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_0_8_PERCENT, AD74115_SLEW_RATE_64KHZ },
306 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_1_5_PERCENT, AD74115_SLEW_RATE_64KHZ },
307 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_6_1_PERCENT, AD74115_SLEW_RATE_64KHZ },
308 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_22_2_PERCENT, AD74115_SLEW_RATE_64KHZ },
309 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_0_8_PERCENT, AD74115_SLEW_RATE_150KHZ },
310 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_1_5_PERCENT, AD74115_SLEW_RATE_150KHZ },
311 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_6_1_PERCENT, AD74115_SLEW_RATE_150KHZ },
312 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_22_2_PERCENT, AD74115_SLEW_RATE_150KHZ },
313 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_0_8_PERCENT, AD74115_SLEW_RATE_240KHZ },
314 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_1_5_PERCENT, AD74115_SLEW_RATE_240KHZ },
315 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_6_1_PERCENT, AD74115_SLEW_RATE_240KHZ },
316 { AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_22_2_PERCENT, AD74115_SLEW_RATE_240KHZ },
317 };
318
319 static const unsigned int ad74115_rtd_excitation_current_ua_tbl[] = {
320 250, 500, 750, 1000
321 };
322
323 static const unsigned int ad74115_burnout_current_na_tbl[] = {
324 0, 50, 0, 500, 1000, 0, 10000, 0
325 };
326
327 static const unsigned int ad74115_viout_burnout_current_na_tbl[] = {
328 0, 0, 0, 0, 1000, 0, 10000, 0
329 };
330
331 static const unsigned int ad74115_gpio_mode_tbl[] = {
332 0, 0, 0, 1, 2, 3, 4, 5
333 };
334
335 static const unsigned int ad74115_adc_conv_rate_tbl[] = {
336 10, 20, 1200, 4800, 9600
337 };
338
339 static const unsigned int ad74115_debounce_tbl[] = {
340 0, 13, 18, 24, 32, 42, 56, 75,
341 100, 130, 180, 240, 320, 420, 560, 750,
342 1000, 1300, 1800, 2400, 3200, 4200, 5600, 7500,
343 10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
344 };
345
346 static const unsigned int ad74115_adc_ch_data_regs_tbl[] = {
347 [AD74115_ADC_CH_CONV1] = 0x44,
348 [AD74115_ADC_CH_CONV2] = 0x46,
349 };
350
351 static const unsigned int ad74115_adc_ch_en_bit_tbl[] = {
352 [AD74115_ADC_CH_CONV1] = BIT(0),
353 [AD74115_ADC_CH_CONV2] = BIT(1),
354 };
355
356 static const bool ad74115_adc_bipolar_tbl[AD74115_ADC_RANGE_NUM] = {
357 [AD74115_ADC_RANGE_12V_BIPOLAR] = true,
358 [AD74115_ADC_RANGE_2_5V_BIPOLAR] = true,
359 [AD74115_ADC_RANGE_104MV_BIPOLAR] = true,
360 };
361
362 static const unsigned int ad74115_adc_conv_mul_tbl[AD74115_ADC_RANGE_NUM] = {
363 [AD74115_ADC_RANGE_12V] = 12000,
364 [AD74115_ADC_RANGE_12V_BIPOLAR] = 24000,
365 [AD74115_ADC_RANGE_2_5V_BIPOLAR] = 5000,
366 [AD74115_ADC_RANGE_2_5V_NEG] = 2500,
367 [AD74115_ADC_RANGE_2_5V] = 2500,
368 [AD74115_ADC_RANGE_0_625V] = 625,
369 [AD74115_ADC_RANGE_104MV_BIPOLAR] = 208,
370 [AD74115_ADC_RANGE_12V_OTHER] = 12000,
371 };
372
373 static const unsigned int ad74115_adc_gain_tbl[AD74115_ADC_RANGE_NUM][2] = {
374 [AD74115_ADC_RANGE_12V] = { 5, 24 },
375 [AD74115_ADC_RANGE_12V_BIPOLAR] = { 5, 24 },
376 [AD74115_ADC_RANGE_2_5V_BIPOLAR] = { 1, 1 },
377 [AD74115_ADC_RANGE_2_5V_NEG] = { 1, 1 },
378 [AD74115_ADC_RANGE_2_5V] = { 1, 1 },
379 [AD74115_ADC_RANGE_0_625V] = { 4, 1 },
380 [AD74115_ADC_RANGE_104MV_BIPOLAR] = { 24, 1 },
381 [AD74115_ADC_RANGE_12V_OTHER] = { 5, 24 },
382 };
383
384 static const int ad74115_adc_range_tbl[AD74115_ADC_RANGE_NUM][2] = {
385 [AD74115_ADC_RANGE_12V] = { 0, 12000000 },
386 [AD74115_ADC_RANGE_12V_BIPOLAR] = { -12000000, 12000000 },
387 [AD74115_ADC_RANGE_2_5V_BIPOLAR] = { -2500000, 2500000 },
388 [AD74115_ADC_RANGE_2_5V_NEG] = { -2500000, 0 },
389 [AD74115_ADC_RANGE_2_5V] = { 0, 2500000 },
390 [AD74115_ADC_RANGE_0_625V] = { 0, 625000 },
391 [AD74115_ADC_RANGE_104MV_BIPOLAR] = { -104000, 104000 },
392 [AD74115_ADC_RANGE_12V_OTHER] = { 0, 12000000 },
393 };
394
395 static int _ad74115_find_tbl_index(const unsigned int *tbl, unsigned int tbl_len,
396 unsigned int val, unsigned int *index)
397 {
398 unsigned int i;
399
400 for (i = 0; i < tbl_len; i++)
401 if (val == tbl[i]) {
402 *index = i;
403 return 0;
404 }
405
406 return -EINVAL;
407 }
408
409 #define ad74115_find_tbl_index(tbl, val, index) \
410 _ad74115_find_tbl_index(tbl, ARRAY_SIZE(tbl), val, index)
411
412 static int ad74115_crc(u8 *buf)
413 {
414 return crc8(ad74115_crc8_table, buf, 3, 0);
415 }
416
417 static void ad74115_format_reg_write(u8 reg, u16 val, u8 *buf)
418 {
419 buf[0] = reg;
420 put_unaligned_be16(val, &buf[1]);
421 buf[3] = ad74115_crc(buf);
422 }
423
424 static int ad74115_reg_write(void *context, unsigned int reg, unsigned int val)
425 {
426 struct ad74115_state *st = context;
427
428 ad74115_format_reg_write(reg, val, st->reg_tx_buf);
429
430 return spi_write(st->spi, st->reg_tx_buf, AD74115_FRAME_SIZE);
431 }
432
433 static int ad74115_crc_check(struct ad74115_state *st, u8 *buf)
434 {
435 struct device *dev = &st->spi->dev;
436 u8 expected_crc = ad74115_crc(buf);
437
438 if (buf[3] != expected_crc) {
439 dev_err(dev, "Bad CRC %02x for %02x%02x%02x, expected %02x\n",
440 buf[3], buf[0], buf[1], buf[2], expected_crc);
441 return -EINVAL;
442 }
443
444 return 0;
445 }
446
447 static int ad74115_reg_read(void *context, unsigned int reg, unsigned int *val)
448 {
449 struct ad74115_state *st = context;
450 struct spi_transfer reg_read_xfer[] = {
451 {
452 .tx_buf = st->reg_tx_buf,
453 .len = sizeof(st->reg_tx_buf),
454 .cs_change = 1,
455 },
456 {
457 .rx_buf = st->reg_rx_buf,
458 .len = sizeof(st->reg_rx_buf),
459 },
460 };
461 int ret;
462
463 ad74115_format_reg_write(AD74115_READ_SELECT_REG, reg, st->reg_tx_buf);
464
465 ret = spi_sync_transfer(st->spi, reg_read_xfer, ARRAY_SIZE(reg_read_xfer));
466 if (ret)
467 return ret;
468
469 ret = ad74115_crc_check(st, st->reg_rx_buf);
470 if (ret)
471 return ret;
472
473 *val = get_unaligned_be16(&st->reg_rx_buf[1]);
474
475 return 0;
476 }
477
478 static const struct regmap_config ad74115_regmap_config = {
479 .reg_bits = 8,
480 .val_bits = 16,
481 .reg_read = ad74115_reg_read,
482 .reg_write = ad74115_reg_write,
483 };
484
485 static int ad74115_gpio_config_set(struct ad74115_state *st, unsigned int offset,
486 enum ad74115_gpio_config cfg)
487 {
488 return regmap_update_bits(st->regmap, AD74115_GPIO_CONFIG_X_REG(offset),
489 AD74115_GPIO_CONFIG_SELECT_MASK,
490 FIELD_PREP(AD74115_GPIO_CONFIG_SELECT_MASK, cfg));
491 }
492
493 static int ad74115_gpio_init_valid_mask(struct gpio_chip *gc,
494 unsigned long *valid_mask,
495 unsigned int ngpios)
496 {
497 struct ad74115_state *st = gpiochip_get_data(gc);
498
499 *valid_mask = st->gpio_valid_mask;
500
501 return 0;
502 }
503
504 static int ad74115_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
505 {
506 struct ad74115_state *st = gpiochip_get_data(gc);
507 unsigned int val;
508 int ret;
509
510 ret = regmap_read(st->regmap, AD74115_GPIO_CONFIG_X_REG(offset), &val);
511 if (ret)
512 return ret;
513
514 return FIELD_GET(AD74115_GPIO_CONFIG_SELECT_MASK, val) == AD74115_GPIO_CONFIG_INPUT;
515 }
516
517 static int ad74115_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
518 {
519 struct ad74115_state *st = gpiochip_get_data(gc);
520
521 return ad74115_gpio_config_set(st, offset, AD74115_GPIO_CONFIG_INPUT);
522 }
523
524 static int ad74115_gpio_direction_output(struct gpio_chip *gc, unsigned int offset,
525 int value)
526 {
527 struct ad74115_state *st = gpiochip_get_data(gc);
528
529 return ad74115_gpio_config_set(st, offset, AD74115_GPIO_CONFIG_OUTPUT_BUFFERED);
530 }
531
532 static int ad74115_gpio_get(struct gpio_chip *gc, unsigned int offset)
533 {
534 struct ad74115_state *st = gpiochip_get_data(gc);
535 unsigned int val;
536 int ret;
537
538 ret = regmap_read(st->regmap, AD74115_GPIO_CONFIG_X_REG(offset), &val);
539 if (ret)
540 return ret;
541
542 return FIELD_GET(AD74115_GPIO_CONFIG_GPI_DATA, val);
543 }
544
545 static void ad74115_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
546 {
547 struct ad74115_state *st = gpiochip_get_data(gc);
548 struct device *dev = &st->spi->dev;
549 int ret;
550
551 ret = regmap_update_bits(st->regmap, AD74115_GPIO_CONFIG_X_REG(offset),
552 AD74115_GPIO_CONFIG_GPO_DATA,
553 FIELD_PREP(AD74115_GPIO_CONFIG_GPO_DATA, value));
554 if (ret)
555 dev_err(dev, "Failed to set GPIO %u output value, err: %d\n",
556 offset, ret);
557 }
558
559 static int ad74115_set_comp_debounce(struct ad74115_state *st, unsigned int val)
560 {
561 unsigned int len = ARRAY_SIZE(ad74115_debounce_tbl);
562 unsigned int i;
563
564 for (i = 0; i < len; i++)
565 if (val <= ad74115_debounce_tbl[i])
566 break;
567
568 if (i == len)
569 i = len - 1;
570
571 return regmap_update_bits(st->regmap, AD74115_DIN_CONFIG1_REG,
572 AD74115_DIN_DEBOUNCE_MASK,
573 FIELD_PREP(AD74115_DIN_DEBOUNCE_MASK, val));
574 }
575
576 static int ad74115_comp_gpio_get_direction(struct gpio_chip *chip,
577 unsigned int offset)
578 {
579 return GPIO_LINE_DIRECTION_IN;
580 }
581
582 static int ad74115_comp_gpio_set_config(struct gpio_chip *chip,
583 unsigned int offset,
584 unsigned long config)
585 {
586 struct ad74115_state *st = gpiochip_get_data(chip);
587 u32 param = pinconf_to_config_param(config);
588 u32 arg = pinconf_to_config_argument(config);
589
590 switch (param) {
591 case PIN_CONFIG_INPUT_DEBOUNCE:
592 return ad74115_set_comp_debounce(st, arg);
593 default:
594 return -ENOTSUPP;
595 }
596 }
597
598 static int ad74115_comp_gpio_get(struct gpio_chip *chip, unsigned int offset)
599 {
600 struct ad74115_state *st = gpiochip_get_data(chip);
601 unsigned int val;
602 int ret;
603
604 ret = regmap_read(st->regmap, AD74115_DIN_COMP_OUT_REG, &val);
605 if (ret)
606 return ret;
607
608 return !!val;
609 }
610
611 static irqreturn_t ad74115_trigger_handler(int irq, void *p)
612 {
613 struct iio_poll_func *pf = p;
614 struct iio_dev *indio_dev = pf->indio_dev;
615 struct ad74115_state *st = iio_priv(indio_dev);
616 int ret;
617
618 ret = spi_sync(st->spi, &st->adc_samples_msg);
619 if (ret)
620 goto out;
621
622 iio_push_to_buffers(indio_dev, st->adc_samples_rx_buf);
623
624 out:
625 iio_trigger_notify_done(indio_dev->trig);
626
627 return IRQ_HANDLED;
628 }
629
630 static irqreturn_t ad74115_adc_data_interrupt(int irq, void *data)
631 {
632 struct iio_dev *indio_dev = data;
633 struct ad74115_state *st = iio_priv(indio_dev);
634
635 if (iio_buffer_enabled(indio_dev))
636 iio_trigger_poll(st->trig);
637 else
638 complete(&st->adc_data_completion);
639
640 return IRQ_HANDLED;
641 }
642
643 static int ad74115_set_adc_ch_en(struct ad74115_state *st,
644 enum ad74115_adc_ch channel, bool status)
645 {
646 unsigned int mask = ad74115_adc_ch_en_bit_tbl[channel];
647
648 return regmap_update_bits(st->regmap, AD74115_ADC_CONV_CTRL_REG, mask,
649 status ? mask : 0);
650 }
651
652 static int ad74115_set_adc_conv_seq(struct ad74115_state *st,
653 enum ad74115_adc_conv_seq conv_seq)
654 {
655 return regmap_update_bits(st->regmap, AD74115_ADC_CONV_CTRL_REG,
656 AD74115_ADC_CONV_SEQ_MASK,
657 FIELD_PREP(AD74115_ADC_CONV_SEQ_MASK, conv_seq));
658 }
659
660 static int ad74115_update_scan_mode(struct iio_dev *indio_dev,
661 const unsigned long *active_scan_mask)
662 {
663 struct ad74115_state *st = iio_priv(indio_dev);
664 struct spi_transfer *xfer = st->adc_samples_xfer;
665 u8 *rx_buf = st->adc_samples_rx_buf;
666 u8 *tx_buf = st->adc_samples_tx_buf;
667 unsigned int i;
668 int ret = 0;
669
670 mutex_lock(&st->lock);
671
672 spi_message_init(&st->adc_samples_msg);
673
674 for_each_clear_bit(i, active_scan_mask, AD74115_ADC_CH_NUM) {
675 ret = ad74115_set_adc_ch_en(st, i, false);
676 if (ret)
677 goto out;
678 }
679
680 /*
681 * The read select register is used to select which register's value
682 * will be sent by the slave on the next SPI frame.
683 *
684 * Create an SPI message that, on each step, writes to the read select
685 * register to select the ADC result of the next enabled channel, and
686 * reads the ADC result of the previous enabled channel.
687 *
688 * Example:
689 * W: [WCH1] [WCH2] [WCH2] [WCH3] [ ]
690 * R: [ ] [RCH1] [RCH2] [RCH3] [RCH4]
691 */
692 for_each_set_bit(i, active_scan_mask, AD74115_ADC_CH_NUM) {
693 ret = ad74115_set_adc_ch_en(st, i, true);
694 if (ret)
695 goto out;
696
697 if (xfer == st->adc_samples_xfer)
698 xfer->rx_buf = NULL;
699 else
700 xfer->rx_buf = rx_buf;
701
702 xfer->tx_buf = tx_buf;
703 xfer->len = AD74115_FRAME_SIZE;
704 xfer->cs_change = 1;
705
706 ad74115_format_reg_write(AD74115_READ_SELECT_REG,
707 ad74115_adc_ch_data_regs_tbl[i], tx_buf);
708
709 spi_message_add_tail(xfer, &st->adc_samples_msg);
710
711 tx_buf += AD74115_FRAME_SIZE;
712 if (xfer != st->adc_samples_xfer)
713 rx_buf += AD74115_FRAME_SIZE;
714 xfer++;
715 }
716
717 xfer->rx_buf = rx_buf;
718 xfer->tx_buf = NULL;
719 xfer->len = AD74115_FRAME_SIZE;
720 xfer->cs_change = 0;
721
722 spi_message_add_tail(xfer, &st->adc_samples_msg);
723
724 out:
725 mutex_unlock(&st->lock);
726
727 return ret;
728 }
729
730 static int ad74115_buffer_postenable(struct iio_dev *indio_dev)
731 {
732 struct ad74115_state *st = iio_priv(indio_dev);
733
734 return ad74115_set_adc_conv_seq(st, AD74115_ADC_CONV_SEQ_CONTINUOUS);
735 }
736
737 static int ad74115_buffer_predisable(struct iio_dev *indio_dev)
738 {
739 struct ad74115_state *st = iio_priv(indio_dev);
740 unsigned int i;
741 int ret;
742
743 mutex_lock(&st->lock);
744
745 ret = ad74115_set_adc_conv_seq(st, AD74115_ADC_CONV_SEQ_STANDBY);
746 if (ret)
747 goto out;
748
749 /*
750 * update_scan_mode() is not called in the disable path, disable all
751 * channels here.
752 */
753 for (i = 0; i < AD74115_ADC_CH_NUM; i++) {
754 ret = ad74115_set_adc_ch_en(st, i, false);
755 if (ret)
756 goto out;
757 }
758
759 out:
760 mutex_unlock(&st->lock);
761
762 return ret;
763 }
764
765 static const struct iio_buffer_setup_ops ad74115_buffer_ops = {
766 .postenable = &ad74115_buffer_postenable,
767 .predisable = &ad74115_buffer_predisable,
768 };
769
770 static const struct iio_trigger_ops ad74115_trigger_ops = {
771 .validate_device = iio_trigger_validate_own_device,
772 };
773
774 static int ad74115_get_adc_rate(struct ad74115_state *st,
775 enum ad74115_adc_ch channel, int *val)
776 {
777 unsigned int i;
778 int ret;
779
780 ret = regmap_read(st->regmap, AD74115_ADC_CONFIG_REG, &i);
781 if (ret)
782 return ret;
783
784 if (channel == AD74115_ADC_CH_CONV1)
785 i = FIELD_GET(AD74115_ADC_CONFIG_CONV1_RATE_MASK, i);
786 else
787 i = FIELD_GET(AD74115_ADC_CONFIG_CONV2_RATE_MASK, i);
788
789 *val = ad74115_adc_conv_rate_tbl[i];
790
791 return IIO_VAL_INT;
792 }
793
794 static int _ad74115_get_adc_code(struct ad74115_state *st,
795 enum ad74115_adc_ch channel, int *val)
796 {
797 unsigned int uval;
798 int ret;
799
800 reinit_completion(&st->adc_data_completion);
801
802 ret = ad74115_set_adc_ch_en(st, channel, true);
803 if (ret)
804 return ret;
805
806 ret = ad74115_set_adc_conv_seq(st, AD74115_ADC_CONV_SEQ_SINGLE);
807 if (ret)
808 return ret;
809
810 if (st->irq) {
811 ret = wait_for_completion_timeout(&st->adc_data_completion,
812 msecs_to_jiffies(1000));
813 if (!ret)
814 return -ETIMEDOUT;
815 } else {
816 unsigned int regval, wait_time;
817 int rate;
818
819 ret = ad74115_get_adc_rate(st, channel, &rate);
820 if (ret < 0)
821 return ret;
822
823 wait_time = DIV_ROUND_CLOSEST(AD74115_CONV_TIME_US, rate);
824
825 ret = regmap_read_poll_timeout(st->regmap, AD74115_LIVE_STATUS_REG,
826 regval, regval & AD74115_ADC_DATA_RDY_MASK,
827 wait_time, 5 * wait_time);
828 if (ret)
829 return ret;
830
831 /*
832 * The ADC_DATA_RDY bit is W1C.
833 * See datasheet page 98, Table 62. Bit Descriptions for
834 * LIVE_STATUS.
835 * Although the datasheet mentions that the bit will auto-clear
836 * when writing to the ADC_CONV_CTRL register, this does not
837 * seem to happen.
838 */
839 ret = regmap_write_bits(st->regmap, AD74115_LIVE_STATUS_REG,
840 AD74115_ADC_DATA_RDY_MASK,
841 FIELD_PREP(AD74115_ADC_DATA_RDY_MASK, 1));
842 if (ret)
843 return ret;
844 }
845
846 ret = regmap_read(st->regmap, ad74115_adc_ch_data_regs_tbl[channel], &uval);
847 if (ret)
848 return ret;
849
850 ret = ad74115_set_adc_conv_seq(st, AD74115_ADC_CONV_SEQ_STANDBY);
851 if (ret)
852 return ret;
853
854 ret = ad74115_set_adc_ch_en(st, channel, false);
855 if (ret)
856 return ret;
857
858 *val = uval;
859
860 return IIO_VAL_INT;
861 }
862
863 static int ad74115_get_adc_code(struct iio_dev *indio_dev,
864 enum ad74115_adc_ch channel, int *val)
865 {
866 struct ad74115_state *st = iio_priv(indio_dev);
867 int ret;
868
869 ret = iio_device_claim_direct_mode(indio_dev);
870 if (ret)
871 return ret;
872
873 mutex_lock(&st->lock);
874 ret = _ad74115_get_adc_code(st, channel, val);
875 mutex_unlock(&st->lock);
876
877 iio_device_release_direct_mode(indio_dev);
878
879 return ret;
880 }
881
882 static int ad74115_adc_code_to_resistance(int code, int *val, int *val2)
883 {
884 if (code == AD74115_ADC_CODE_MAX)
885 code--;
886
887 *val = code * AD74115_REF_RESISTOR_OHMS;
888 *val2 = AD74115_ADC_CODE_MAX - code;
889
890 return IIO_VAL_FRACTIONAL;
891 }
892
893 static int ad74115_set_dac_code(struct ad74115_state *st,
894 enum ad74115_dac_ch channel, int val)
895 {
896 if (val < 0)
897 return -EINVAL;
898
899 if (channel == AD74115_DAC_CH_COMPARATOR) {
900 if (val > AD74115_COMP_THRESH_MAX)
901 return -EINVAL;
902
903 return regmap_update_bits(st->regmap, AD74115_DIN_CONFIG2_REG,
904 AD74115_COMP_THRESH_MASK,
905 FIELD_PREP(AD74115_COMP_THRESH_MASK, val));
906 }
907
908 if (val > AD74115_DAC_CODE_MAX)
909 return -EINVAL;
910
911 return regmap_write(st->regmap, AD74115_DAC_CODE_REG, val);
912 }
913
914 static int ad74115_get_dac_code(struct ad74115_state *st,
915 enum ad74115_dac_ch channel, int *val)
916 {
917 unsigned int uval;
918 int ret;
919
920 if (channel == AD74115_DAC_CH_COMPARATOR)
921 return -EINVAL;
922
923 ret = regmap_read(st->regmap, AD74115_DAC_ACTIVE_REG, &uval);
924 if (ret)
925 return ret;
926
927 *val = uval;
928
929 return IIO_VAL_INT;
930 }
931
932 static int ad74115_set_adc_rate(struct ad74115_state *st,
933 enum ad74115_adc_ch channel, int val)
934 {
935 unsigned int i;
936 int ret;
937
938 ret = ad74115_find_tbl_index(ad74115_adc_conv_rate_tbl, val, &i);
939 if (ret)
940 return ret;
941
942 if (channel == AD74115_ADC_CH_CONV1)
943 return regmap_update_bits(st->regmap, AD74115_ADC_CONFIG_REG,
944 AD74115_ADC_CONFIG_CONV1_RATE_MASK,
945 FIELD_PREP(AD74115_ADC_CONFIG_CONV1_RATE_MASK, i));
946
947 return regmap_update_bits(st->regmap, AD74115_ADC_CONFIG_REG,
948 AD74115_ADC_CONFIG_CONV2_RATE_MASK,
949 FIELD_PREP(AD74115_ADC_CONFIG_CONV2_RATE_MASK, i));
950 }
951
952 static int ad74115_get_dac_rate(struct ad74115_state *st, int *val)
953 {
954 unsigned int i, en_val, step_val, rate_val, tmp;
955 int ret;
956
957 ret = regmap_read(st->regmap, AD74115_OUTPUT_CONFIG_REG, &tmp);
958 if (ret)
959 return ret;
960
961 en_val = FIELD_GET(AD74115_OUTPUT_SLEW_EN_MASK, tmp);
962 step_val = FIELD_GET(AD74115_OUTPUT_SLEW_LIN_STEP_MASK, tmp);
963 rate_val = FIELD_GET(AD74115_OUTPUT_SLEW_LIN_RATE_MASK, tmp);
964
965 for (i = 0; i < ARRAY_SIZE(ad74115_dac_rate_step_tbl); i++)
966 if (en_val == ad74115_dac_rate_step_tbl[i][0] &&
967 step_val == ad74115_dac_rate_step_tbl[i][1] &&
968 rate_val == ad74115_dac_rate_step_tbl[i][2])
969 break;
970
971 if (i == ARRAY_SIZE(ad74115_dac_rate_step_tbl))
972 return -EINVAL;
973
974 *val = ad74115_dac_rate_tbl[i];
975
976 return IIO_VAL_INT;
977 }
978
979 static int ad74115_set_dac_rate(struct ad74115_state *st, int val)
980 {
981 unsigned int i, en_val, step_val, rate_val, mask, tmp;
982 int ret;
983
984 ret = ad74115_find_tbl_index(ad74115_dac_rate_tbl, val, &i);
985 if (ret)
986 return ret;
987
988 en_val = ad74115_dac_rate_step_tbl[i][0];
989 step_val = ad74115_dac_rate_step_tbl[i][1];
990 rate_val = ad74115_dac_rate_step_tbl[i][2];
991
992 mask = AD74115_OUTPUT_SLEW_EN_MASK;
993 mask |= AD74115_OUTPUT_SLEW_LIN_STEP_MASK;
994 mask |= AD74115_OUTPUT_SLEW_LIN_RATE_MASK;
995
996 tmp = FIELD_PREP(AD74115_OUTPUT_SLEW_EN_MASK, en_val);
997 tmp |= FIELD_PREP(AD74115_OUTPUT_SLEW_LIN_STEP_MASK, step_val);
998 tmp |= FIELD_PREP(AD74115_OUTPUT_SLEW_LIN_RATE_MASK, rate_val);
999
1000 return regmap_update_bits(st->regmap, AD74115_OUTPUT_CONFIG_REG, mask, tmp);
1001 }
1002
1003 static int ad74115_get_dac_scale(struct ad74115_state *st,
1004 struct iio_chan_spec const *chan,
1005 int *val, int *val2)
1006 {
1007 if (chan->channel == AD74115_DAC_CH_MAIN) {
1008 if (chan->type == IIO_VOLTAGE) {
1009 *val = AD74115_DAC_VOLTAGE_MAX;
1010
1011 if (st->dac_bipolar)
1012 *val *= 2;
1013
1014 } else {
1015 *val = AD74115_DAC_CURRENT_MAX;
1016 }
1017
1018 *val2 = AD74115_DAC_CODE_MAX;
1019 } else {
1020 if (st->din_threshold_mode == AD74115_DIN_THRESHOLD_MODE_AVDD) {
1021 *val = 196 * st->avdd_mv;
1022 *val2 = 10 * AD74115_COMP_THRESH_MAX;
1023 } else {
1024 *val = 49000;
1025 *val2 = AD74115_COMP_THRESH_MAX;
1026 }
1027 }
1028
1029 return IIO_VAL_FRACTIONAL;
1030 }
1031
1032 static int ad74115_get_dac_offset(struct ad74115_state *st,
1033 struct iio_chan_spec const *chan, int *val)
1034 {
1035 if (chan->channel == AD74115_DAC_CH_MAIN) {
1036 if (chan->type == IIO_VOLTAGE && st->dac_bipolar)
1037 *val = -AD74115_DAC_CODE_HALF;
1038 else
1039 *val = 0;
1040 } else {
1041 if (st->din_threshold_mode == AD74115_DIN_THRESHOLD_MODE_AVDD)
1042 *val = -48;
1043 else
1044 *val = -38;
1045 }
1046
1047 return IIO_VAL_INT;
1048 }
1049
1050 static int ad74115_get_adc_range(struct ad74115_state *st,
1051 enum ad74115_adc_ch channel, unsigned int *val)
1052 {
1053 int ret;
1054
1055 ret = regmap_read(st->regmap, AD74115_ADC_CONFIG_REG, val);
1056 if (ret)
1057 return ret;
1058
1059 if (channel == AD74115_ADC_CH_CONV1)
1060 *val = FIELD_GET(AD74115_ADC_CONFIG_CONV1_RANGE_MASK, *val);
1061 else
1062 *val = FIELD_GET(AD74115_ADC_CONFIG_CONV2_RANGE_MASK, *val);
1063
1064 return 0;
1065 }
1066
1067 static int ad74115_get_adc_resistance_scale(struct ad74115_state *st,
1068 unsigned int range,
1069 int *val, int *val2)
1070 {
1071 *val = ad74115_adc_gain_tbl[range][1] * AD74115_REF_RESISTOR_OHMS;
1072 *val2 = ad74115_adc_gain_tbl[range][0];
1073
1074 if (ad74115_adc_bipolar_tbl[range])
1075 *val2 *= AD74115_ADC_CODE_HALF;
1076 else
1077 *val2 *= AD74115_ADC_CODE_MAX;
1078
1079 return IIO_VAL_FRACTIONAL;
1080 }
1081
1082 static int ad74115_get_adc_scale(struct ad74115_state *st,
1083 struct iio_chan_spec const *chan,
1084 int *val, int *val2)
1085 {
1086 unsigned int range;
1087 int ret;
1088
1089 ret = ad74115_get_adc_range(st, chan->channel, &range);
1090 if (ret)
1091 return ret;
1092
1093 if (chan->type == IIO_RESISTANCE)
1094 return ad74115_get_adc_resistance_scale(st, range, val, val2);
1095
1096 *val = ad74115_adc_conv_mul_tbl[range];
1097 *val2 = AD74115_ADC_CODE_MAX;
1098
1099 if (chan->type == IIO_CURRENT)
1100 *val2 *= AD74115_SENSE_RESISTOR_OHMS;
1101
1102 return IIO_VAL_FRACTIONAL;
1103 }
1104
1105 static int ad74115_get_adc_resistance_offset(struct ad74115_state *st,
1106 unsigned int range,
1107 int *val, int *val2)
1108 {
1109 unsigned int d = 10 * AD74115_REF_RESISTOR_OHMS
1110 * ad74115_adc_gain_tbl[range][1];
1111
1112 *val = 5;
1113
1114 if (ad74115_adc_bipolar_tbl[range])
1115 *val -= AD74115_ADC_CODE_HALF;
1116
1117 *val *= d;
1118
1119 if (!st->rtd_mode_4_wire) {
1120 /* Add 0.2 Ohm to the final result for 3-wire RTD. */
1121 unsigned int v = 2 * ad74115_adc_gain_tbl[range][0];
1122
1123 if (ad74115_adc_bipolar_tbl[range])
1124 v *= AD74115_ADC_CODE_HALF;
1125 else
1126 v *= AD74115_ADC_CODE_MAX;
1127
1128 *val += v;
1129 }
1130
1131 *val2 = d;
1132
1133 return IIO_VAL_FRACTIONAL;
1134 }
1135
1136 static int ad74115_get_adc_offset(struct ad74115_state *st,
1137 struct iio_chan_spec const *chan,
1138 int *val, int *val2)
1139 {
1140 unsigned int range;
1141 int ret;
1142
1143 ret = ad74115_get_adc_range(st, chan->channel, &range);
1144 if (ret)
1145 return ret;
1146
1147 if (chan->type == IIO_RESISTANCE)
1148 return ad74115_get_adc_resistance_offset(st, range, val, val2);
1149
1150 if (ad74115_adc_bipolar_tbl[range])
1151 *val = -AD74115_ADC_CODE_HALF;
1152 else if (range == AD74115_ADC_RANGE_2_5V_NEG)
1153 *val = -AD74115_ADC_CODE_MAX;
1154 else
1155 *val = 0;
1156
1157 return IIO_VAL_INT;
1158 }
1159
1160 static int ad74115_read_raw(struct iio_dev *indio_dev,
1161 struct iio_chan_spec const *chan,
1162 int *val, int *val2, long info)
1163 {
1164 struct ad74115_state *st = iio_priv(indio_dev);
1165 int ret;
1166
1167 switch (info) {
1168 case IIO_CHAN_INFO_RAW:
1169 if (chan->output)
1170 return ad74115_get_dac_code(st, chan->channel, val);
1171
1172 return ad74115_get_adc_code(indio_dev, chan->channel, val);
1173 case IIO_CHAN_INFO_PROCESSED:
1174 ret = ad74115_get_adc_code(indio_dev, chan->channel, val);
1175 if (ret)
1176 return ret;
1177
1178 return ad74115_adc_code_to_resistance(*val, val, val2);
1179 case IIO_CHAN_INFO_SCALE:
1180 if (chan->output)
1181 return ad74115_get_dac_scale(st, chan, val, val2);
1182
1183 return ad74115_get_adc_scale(st, chan, val, val2);
1184 case IIO_CHAN_INFO_OFFSET:
1185 if (chan->output)
1186 return ad74115_get_dac_offset(st, chan, val);
1187
1188 return ad74115_get_adc_offset(st, chan, val, val2);
1189 case IIO_CHAN_INFO_SAMP_FREQ:
1190 if (chan->output)
1191 return ad74115_get_dac_rate(st, val);
1192
1193 return ad74115_get_adc_rate(st, chan->channel, val);
1194 default:
1195 return -EINVAL;
1196 }
1197 }
1198
1199 static int ad74115_write_raw(struct iio_dev *indio_dev,
1200 struct iio_chan_spec const *chan, int val, int val2,
1201 long info)
1202 {
1203 struct ad74115_state *st = iio_priv(indio_dev);
1204
1205 switch (info) {
1206 case IIO_CHAN_INFO_RAW:
1207 if (!chan->output)
1208 return -EINVAL;
1209
1210 return ad74115_set_dac_code(st, chan->channel, val);
1211 case IIO_CHAN_INFO_SAMP_FREQ:
1212 if (chan->output)
1213 return ad74115_set_dac_rate(st, val);
1214
1215 return ad74115_set_adc_rate(st, chan->channel, val);
1216 default:
1217 return -EINVAL;
1218 }
1219 }
1220
1221 static int ad74115_read_avail(struct iio_dev *indio_dev,
1222 struct iio_chan_spec const *chan,
1223 const int **vals, int *type, int *length, long info)
1224 {
1225 switch (info) {
1226 case IIO_CHAN_INFO_SAMP_FREQ:
1227 if (chan->output) {
1228 *vals = ad74115_dac_rate_tbl;
1229 *length = ARRAY_SIZE(ad74115_dac_rate_tbl);
1230 } else {
1231 *vals = ad74115_adc_conv_rate_tbl;
1232 *length = ARRAY_SIZE(ad74115_adc_conv_rate_tbl);
1233 }
1234
1235 *type = IIO_VAL_INT;
1236
1237 return IIO_AVAIL_LIST;
1238 default:
1239 return -EINVAL;
1240 }
1241 }
1242
1243 static int ad74115_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1244 unsigned int writeval, unsigned int *readval)
1245 {
1246 struct ad74115_state *st = iio_priv(indio_dev);
1247
1248 if (readval)
1249 return regmap_read(st->regmap, reg, readval);
1250
1251 return regmap_write(st->regmap, reg, writeval);
1252 }
1253
1254 static const struct iio_info ad74115_info = {
1255 .read_raw = ad74115_read_raw,
1256 .write_raw = ad74115_write_raw,
1257 .read_avail = ad74115_read_avail,
1258 .update_scan_mode = ad74115_update_scan_mode,
1259 .debugfs_reg_access = ad74115_reg_access,
1260 };
1261
1262 #define AD74115_DAC_CHANNEL(_type, index) \
1263 { \
1264 .type = (_type), \
1265 .channel = (index), \
1266 .indexed = 1, \
1267 .output = 1, \
1268 .scan_index = -1, \
1269 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1270 | BIT(IIO_CHAN_INFO_SCALE) \
1271 | BIT(IIO_CHAN_INFO_OFFSET), \
1272 }
1273
1274 #define _AD74115_ADC_CHANNEL(_type, index, extra_mask_separate) \
1275 { \
1276 .type = (_type), \
1277 .channel = (index), \
1278 .indexed = 1, \
1279 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
1280 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \
1281 | (extra_mask_separate), \
1282 .info_mask_separate_available = \
1283 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1284 .scan_index = index, \
1285 .scan_type = { \
1286 .sign = 'u', \
1287 .realbits = 16, \
1288 .storagebits = 32, \
1289 .shift = 8, \
1290 .endianness = IIO_BE, \
1291 }, \
1292 }
1293
1294 #define AD74115_ADC_CHANNEL(_type, index) \
1295 _AD74115_ADC_CHANNEL(_type, index, BIT(IIO_CHAN_INFO_SCALE) \
1296 | BIT(IIO_CHAN_INFO_OFFSET))
1297
1298 static const struct iio_chan_spec ad74115_voltage_input_channels[] = {
1299 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV1),
1300 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1301 };
1302
1303 static const struct iio_chan_spec ad74115_voltage_output_channels[] = {
1304 AD74115_DAC_CHANNEL(IIO_VOLTAGE, AD74115_DAC_CH_MAIN),
1305 AD74115_ADC_CHANNEL(IIO_CURRENT, AD74115_ADC_CH_CONV1),
1306 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1307 };
1308
1309 static const struct iio_chan_spec ad74115_current_input_channels[] = {
1310 AD74115_ADC_CHANNEL(IIO_CURRENT, AD74115_ADC_CH_CONV1),
1311 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1312 };
1313
1314 static const struct iio_chan_spec ad74115_current_output_channels[] = {
1315 AD74115_DAC_CHANNEL(IIO_CURRENT, AD74115_DAC_CH_MAIN),
1316 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV1),
1317 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1318 };
1319
1320 static const struct iio_chan_spec ad74115_2_wire_resistance_input_channels[] = {
1321 _AD74115_ADC_CHANNEL(IIO_RESISTANCE, AD74115_ADC_CH_CONV1,
1322 BIT(IIO_CHAN_INFO_PROCESSED)),
1323 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1324 };
1325
1326 static const struct iio_chan_spec ad74115_3_4_wire_resistance_input_channels[] = {
1327 AD74115_ADC_CHANNEL(IIO_RESISTANCE, AD74115_ADC_CH_CONV1),
1328 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1329 };
1330
1331 static const struct iio_chan_spec ad74115_digital_input_logic_channels[] = {
1332 AD74115_DAC_CHANNEL(IIO_VOLTAGE, AD74115_DAC_CH_COMPARATOR),
1333 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV1),
1334 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1335 };
1336
1337 static const struct iio_chan_spec ad74115_digital_input_loop_channels[] = {
1338 AD74115_DAC_CHANNEL(IIO_CURRENT, AD74115_DAC_CH_MAIN),
1339 AD74115_DAC_CHANNEL(IIO_VOLTAGE, AD74115_DAC_CH_COMPARATOR),
1340 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV1),
1341 AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1342 };
1343
1344 #define _AD74115_CHANNELS(_channels) \
1345 { \
1346 .channels = _channels, \
1347 .num_channels = ARRAY_SIZE(_channels), \
1348 }
1349
1350 #define AD74115_CHANNELS(name) \
1351 _AD74115_CHANNELS(ad74115_ ## name ## _channels)
1352
1353 static const struct ad74115_channels ad74115_channels_map[AD74115_CH_FUNC_NUM] = {
1354 [AD74115_CH_FUNC_HIGH_IMPEDANCE] = AD74115_CHANNELS(voltage_input),
1355 [AD74115_CH_FUNC_VOLTAGE_INPUT] = AD74115_CHANNELS(voltage_input),
1356
1357 [AD74115_CH_FUNC_VOLTAGE_OUTPUT] = AD74115_CHANNELS(voltage_output),
1358
1359 [AD74115_CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74115_CHANNELS(current_input),
1360 [AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74115_CHANNELS(current_input),
1361 [AD74115_CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74115_CHANNELS(current_input),
1362 [AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74115_CHANNELS(current_input),
1363
1364 [AD74115_CH_FUNC_CURRENT_OUTPUT] = AD74115_CHANNELS(current_output),
1365 [AD74115_CH_FUNC_CURRENT_OUTPUT_HART] = AD74115_CHANNELS(current_output),
1366
1367 [AD74115_CH_FUNC_2_WIRE_RESISTANCE_INPUT] = AD74115_CHANNELS(2_wire_resistance_input),
1368 [AD74115_CH_FUNC_3_4_WIRE_RESISTANCE_INPUT] = AD74115_CHANNELS(3_4_wire_resistance_input),
1369
1370 [AD74115_CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74115_CHANNELS(digital_input_logic),
1371
1372 [AD74115_CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74115_CHANNELS(digital_input_loop),
1373 };
1374
1375 #define AD74115_GPIO_MODE_FW_PROP(i) \
1376 { \
1377 .name = "adi,gpio" __stringify(i) "-mode", \
1378 .reg = AD74115_GPIO_CONFIG_X_REG(i), \
1379 .mask = AD74115_GPIO_CONFIG_SELECT_MASK, \
1380 .lookup_tbl = ad74115_gpio_mode_tbl, \
1381 .lookup_tbl_len = ARRAY_SIZE(ad74115_gpio_mode_tbl), \
1382 }
1383
1384 static const struct ad74115_fw_prop ad74115_gpio_mode_fw_props[] = {
1385 AD74115_GPIO_MODE_FW_PROP(0),
1386 AD74115_GPIO_MODE_FW_PROP(1),
1387 AD74115_GPIO_MODE_FW_PROP(2),
1388 AD74115_GPIO_MODE_FW_PROP(3),
1389 };
1390
1391 static const struct ad74115_fw_prop ad74115_din_threshold_mode_fw_prop =
1392 AD74115_FW_PROP_BOOL("adi,digital-input-threshold-mode-fixed",
1393 AD74115_DIN_CONFIG2_REG, BIT(7));
1394
1395 static const struct ad74115_fw_prop ad74115_dac_bipolar_fw_prop =
1396 AD74115_FW_PROP_BOOL("adi,dac-bipolar", AD74115_OUTPUT_CONFIG_REG, BIT(7));
1397
1398 static const struct ad74115_fw_prop ad74115_ch_func_fw_prop =
1399 AD74115_FW_PROP("adi,ch-func", AD74115_CH_FUNC_MAX,
1400 AD74115_CH_FUNC_SETUP_REG, GENMASK(3, 0));
1401
1402 static const struct ad74115_fw_prop ad74115_rtd_mode_fw_prop =
1403 AD74115_FW_PROP_BOOL("adi,4-wire-rtd", AD74115_RTD3W4W_CONFIG_REG, BIT(3));
1404
1405 static const struct ad74115_fw_prop ad74115_din_range_fw_prop =
1406 AD74115_FW_PROP_BOOL("adi,digital-input-sink-range-high",
1407 AD74115_DIN_CONFIG1_REG, BIT(12));
1408
1409 static const struct ad74115_fw_prop ad74115_ext2_burnout_current_fw_prop =
1410 AD74115_FW_PROP_TBL("adi,ext2-burnout-current-nanoamp",
1411 ad74115_burnout_current_na_tbl,
1412 AD74115_BURNOUT_CONFIG_REG, GENMASK(14, 12));
1413
1414 static const struct ad74115_fw_prop ad74115_ext1_burnout_current_fw_prop =
1415 AD74115_FW_PROP_TBL("adi,ext1-burnout-current-nanoamp",
1416 ad74115_burnout_current_na_tbl,
1417 AD74115_BURNOUT_CONFIG_REG, GENMASK(9, 7));
1418
1419 static const struct ad74115_fw_prop ad74115_viout_burnout_current_fw_prop =
1420 AD74115_FW_PROP_TBL("adi,viout-burnout-current-nanoamp",
1421 ad74115_viout_burnout_current_na_tbl,
1422 AD74115_BURNOUT_CONFIG_REG, GENMASK(4, 2));
1423
1424 static const struct ad74115_fw_prop ad74115_fw_props[] = {
1425 AD74115_FW_PROP("adi,conv2-mux", 3,
1426 AD74115_ADC_CONFIG_REG, GENMASK(3, 2)),
1427
1428 AD74115_FW_PROP_BOOL_NEG("adi,sense-agnd-buffer-low-power",
1429 AD74115_PWR_OPTIM_CONFIG_REG, BIT(4)),
1430 AD74115_FW_PROP_BOOL_NEG("adi,lf-buffer-low-power",
1431 AD74115_PWR_OPTIM_CONFIG_REG, BIT(3)),
1432 AD74115_FW_PROP_BOOL_NEG("adi,hf-buffer-low-power",
1433 AD74115_PWR_OPTIM_CONFIG_REG, BIT(2)),
1434 AD74115_FW_PROP_BOOL_NEG("adi,ext2-buffer-low-power",
1435 AD74115_PWR_OPTIM_CONFIG_REG, BIT(1)),
1436 AD74115_FW_PROP_BOOL_NEG("adi,ext1-buffer-low-power",
1437 AD74115_PWR_OPTIM_CONFIG_REG, BIT(0)),
1438
1439 AD74115_FW_PROP_BOOL("adi,comparator-invert",
1440 AD74115_DIN_CONFIG1_REG, BIT(14)),
1441 AD74115_FW_PROP_BOOL("adi,digital-input-debounce-mode-counter-reset",
1442 AD74115_DIN_CONFIG1_REG, BIT(6)),
1443
1444 AD74115_FW_PROP_BOOL("adi,digital-input-unbuffered",
1445 AD74115_DIN_CONFIG2_REG, BIT(10)),
1446 AD74115_FW_PROP_BOOL("adi,digital-input-short-circuit-detection",
1447 AD74115_DIN_CONFIG2_REG, BIT(9)),
1448 AD74115_FW_PROP_BOOL("adi,digital-input-open-circuit-detection",
1449 AD74115_DIN_CONFIG2_REG, BIT(8)),
1450
1451 AD74115_FW_PROP_BOOL("adi,dac-current-limit-low",
1452 AD74115_OUTPUT_CONFIG_REG, BIT(0)),
1453
1454 AD74115_FW_PROP_BOOL("adi,3-wire-rtd-excitation-swap",
1455 AD74115_RTD3W4W_CONFIG_REG, BIT(2)),
1456 AD74115_FW_PROP_TBL("adi,rtd-excitation-current-microamp",
1457 ad74115_rtd_excitation_current_ua_tbl,
1458 AD74115_RTD3W4W_CONFIG_REG, GENMASK(1, 0)),
1459
1460 AD74115_FW_PROP_BOOL("adi,ext2-burnout-current-polarity-sourcing",
1461 AD74115_BURNOUT_CONFIG_REG, BIT(11)),
1462 AD74115_FW_PROP_BOOL("adi,ext1-burnout-current-polarity-sourcing",
1463 AD74115_BURNOUT_CONFIG_REG, BIT(6)),
1464 AD74115_FW_PROP_BOOL("adi,viout-burnout-current-polarity-sourcing",
1465 AD74115_BURNOUT_CONFIG_REG, BIT(1)),
1466
1467 AD74115_FW_PROP_BOOL("adi,charge-pump",
1468 AD74115_CHARGE_PUMP_REG, BIT(0)),
1469 };
1470
1471 static int ad74115_apply_fw_prop(struct ad74115_state *st,
1472 const struct ad74115_fw_prop *prop, u32 *retval)
1473 {
1474 struct device *dev = &st->spi->dev;
1475 u32 val = 0;
1476 int ret;
1477
1478 if (prop->is_boolean) {
1479 val = device_property_read_bool(dev, prop->name);
1480 } else {
1481 ret = device_property_read_u32(dev, prop->name, &val);
1482 if (ret && prop->lookup_tbl)
1483 val = prop->lookup_tbl[0];
1484 }
1485
1486 *retval = val;
1487
1488 if (prop->negate)
1489 val = !val;
1490
1491 if (prop->lookup_tbl)
1492 ret = _ad74115_find_tbl_index(prop->lookup_tbl,
1493 prop->lookup_tbl_len, val, &val);
1494 else if (prop->max && val > prop->max)
1495 ret = -EINVAL;
1496 else
1497 ret = 0;
1498
1499 if (ret)
1500 return dev_err_probe(dev, -EINVAL,
1501 "Invalid value %u for prop %s\n",
1502 val, prop->name);
1503
1504 WARN(!prop->mask, "Prop %s mask is empty\n", prop->name);
1505
1506 val = (val << __ffs(prop->mask)) & prop->mask;
1507
1508 return regmap_update_bits(st->regmap, prop->reg, prop->mask, val);
1509 }
1510
1511 static int ad74115_setup_adc_conv2_range(struct ad74115_state *st)
1512 {
1513 unsigned int tbl_len = ARRAY_SIZE(ad74115_adc_range_tbl);
1514 const char *prop_name = "adi,conv2-range-microvolt";
1515 s32 vals[2] = {
1516 ad74115_adc_range_tbl[0][0],
1517 ad74115_adc_range_tbl[0][1],
1518 };
1519 struct device *dev = &st->spi->dev;
1520 unsigned int i;
1521
1522 device_property_read_u32_array(dev, prop_name, vals, 2);
1523
1524 for (i = 0; i < tbl_len; i++)
1525 if (vals[0] == ad74115_adc_range_tbl[i][0] &&
1526 vals[1] == ad74115_adc_range_tbl[i][1])
1527 break;
1528
1529 if (i == tbl_len)
1530 return dev_err_probe(dev, -EINVAL,
1531 "Invalid value %d, %d for prop %s\n",
1532 vals[0], vals[1], prop_name);
1533
1534 return regmap_update_bits(st->regmap, AD74115_ADC_CONFIG_REG,
1535 AD74115_ADC_CONFIG_CONV2_RANGE_MASK,
1536 FIELD_PREP(AD74115_ADC_CONFIG_CONV2_RANGE_MASK, i));
1537 }
1538
1539 static int ad74115_setup_iio_channels(struct iio_dev *indio_dev)
1540 {
1541 struct ad74115_state *st = iio_priv(indio_dev);
1542 struct device *dev = &st->spi->dev;
1543 struct iio_chan_spec *channels;
1544
1545 channels = devm_kcalloc(dev, sizeof(*channels),
1546 indio_dev->num_channels, GFP_KERNEL);
1547 if (!channels)
1548 return -ENOMEM;
1549
1550 indio_dev->channels = channels;
1551
1552 memcpy(channels, ad74115_channels_map[st->ch_func].channels,
1553 sizeof(*channels) * ad74115_channels_map[st->ch_func].num_channels);
1554
1555 if (channels[0].output && channels[0].channel == AD74115_DAC_CH_MAIN &&
1556 channels[0].type == IIO_VOLTAGE && !st->dac_hart_slew) {
1557 channels[0].info_mask_separate |= BIT(IIO_CHAN_INFO_SAMP_FREQ);
1558 channels[0].info_mask_separate_available |= BIT(IIO_CHAN_INFO_SAMP_FREQ);
1559 }
1560
1561 return 0;
1562 }
1563
1564 static int ad74115_setup_gpio_chip(struct ad74115_state *st)
1565 {
1566 struct device *dev = &st->spi->dev;
1567
1568 if (!st->gpio_valid_mask)
1569 return 0;
1570
1571 st->gc = (struct gpio_chip) {
1572 .owner = THIS_MODULE,
1573 .label = AD74115_NAME,
1574 .base = -1,
1575 .ngpio = AD74115_GPIO_NUM,
1576 .parent = dev,
1577 .can_sleep = true,
1578 .init_valid_mask = ad74115_gpio_init_valid_mask,
1579 .get_direction = ad74115_gpio_get_direction,
1580 .direction_input = ad74115_gpio_direction_input,
1581 .direction_output = ad74115_gpio_direction_output,
1582 .get = ad74115_gpio_get,
1583 .set = ad74115_gpio_set,
1584 };
1585
1586 return devm_gpiochip_add_data(dev, &st->gc, st);
1587 }
1588
1589 static int ad74115_setup_comp_gpio_chip(struct ad74115_state *st)
1590 {
1591 struct device *dev = &st->spi->dev;
1592 u32 val;
1593 int ret;
1594
1595 ret = regmap_read(st->regmap, AD74115_DIN_CONFIG1_REG, &val);
1596 if (ret)
1597 return ret;
1598
1599 if (!(val & AD74115_DIN_COMPARATOR_EN_MASK))
1600 return 0;
1601
1602 st->comp_gc = (struct gpio_chip) {
1603 .owner = THIS_MODULE,
1604 .label = AD74115_NAME,
1605 .base = -1,
1606 .ngpio = 1,
1607 .parent = dev,
1608 .can_sleep = true,
1609 .get_direction = ad74115_comp_gpio_get_direction,
1610 .get = ad74115_comp_gpio_get,
1611 .set_config = ad74115_comp_gpio_set_config,
1612 };
1613
1614 return devm_gpiochip_add_data(dev, &st->comp_gc, st);
1615 }
1616
1617 static int ad74115_setup(struct iio_dev *indio_dev)
1618 {
1619 struct ad74115_state *st = iio_priv(indio_dev);
1620 struct device *dev = &st->spi->dev;
1621 u32 val, din_range_high;
1622 unsigned int i;
1623 int ret;
1624
1625 ret = ad74115_apply_fw_prop(st, &ad74115_ch_func_fw_prop, &val);
1626 if (ret)
1627 return ret;
1628
1629 indio_dev->num_channels += ad74115_channels_map[val].num_channels;
1630 st->ch_func = val;
1631
1632 ret = ad74115_setup_adc_conv2_range(st);
1633 if (ret)
1634 return ret;
1635
1636 val = device_property_read_bool(dev, "adi,dac-hart-slew");
1637 if (val) {
1638 st->dac_hart_slew = val;
1639
1640 ret = regmap_update_bits(st->regmap, AD74115_OUTPUT_CONFIG_REG,
1641 AD74115_OUTPUT_SLEW_EN_MASK,
1642 FIELD_PREP(AD74115_OUTPUT_SLEW_EN_MASK,
1643 AD74115_SLEW_MODE_HART));
1644 if (ret)
1645 return ret;
1646 }
1647
1648 ret = ad74115_apply_fw_prop(st, &ad74115_din_range_fw_prop,
1649 &din_range_high);
1650 if (ret)
1651 return ret;
1652
1653 ret = device_property_read_u32(dev, "adi,digital-input-sink-microamp", &val);
1654 if (!ret) {
1655 if (din_range_high)
1656 val = DIV_ROUND_CLOSEST(val, AD74115_DIN_SINK_LOW_STEP);
1657 else
1658 val = DIV_ROUND_CLOSEST(val, AD74115_DIN_SINK_HIGH_STEP);
1659
1660 if (val > AD74115_DIN_SINK_MAX)
1661 val = AD74115_DIN_SINK_MAX;
1662
1663 ret = regmap_update_bits(st->regmap, AD74115_DIN_CONFIG1_REG,
1664 AD74115_DIN_SINK_MASK,
1665 FIELD_PREP(AD74115_DIN_SINK_MASK, val));
1666 if (ret)
1667 return ret;
1668 }
1669
1670 ret = ad74115_apply_fw_prop(st, &ad74115_din_threshold_mode_fw_prop, &val);
1671 if (ret)
1672 return ret;
1673
1674 if (val == AD74115_DIN_THRESHOLD_MODE_AVDD && !st->avdd_mv)
1675 return dev_err_probe(dev, -EINVAL,
1676 "AVDD voltage is required for digital input threshold mode AVDD\n");
1677
1678 st->din_threshold_mode = val;
1679
1680 ret = ad74115_apply_fw_prop(st, &ad74115_dac_bipolar_fw_prop, &val);
1681 if (ret)
1682 return ret;
1683
1684 st->dac_bipolar = val;
1685
1686 ret = ad74115_apply_fw_prop(st, &ad74115_rtd_mode_fw_prop, &val);
1687 if (ret)
1688 return ret;
1689
1690 st->rtd_mode_4_wire = val;
1691
1692 ret = ad74115_apply_fw_prop(st, &ad74115_ext2_burnout_current_fw_prop, &val);
1693 if (ret)
1694 return ret;
1695
1696 if (val) {
1697 ret = regmap_update_bits(st->regmap, AD74115_BURNOUT_CONFIG_REG,
1698 AD74115_BURNOUT_EXT2_EN_MASK,
1699 FIELD_PREP(AD74115_BURNOUT_EXT2_EN_MASK, 1));
1700 if (ret)
1701 return ret;
1702 }
1703
1704 ret = ad74115_apply_fw_prop(st, &ad74115_ext1_burnout_current_fw_prop, &val);
1705 if (ret)
1706 return ret;
1707
1708 if (val) {
1709 ret = regmap_update_bits(st->regmap, AD74115_BURNOUT_CONFIG_REG,
1710 AD74115_BURNOUT_EXT1_EN_MASK,
1711 FIELD_PREP(AD74115_BURNOUT_EXT1_EN_MASK, 1));
1712 if (ret)
1713 return ret;
1714 }
1715
1716 ret = ad74115_apply_fw_prop(st, &ad74115_viout_burnout_current_fw_prop, &val);
1717 if (ret)
1718 return ret;
1719
1720 if (val) {
1721 ret = regmap_update_bits(st->regmap, AD74115_BURNOUT_CONFIG_REG,
1722 AD74115_BURNOUT_VIOUT_EN_MASK,
1723 FIELD_PREP(AD74115_BURNOUT_VIOUT_EN_MASK, 1));
1724 if (ret)
1725 return ret;
1726 }
1727
1728 for (i = 0; i < AD74115_GPIO_NUM; i++) {
1729 ret = ad74115_apply_fw_prop(st, &ad74115_gpio_mode_fw_props[i], &val);
1730 if (ret)
1731 return ret;
1732
1733 if (val == AD74115_GPIO_MODE_LOGIC)
1734 st->gpio_valid_mask |= BIT(i);
1735 }
1736
1737 for (i = 0; i < ARRAY_SIZE(ad74115_fw_props); i++) {
1738 ret = ad74115_apply_fw_prop(st, &ad74115_fw_props[i], &val);
1739 if (ret)
1740 return ret;
1741 }
1742
1743 ret = ad74115_setup_gpio_chip(st);
1744 if (ret)
1745 return ret;
1746
1747 ret = ad74115_setup_comp_gpio_chip(st);
1748 if (ret)
1749 return ret;
1750
1751 return ad74115_setup_iio_channels(indio_dev);
1752 }
1753
1754 static int ad74115_reset(struct ad74115_state *st)
1755 {
1756 struct device *dev = &st->spi->dev;
1757 struct gpio_desc *reset_gpio;
1758 int ret;
1759
1760 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1761 if (IS_ERR(reset_gpio))
1762 return dev_err_probe(dev, PTR_ERR(reset_gpio),
1763 "Failed to find reset GPIO\n");
1764
1765 if (reset_gpio) {
1766 fsleep(100);
1767
1768 gpiod_set_value_cansleep(reset_gpio, 0);
1769 } else {
1770 ret = regmap_write(st->regmap, AD74115_CMD_KEY_REG,
1771 AD74115_CMD_KEY_RESET1);
1772 if (ret)
1773 return ret;
1774
1775 ret = regmap_write(st->regmap, AD74115_CMD_KEY_REG,
1776 AD74115_CMD_KEY_RESET2);
1777 if (ret)
1778 return ret;
1779 }
1780
1781 fsleep(1000);
1782
1783 return 0;
1784 }
1785
1786 static int ad74115_setup_trigger(struct iio_dev *indio_dev)
1787 {
1788 struct ad74115_state *st = iio_priv(indio_dev);
1789 struct device *dev = &st->spi->dev;
1790 int ret;
1791
1792 st->irq = fwnode_irq_get_byname(dev_fwnode(dev), "adc_rdy");
1793
1794 if (st->irq == -EPROBE_DEFER)
1795 return -EPROBE_DEFER;
1796
1797 if (st->irq < 0) {
1798 st->irq = 0;
1799 return 0;
1800 }
1801
1802 ret = devm_request_irq(dev, st->irq, ad74115_adc_data_interrupt,
1803 0, AD74115_NAME, indio_dev);
1804 if (ret)
1805 return ret;
1806
1807 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", AD74115_NAME,
1808 iio_device_id(indio_dev));
1809 if (!st->trig)
1810 return -ENOMEM;
1811
1812 st->trig->ops = &ad74115_trigger_ops;
1813 iio_trigger_set_drvdata(st->trig, st);
1814
1815 ret = devm_iio_trigger_register(dev, st->trig);
1816 if (ret)
1817 return ret;
1818
1819 indio_dev->trig = iio_trigger_get(st->trig);
1820
1821 return 0;
1822 }
1823
1824 static int ad74115_probe(struct spi_device *spi)
1825 {
1826 static const char * const regulator_names[] = {
1827 "avcc", "dvcc", "dovdd", "refin",
1828 };
1829 struct device *dev = &spi->dev;
1830 struct ad74115_state *st;
1831 struct iio_dev *indio_dev;
1832 int ret;
1833
1834 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1835 if (!indio_dev)
1836 return -ENOMEM;
1837
1838 st = iio_priv(indio_dev);
1839
1840 st->spi = spi;
1841 mutex_init(&st->lock);
1842 init_completion(&st->adc_data_completion);
1843
1844 indio_dev->name = AD74115_NAME;
1845 indio_dev->modes = INDIO_DIRECT_MODE;
1846 indio_dev->info = &ad74115_info;
1847
1848 ret = devm_regulator_get_enable_read_voltage(dev, "avdd");
1849 if (ret < 0) {
1850 /*
1851 * Since this is both a power supply and only optionally a
1852 * reference voltage, make sure to enable it even when the
1853 * voltage is not available.
1854 */
1855 ret = devm_regulator_get_enable(dev, "avdd");
1856 if (ret)
1857 return dev_err_probe(dev, ret, "failed to enable avdd\n");
1858 } else {
1859 st->avdd_mv = ret / 1000;
1860 }
1861
1862 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),
1863 regulator_names);
1864 if (ret)
1865 return ret;
1866
1867 st->regmap = devm_regmap_init(dev, NULL, st, &ad74115_regmap_config);
1868 if (IS_ERR(st->regmap))
1869 return PTR_ERR(st->regmap);
1870
1871 ret = ad74115_reset(st);
1872 if (ret)
1873 return ret;
1874
1875 ret = ad74115_setup(indio_dev);
1876 if (ret)
1877 return ret;
1878
1879 ret = ad74115_setup_trigger(indio_dev);
1880 if (ret)
1881 return ret;
1882
1883 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
1884 ad74115_trigger_handler,
1885 &ad74115_buffer_ops);
1886 if (ret)
1887 return ret;
1888
1889 return devm_iio_device_register(dev, indio_dev);
1890 }
1891
1892 static int ad74115_unregister_driver(struct spi_driver *spi)
1893 {
1894 spi_unregister_driver(spi);
1895
1896 return 0;
1897 }
1898
1899 static int __init ad74115_register_driver(struct spi_driver *spi)
1900 {
1901 crc8_populate_msb(ad74115_crc8_table, AD74115_CRC_POLYNOMIAL);
1902
1903 return spi_register_driver(spi);
1904 }
1905
1906 static const struct spi_device_id ad74115_spi_id[] = {
1907 { "ad74115h" },
1908 { }
1909 };
1910
1911 MODULE_DEVICE_TABLE(spi, ad74115_spi_id);
1912
1913 static const struct of_device_id ad74115_dt_id[] = {
1914 { .compatible = "adi,ad74115h" },
1915 { }
1916 };
1917 MODULE_DEVICE_TABLE(of, ad74115_dt_id);
1918
1919 static struct spi_driver ad74115_driver = {
1920 .driver = {
1921 .name = "ad74115",
1922 .of_match_table = ad74115_dt_id,
1923 },
1924 .probe = ad74115_probe,
1925 .id_table = ad74115_spi_id,
1926 };
1927
1928 module_driver(ad74115_driver,
1929 ad74115_register_driver, ad74115_unregister_driver);
1930
1931 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1932 MODULE_DESCRIPTION("Analog Devices AD74115 ADDAC");
1933 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes