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Merge tag 'trace-printf-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
[drm/drm-misc.git] / drivers / infiniband / hw / bnxt_re / ib_verbs.c
blob82023394e3300edcbf9555ad6dc283145ade81b1
1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44 #include <net/addrconf.h>
45
46 #include <rdma/ib_verbs.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_umem.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_mad.h>
51 #include <rdma/ib_cache.h>
52 #include <rdma/uverbs_ioctl.h>
53 #include <linux/hashtable.h>
54
55 #include "bnxt_ulp.h"
56
57 #include "roce_hsi.h"
58 #include "qplib_res.h"
59 #include "qplib_sp.h"
60 #include "qplib_fp.h"
61 #include "qplib_rcfw.h"
62
63 #include "bnxt_re.h"
64 #include "ib_verbs.h"
65 #include "debugfs.h"
66
67 #include <rdma/uverbs_types.h>
68 #include <rdma/uverbs_std_types.h>
69
70 #include <rdma/ib_user_ioctl_cmds.h>
71
72 #define UVERBS_MODULE_NAME bnxt_re
73 #include <rdma/uverbs_named_ioctl.h>
74
75 #include <rdma/bnxt_re-abi.h>
76
77 static int __from_ib_access_flags(int iflags)
78 {
79 int qflags = 0;
80
81 if (iflags & IB_ACCESS_LOCAL_WRITE)
82 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
83 if (iflags & IB_ACCESS_REMOTE_READ)
84 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
85 if (iflags & IB_ACCESS_REMOTE_WRITE)
86 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
87 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
88 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
89 if (iflags & IB_ACCESS_MW_BIND)
90 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
91 if (iflags & IB_ZERO_BASED)
92 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
93 if (iflags & IB_ACCESS_ON_DEMAND)
94 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
95 return qflags;
96 };
97
98 static int __to_ib_access_flags(int qflags)
99 {
100 int iflags = 0;
101
102 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
103 iflags |= IB_ACCESS_LOCAL_WRITE;
104 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
105 iflags |= IB_ACCESS_REMOTE_WRITE;
106 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
107 iflags |= IB_ACCESS_REMOTE_READ;
108 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
109 iflags |= IB_ACCESS_REMOTE_ATOMIC;
110 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
111 iflags |= IB_ACCESS_MW_BIND;
112 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
113 iflags |= IB_ZERO_BASED;
114 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
115 iflags |= IB_ACCESS_ON_DEMAND;
116 return iflags;
117 }
118
119 static u8 __qp_access_flags_from_ib(struct bnxt_qplib_chip_ctx *cctx, int iflags)
120 {
121 u8 qflags = 0;
122
123 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx))
124 /* For Wh+ */
125 return (u8)__from_ib_access_flags(iflags);
126
127 /* For P5, P7 and later chips */
128 if (iflags & IB_ACCESS_LOCAL_WRITE)
129 qflags |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE;
130 if (iflags & IB_ACCESS_REMOTE_WRITE)
131 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
132 if (iflags & IB_ACCESS_REMOTE_READ)
133 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
134 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
135 qflags |= CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC;
136
137 return qflags;
138 }
139
140 static int __qp_access_flags_to_ib(struct bnxt_qplib_chip_ctx *cctx, u8 qflags)
141 {
142 int iflags = 0;
143
144 if (!bnxt_qplib_is_chip_gen_p5_p7(cctx))
145 /* For Wh+ */
146 return __to_ib_access_flags(qflags);
147
148 /* For P5, P7 and later chips */
149 if (qflags & CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE)
150 iflags |= IB_ACCESS_LOCAL_WRITE;
151 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE)
152 iflags |= IB_ACCESS_REMOTE_WRITE;
153 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_READ)
154 iflags |= IB_ACCESS_REMOTE_READ;
155 if (qflags & CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC)
156 iflags |= IB_ACCESS_REMOTE_ATOMIC;
157
158 return iflags;
159 }
160
161 static void bnxt_re_check_and_set_relaxed_ordering(struct bnxt_re_dev *rdev,
162 struct bnxt_qplib_mrw *qplib_mr)
163 {
164 if (_is_relaxed_ordering_supported(rdev->dev_attr.dev_cap_flags2) &&
165 pcie_relaxed_ordering_enabled(rdev->en_dev->pdev))
166 qplib_mr->flags |= CMDQ_REGISTER_MR_FLAGS_ENABLE_RO;
167 }
168
169 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
170 struct bnxt_qplib_sge *sg_list, int num)
171 {
172 int i, total = 0;
173
174 for (i = 0; i < num; i++) {
175 sg_list[i].addr = ib_sg_list[i].addr;
176 sg_list[i].lkey = ib_sg_list[i].lkey;
177 sg_list[i].size = ib_sg_list[i].length;
178 total += sg_list[i].size;
179 }
180 return total;
181 }
182
183 /* Device */
184 int bnxt_re_query_device(struct ib_device *ibdev,
185 struct ib_device_attr *ib_attr,
186 struct ib_udata *udata)
187 {
188 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
189 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
190
191 memset(ib_attr, 0, sizeof(*ib_attr));
192 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
193 min(sizeof(dev_attr->fw_ver),
194 sizeof(ib_attr->fw_ver)));
195 addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid,
196 rdev->netdev->dev_addr);
197 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
198 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED;
199
200 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
201 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
202 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
203 ib_attr->max_qp = dev_attr->max_qp;
204 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
205 ib_attr->device_cap_flags =
206 IB_DEVICE_CURR_QP_STATE_MOD
207 | IB_DEVICE_RC_RNR_NAK_GEN
208 | IB_DEVICE_SHUTDOWN_PORT
209 | IB_DEVICE_SYS_IMAGE_GUID
210 | IB_DEVICE_RESIZE_MAX_WR
211 | IB_DEVICE_PORT_ACTIVE_EVENT
212 | IB_DEVICE_N_NOTIFY_CQ
213 | IB_DEVICE_MEM_WINDOW
214 | IB_DEVICE_MEM_WINDOW_TYPE_2B
215 | IB_DEVICE_MEM_MGT_EXTENSIONS;
216 ib_attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
217 ib_attr->max_send_sge = dev_attr->max_qp_sges;
218 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
219 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
220 ib_attr->max_cq = dev_attr->max_cq;
221 ib_attr->max_cqe = dev_attr->max_cq_wqes;
222 ib_attr->max_mr = dev_attr->max_mr;
223 ib_attr->max_pd = dev_attr->max_pd;
224 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
225 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
226 ib_attr->atomic_cap = IB_ATOMIC_NONE;
227 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
228 if (dev_attr->is_atomic) {
229 ib_attr->atomic_cap = IB_ATOMIC_GLOB;
230 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;
231 }
232
233 ib_attr->max_ee_rd_atom = 0;
234 ib_attr->max_res_rd_atom = 0;
235 ib_attr->max_ee_init_rd_atom = 0;
236 ib_attr->max_ee = 0;
237 ib_attr->max_rdd = 0;
238 ib_attr->max_mw = dev_attr->max_mw;
239 ib_attr->max_raw_ipv6_qp = 0;
240 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
241 ib_attr->max_mcast_grp = 0;
242 ib_attr->max_mcast_qp_attach = 0;
243 ib_attr->max_total_mcast_qp_attach = 0;
244 ib_attr->max_ah = dev_attr->max_ah;
245
246 ib_attr->max_srq = dev_attr->max_srq;
247 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
248 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
249
250 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
251
252 ib_attr->max_pkeys = 1;
253 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
254 return 0;
255 }
256
257 int bnxt_re_modify_device(struct ib_device *ibdev,
258 int device_modify_mask,
259 struct ib_device_modify *device_modify)
260 {
261 ibdev_dbg(ibdev, "Modify device with mask 0x%x", device_modify_mask);
262
263 if (device_modify_mask & ~IB_DEVICE_MODIFY_NODE_DESC)
264 return -EOPNOTSUPP;
265
266 if (!(device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC))
267 return 0;
268
269 memcpy(ibdev->node_desc, device_modify->node_desc, IB_DEVICE_NODE_DESC_MAX);
270 return 0;
271 }
272
273 /* Port */
274 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num,
275 struct ib_port_attr *port_attr)
276 {
277 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
278 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
279 int rc;
280
281 memset(port_attr, 0, sizeof(*port_attr));
282
283 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
284 port_attr->state = IB_PORT_ACTIVE;
285 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
286 } else {
287 port_attr->state = IB_PORT_DOWN;
288 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
289 }
290 port_attr->max_mtu = IB_MTU_4096;
291 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
292 port_attr->gid_tbl_len = dev_attr->max_sgid;
293 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
294 IB_PORT_DEVICE_MGMT_SUP |
295 IB_PORT_VENDOR_CLASS_SUP;
296 port_attr->ip_gids = true;
297
298 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
299 port_attr->bad_pkey_cntr = 0;
300 port_attr->qkey_viol_cntr = 0;
301 port_attr->pkey_tbl_len = dev_attr->max_pkey;
302 port_attr->lid = 0;
303 port_attr->sm_lid = 0;
304 port_attr->lmc = 0;
305 port_attr->max_vl_num = 4;
306 port_attr->sm_sl = 0;
307 port_attr->subnet_timeout = 0;
308 port_attr->init_type_reply = 0;
309 rc = ib_get_eth_speed(&rdev->ibdev, port_num, &port_attr->active_speed,
310 &port_attr->active_width);
311
312 return rc;
313 }
314
315 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num,
316 struct ib_port_immutable *immutable)
317 {
318 struct ib_port_attr port_attr;
319
320 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
321 return -EINVAL;
322
323 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
324 immutable->gid_tbl_len = port_attr.gid_tbl_len;
325 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
326 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
327 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
328 return 0;
329 }
330
331 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
332 {
333 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
334
335 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
336 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
337 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
338 }
339
340 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num,
341 u16 index, u16 *pkey)
342 {
343 if (index > 0)
344 return -EINVAL;
345
346 *pkey = IB_DEFAULT_PKEY_FULL;
347
348 return 0;
349 }
350
351 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num,
352 int index, union ib_gid *gid)
353 {
354 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
355 int rc;
356
357 /* Ignore port_num */
358 memset(gid, 0, sizeof(*gid));
359 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
360 &rdev->qplib_res.sgid_tbl, index,
361 (struct bnxt_qplib_gid *)gid);
362 return rc;
363 }
364
365 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
366 {
367 int rc = 0;
368 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
369 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
370 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
371 struct bnxt_qplib_gid *gid_to_del;
372 u16 vlan_id = 0xFFFF;
373
374 /* Delete the entry from the hardware */
375 ctx = *context;
376 if (!ctx)
377 return -EINVAL;
378
379 if (sgid_tbl && sgid_tbl->active) {
380 if (ctx->idx >= sgid_tbl->max)
381 return -EINVAL;
382 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
383 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
384 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
385 * or via the ib_unregister_device path. In the former case QP1
386 * may not be destroyed yet, in which case just return as FW
387 * needs that entry to be present and will fail it's deletion.
388 * We could get invoked again after QP1 is destroyed OR get an
389 * ADD_GID call with a different GID value for the same index
390 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
391 */
392 if (ctx->idx == 0 &&
393 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
394 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
395 ibdev_dbg(&rdev->ibdev,
396 "Trying to delete GID0 while QP1 is alive\n");
397 return -EFAULT;
398 }
399 ctx->refcnt--;
400 if (!ctx->refcnt) {
401 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
402 vlan_id, true);
403 if (rc) {
404 ibdev_err(&rdev->ibdev,
405 "Failed to remove GID: %#x", rc);
406 } else {
407 ctx_tbl = sgid_tbl->ctx;
408 ctx_tbl[ctx->idx] = NULL;
409 kfree(ctx);
410 }
411 }
412 } else {
413 return -EINVAL;
414 }
415 return rc;
416 }
417
418 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
419 {
420 int rc;
421 u32 tbl_idx = 0;
422 u16 vlan_id = 0xFFFF;
423 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
424 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
425 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
426
427 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
428 if (rc)
429 return rc;
430
431 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
432 rdev->qplib_res.netdev->dev_addr,
433 vlan_id, true, &tbl_idx);
434 if (rc == -EALREADY) {
435 ctx_tbl = sgid_tbl->ctx;
436 ctx_tbl[tbl_idx]->refcnt++;
437 *context = ctx_tbl[tbl_idx];
438 return 0;
439 }
440
441 if (rc < 0) {
442 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
443 return rc;
444 }
445
446 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
447 if (!ctx)
448 return -ENOMEM;
449 ctx_tbl = sgid_tbl->ctx;
450 ctx->idx = tbl_idx;
451 ctx->refcnt = 1;
452 ctx_tbl[tbl_idx] = ctx;
453 *context = ctx;
454
455 return rc;
456 }
457
458 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
459 u32 port_num)
460 {
461 return IB_LINK_LAYER_ETHERNET;
462 }
463
464 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
465
466 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
467 {
468 struct bnxt_re_fence_data *fence = &pd->fence;
469 struct ib_mr *ib_mr = &fence->mr->ib_mr;
470 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
471 struct bnxt_re_dev *rdev = pd->rdev;
472
473 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
474 return;
475
476 memset(wqe, 0, sizeof(*wqe));
477 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
478 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
479 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
480 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
481 wqe->bind.zero_based = false;
482 wqe->bind.parent_l_key = ib_mr->lkey;
483 wqe->bind.va = (u64)(unsigned long)fence->va;
484 wqe->bind.length = fence->size;
485 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
486 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
487
488 /* Save the initial rkey in fence structure for now;
489 * wqe->bind.r_key will be set at (re)bind time.
490 */
491 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
492 }
493
494 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
495 {
496 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
497 qplib_qp);
498 struct ib_pd *ib_pd = qp->ib_qp.pd;
499 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
500 struct bnxt_re_fence_data *fence = &pd->fence;
501 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
502 struct bnxt_qplib_swqe wqe;
503 int rc;
504
505 memcpy(&wqe, fence_wqe, sizeof(wqe));
506 wqe.bind.r_key = fence->bind_rkey;
507 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
508
509 ibdev_dbg(&qp->rdev->ibdev,
510 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
511 wqe.bind.r_key, qp->qplib_qp.id, pd);
512 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
513 if (rc) {
514 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
515 return rc;
516 }
517 bnxt_qplib_post_send_db(&qp->qplib_qp);
518
519 return rc;
520 }
521
522 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
523 {
524 struct bnxt_re_fence_data *fence = &pd->fence;
525 struct bnxt_re_dev *rdev = pd->rdev;
526 struct device *dev = &rdev->en_dev->pdev->dev;
527 struct bnxt_re_mr *mr = fence->mr;
528
529 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
530 return;
531
532 if (fence->mw) {
533 bnxt_re_dealloc_mw(fence->mw);
534 fence->mw = NULL;
535 }
536 if (mr) {
537 if (mr->ib_mr.rkey)
538 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
539 true);
540 if (mr->ib_mr.lkey)
541 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
542 kfree(mr);
543 fence->mr = NULL;
544 }
545 if (fence->dma_addr) {
546 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
547 DMA_BIDIRECTIONAL);
548 fence->dma_addr = 0;
549 }
550 }
551
552 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
553 {
554 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
555 struct bnxt_re_fence_data *fence = &pd->fence;
556 struct bnxt_re_dev *rdev = pd->rdev;
557 struct device *dev = &rdev->en_dev->pdev->dev;
558 struct bnxt_re_mr *mr = NULL;
559 dma_addr_t dma_addr = 0;
560 struct ib_mw *mw;
561 int rc;
562
563 if (bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))
564 return 0;
565
566 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
567 DMA_BIDIRECTIONAL);
568 rc = dma_mapping_error(dev, dma_addr);
569 if (rc) {
570 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
571 rc = -EIO;
572 fence->dma_addr = 0;
573 goto fail;
574 }
575 fence->dma_addr = dma_addr;
576
577 /* Allocate a MR */
578 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
579 if (!mr) {
580 rc = -ENOMEM;
581 goto fail;
582 }
583 fence->mr = mr;
584 mr->rdev = rdev;
585 mr->qplib_mr.pd = &pd->qplib_pd;
586 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
587 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
588 if (!_is_alloc_mr_unified(rdev->dev_attr.dev_cap_flags)) {
589 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
590 if (rc) {
591 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
592 goto fail;
593 }
594
595 /* Register MR */
596 mr->ib_mr.lkey = mr->qplib_mr.lkey;
597 } else {
598 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR;
599 }
600 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
601 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
602 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL,
603 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE);
604 if (rc) {
605 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
606 goto fail;
607 }
608 mr->ib_mr.rkey = mr->qplib_mr.rkey;
609
610 /* Create a fence MW only for kernel consumers */
611 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
612 if (IS_ERR(mw)) {
613 ibdev_err(&rdev->ibdev,
614 "Failed to create fence-MW for PD: %p\n", pd);
615 rc = PTR_ERR(mw);
616 goto fail;
617 }
618 fence->mw = mw;
619
620 bnxt_re_create_fence_wqe(pd);
621 return 0;
622
623 fail:
624 bnxt_re_destroy_fence_mr(pd);
625 return rc;
626 }
627
628 static struct bnxt_re_user_mmap_entry*
629 bnxt_re_mmap_entry_insert(struct bnxt_re_ucontext *uctx, u64 mem_offset,
630 enum bnxt_re_mmap_flag mmap_flag, u64 *offset)
631 {
632 struct bnxt_re_user_mmap_entry *entry;
633 int ret;
634
635 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
636 if (!entry)
637 return NULL;
638
639 entry->mem_offset = mem_offset;
640 entry->mmap_flag = mmap_flag;
641 entry->uctx = uctx;
642
643 switch (mmap_flag) {
644 case BNXT_RE_MMAP_SH_PAGE:
645 ret = rdma_user_mmap_entry_insert_exact(&uctx->ib_uctx,
646 &entry->rdma_entry, PAGE_SIZE, 0);
647 break;
648 case BNXT_RE_MMAP_UC_DB:
649 case BNXT_RE_MMAP_WC_DB:
650 case BNXT_RE_MMAP_DBR_BAR:
651 case BNXT_RE_MMAP_DBR_PAGE:
652 case BNXT_RE_MMAP_TOGGLE_PAGE:
653 ret = rdma_user_mmap_entry_insert(&uctx->ib_uctx,
654 &entry->rdma_entry, PAGE_SIZE);
655 break;
656 default:
657 ret = -EINVAL;
658 break;
659 }
660
661 if (ret) {
662 kfree(entry);
663 return NULL;
664 }
665 if (offset)
666 *offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
667
668 return entry;
669 }
670
671 /* Protection Domains */
672 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
673 {
674 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
675 struct bnxt_re_dev *rdev = pd->rdev;
676
677 if (udata) {
678 rdma_user_mmap_entry_remove(pd->pd_db_mmap);
679 pd->pd_db_mmap = NULL;
680 }
681
682 bnxt_re_destroy_fence_mr(pd);
683
684 if (pd->qplib_pd.id) {
685 if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res,
686 &rdev->qplib_res.pd_tbl,
687 &pd->qplib_pd))
688 atomic_dec(&rdev->stats.res.pd_count);
689 }
690 return 0;
691 }
692
693 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
694 {
695 struct ib_device *ibdev = ibpd->device;
696 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
697 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
698 udata, struct bnxt_re_ucontext, ib_uctx);
699 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
700 struct bnxt_re_user_mmap_entry *entry = NULL;
701 u32 active_pds;
702 int rc = 0;
703
704 pd->rdev = rdev;
705 if (bnxt_qplib_alloc_pd(&rdev->qplib_res, &pd->qplib_pd)) {
706 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
707 rc = -ENOMEM;
708 goto fail;
709 }
710
711 if (udata) {
712 struct bnxt_re_pd_resp resp = {};
713
714 if (!ucntx->dpi.dbr) {
715 /* Allocate DPI in alloc_pd to avoid failing of
716 * ibv_devinfo and family of application when DPIs
717 * are depleted.
718 */
719 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res,
720 &ucntx->dpi, ucntx, BNXT_QPLIB_DPI_TYPE_UC)) {
721 rc = -ENOMEM;
722 goto dbfail;
723 }
724 }
725
726 resp.pdid = pd->qplib_pd.id;
727 /* Still allow mapping this DBR to the new user PD. */
728 resp.dpi = ucntx->dpi.dpi;
729
730 entry = bnxt_re_mmap_entry_insert(ucntx, (u64)ucntx->dpi.umdbr,
731 BNXT_RE_MMAP_UC_DB, &resp.dbr);
732
733 if (!entry) {
734 rc = -ENOMEM;
735 goto dbfail;
736 }
737
738 pd->pd_db_mmap = &entry->rdma_entry;
739
740 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
741 if (rc) {
742 rdma_user_mmap_entry_remove(pd->pd_db_mmap);
743 rc = -EFAULT;
744 goto dbfail;
745 }
746 }
747
748 if (!udata)
749 if (bnxt_re_create_fence_mr(pd))
750 ibdev_warn(&rdev->ibdev,
751 "Failed to create Fence-MR\n");
752 active_pds = atomic_inc_return(&rdev->stats.res.pd_count);
753 if (active_pds > rdev->stats.res.pd_watermark)
754 rdev->stats.res.pd_watermark = active_pds;
755
756 return 0;
757 dbfail:
758 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
759 &pd->qplib_pd);
760 fail:
761 return rc;
762 }
763
764 /* Address Handles */
765 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
766 {
767 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
768 struct bnxt_re_dev *rdev = ah->rdev;
769 bool block = true;
770 int rc;
771
772 block = !(flags & RDMA_DESTROY_AH_SLEEPABLE);
773 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, block);
774 if (BNXT_RE_CHECK_RC(rc)) {
775 if (rc == -ETIMEDOUT)
776 rc = 0;
777 else
778 goto fail;
779 }
780 atomic_dec(&rdev->stats.res.ah_count);
781 fail:
782 return rc;
783 }
784
785 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
786 {
787 u8 nw_type;
788
789 switch (ntype) {
790 case RDMA_NETWORK_IPV4:
791 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
792 break;
793 case RDMA_NETWORK_IPV6:
794 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
795 break;
796 default:
797 nw_type = CMDQ_CREATE_AH_TYPE_V1;
798 break;
799 }
800 return nw_type;
801 }
802
803 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
804 struct ib_udata *udata)
805 {
806 struct ib_pd *ib_pd = ib_ah->pd;
807 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
808 struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
809 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
810 struct bnxt_re_dev *rdev = pd->rdev;
811 const struct ib_gid_attr *sgid_attr;
812 struct bnxt_re_gid_ctx *ctx;
813 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
814 u32 active_ahs;
815 u8 nw_type;
816 int rc;
817
818 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
819 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
820 return -EINVAL;
821 }
822
823 ah->rdev = rdev;
824 ah->qplib_ah.pd = &pd->qplib_pd;
825
826 /* Supply the configuration for the HW */
827 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
828 sizeof(union ib_gid));
829 sgid_attr = grh->sgid_attr;
830 /* Get the HW context of the GID. The reference
831 * of GID table entry is already taken by the caller.
832 */
833 ctx = rdma_read_gid_hw_context(sgid_attr);
834 ah->qplib_ah.sgid_index = ctx->idx;
835 ah->qplib_ah.host_sgid_index = grh->sgid_index;
836 ah->qplib_ah.traffic_class = grh->traffic_class;
837 ah->qplib_ah.flow_label = grh->flow_label;
838 ah->qplib_ah.hop_limit = grh->hop_limit;
839 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
840
841 /* Get network header type for this GID */
842 nw_type = rdma_gid_attr_network_type(sgid_attr);
843 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
844
845 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
846 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
847 !(init_attr->flags &
848 RDMA_CREATE_AH_SLEEPABLE));
849 if (rc) {
850 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
851 return rc;
852 }
853
854 /* Write AVID to shared page. */
855 if (udata) {
856 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
857 udata, struct bnxt_re_ucontext, ib_uctx);
858 unsigned long flag;
859 u32 *wrptr;
860
861 spin_lock_irqsave(&uctx->sh_lock, flag);
862 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
863 *wrptr = ah->qplib_ah.id;
864 wmb(); /* make sure cache is updated. */
865 spin_unlock_irqrestore(&uctx->sh_lock, flag);
866 }
867 active_ahs = atomic_inc_return(&rdev->stats.res.ah_count);
868 if (active_ahs > rdev->stats.res.ah_watermark)
869 rdev->stats.res.ah_watermark = active_ahs;
870
871 return 0;
872 }
873
874 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
875 {
876 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
877
878 ah_attr->type = ib_ah->type;
879 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
880 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
881 rdma_ah_set_grh(ah_attr, NULL, 0,
882 ah->qplib_ah.host_sgid_index,
883 0, ah->qplib_ah.traffic_class);
884 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
885 rdma_ah_set_port_num(ah_attr, 1);
886 rdma_ah_set_static_rate(ah_attr, 0);
887 return 0;
888 }
889
890 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
891 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
892 {
893 unsigned long flags;
894
895 spin_lock_irqsave(&qp->scq->cq_lock, flags);
896 if (qp->rcq != qp->scq)
897 spin_lock(&qp->rcq->cq_lock);
898 else
899 __acquire(&qp->rcq->cq_lock);
900
901 return flags;
902 }
903
904 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
905 unsigned long flags)
906 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
907 {
908 if (qp->rcq != qp->scq)
909 spin_unlock(&qp->rcq->cq_lock);
910 else
911 __release(&qp->rcq->cq_lock);
912 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
913 }
914
915 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
916 {
917 struct bnxt_re_qp *gsi_sqp;
918 struct bnxt_re_ah *gsi_sah;
919 struct bnxt_re_dev *rdev;
920 int rc;
921
922 rdev = qp->rdev;
923 gsi_sqp = rdev->gsi_ctx.gsi_sqp;
924 gsi_sah = rdev->gsi_ctx.gsi_sah;
925
926 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
927 bnxt_qplib_destroy_ah(&rdev->qplib_res,
928 &gsi_sah->qplib_ah,
929 true);
930 atomic_dec(&rdev->stats.res.ah_count);
931 bnxt_qplib_clean_qp(&qp->qplib_qp);
932
933 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
934 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
935 if (rc) {
936 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
937 goto fail;
938 }
939 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
940
941 /* remove from active qp list */
942 mutex_lock(&rdev->qp_lock);
943 list_del(&gsi_sqp->list);
944 mutex_unlock(&rdev->qp_lock);
945 atomic_dec(&rdev->stats.res.qp_count);
946
947 kfree(rdev->gsi_ctx.sqp_tbl);
948 kfree(gsi_sah);
949 kfree(gsi_sqp);
950 rdev->gsi_ctx.gsi_sqp = NULL;
951 rdev->gsi_ctx.gsi_sah = NULL;
952 rdev->gsi_ctx.sqp_tbl = NULL;
953
954 return 0;
955 fail:
956 return rc;
957 }
958
959 /* Queue Pairs */
960 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
961 {
962 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
963 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
964 struct bnxt_re_dev *rdev = qp->rdev;
965 struct bnxt_qplib_nq *scq_nq = NULL;
966 struct bnxt_qplib_nq *rcq_nq = NULL;
967 unsigned int flags;
968 int rc;
969
970 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
971
972 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
973 if (rc) {
974 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
975 return rc;
976 }
977
978 if (rdma_is_kernel_res(&qp->ib_qp.res)) {
979 flags = bnxt_re_lock_cqs(qp);
980 bnxt_qplib_clean_qp(&qp->qplib_qp);
981 bnxt_re_unlock_cqs(qp, flags);
982 }
983
984 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
985
986 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) {
987 rc = bnxt_re_destroy_gsi_sqp(qp);
988 if (rc)
989 return rc;
990 }
991
992 mutex_lock(&rdev->qp_lock);
993 list_del(&qp->list);
994 mutex_unlock(&rdev->qp_lock);
995 atomic_dec(&rdev->stats.res.qp_count);
996 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_RC)
997 atomic_dec(&rdev->stats.res.rc_qp_count);
998 else if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD)
999 atomic_dec(&rdev->stats.res.ud_qp_count);
1000
1001 bnxt_re_debug_rem_qpinfo(rdev, qp);
1002
1003 ib_umem_release(qp->rumem);
1004 ib_umem_release(qp->sumem);
1005
1006 /* Flush all the entries of notification queue associated with
1007 * given qp.
1008 */
1009 scq_nq = qplib_qp->scq->nq;
1010 rcq_nq = qplib_qp->rcq->nq;
1011 bnxt_re_synchronize_nq(scq_nq);
1012 if (scq_nq != rcq_nq)
1013 bnxt_re_synchronize_nq(rcq_nq);
1014
1015 return 0;
1016 }
1017
1018 static u8 __from_ib_qp_type(enum ib_qp_type type)
1019 {
1020 switch (type) {
1021 case IB_QPT_GSI:
1022 return CMDQ_CREATE_QP1_TYPE_GSI;
1023 case IB_QPT_RC:
1024 return CMDQ_CREATE_QP_TYPE_RC;
1025 case IB_QPT_UD:
1026 return CMDQ_CREATE_QP_TYPE_UD;
1027 default:
1028 return IB_QPT_MAX;
1029 }
1030 }
1031
1032 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
1033 int rsge, int max)
1034 {
1035 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
1036 rsge = max;
1037 return bnxt_re_get_rwqe_size(rsge);
1038 }
1039
1040 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
1041 {
1042 u16 wqe_size, calc_ils;
1043
1044 wqe_size = bnxt_re_get_swqe_size(nsge);
1045 if (ilsize) {
1046 calc_ils = sizeof(struct sq_send_hdr) + ilsize;
1047 wqe_size = max_t(u16, calc_ils, wqe_size);
1048 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
1049 }
1050 return wqe_size;
1051 }
1052
1053 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
1054 struct ib_qp_init_attr *init_attr)
1055 {
1056 struct bnxt_qplib_dev_attr *dev_attr;
1057 struct bnxt_qplib_qp *qplqp;
1058 struct bnxt_re_dev *rdev;
1059 struct bnxt_qplib_q *sq;
1060 int align, ilsize;
1061
1062 rdev = qp->rdev;
1063 qplqp = &qp->qplib_qp;
1064 sq = &qplqp->sq;
1065 dev_attr = &rdev->dev_attr;
1066
1067 align = sizeof(struct sq_send_hdr);
1068 ilsize = ALIGN(init_attr->cap.max_inline_data, align);
1069
1070 /* For gen p4 and gen p5 fixed wqe compatibility mode
1071 * wqe size is fixed to 128 bytes - ie 6 SGEs
1072 */
1073 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) {
1074 sq->wqe_size = bnxt_re_get_swqe_size(BNXT_STATIC_MAX_SGE);
1075 sq->max_sge = BNXT_STATIC_MAX_SGE;
1076 } else {
1077 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
1078 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
1079 return -EINVAL;
1080 }
1081
1082 if (init_attr->cap.max_inline_data) {
1083 qplqp->max_inline_data = sq->wqe_size -
1084 sizeof(struct sq_send_hdr);
1085 init_attr->cap.max_inline_data = qplqp->max_inline_data;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
1092 struct bnxt_re_qp *qp, struct bnxt_re_ucontext *cntx,
1093 struct bnxt_re_qp_req *ureq)
1094 {
1095 struct bnxt_qplib_qp *qplib_qp;
1096 int bytes = 0, psn_sz;
1097 struct ib_umem *umem;
1098 int psn_nume;
1099
1100 qplib_qp = &qp->qplib_qp;
1101
1102 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
1103 /* Consider mapping PSN search memory only for RC QPs. */
1104 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
1105 psn_sz = bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx) ?
1106 sizeof(struct sq_psn_search_ext) :
1107 sizeof(struct sq_psn_search);
1108 if (cntx && bnxt_re_is_var_size_supported(rdev, cntx)) {
1109 psn_nume = ureq->sq_slots;
1110 } else {
1111 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
1112 qplib_qp->sq.max_wqe : ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
1113 sizeof(struct bnxt_qplib_sge));
1114 }
1115 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
1116 psn_nume = roundup_pow_of_two(psn_nume);
1117 bytes += (psn_nume * psn_sz);
1118 }
1119
1120 bytes = PAGE_ALIGN(bytes);
1121 umem = ib_umem_get(&rdev->ibdev, ureq->qpsva, bytes,
1122 IB_ACCESS_LOCAL_WRITE);
1123 if (IS_ERR(umem))
1124 return PTR_ERR(umem);
1125
1126 qp->sumem = umem;
1127 qplib_qp->sq.sg_info.umem = umem;
1128 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
1129 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
1130 qplib_qp->qp_handle = ureq->qp_handle;
1131
1132 if (!qp->qplib_qp.srq) {
1133 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
1134 bytes = PAGE_ALIGN(bytes);
1135 umem = ib_umem_get(&rdev->ibdev, ureq->qprva, bytes,
1136 IB_ACCESS_LOCAL_WRITE);
1137 if (IS_ERR(umem))
1138 goto rqfail;
1139 qp->rumem = umem;
1140 qplib_qp->rq.sg_info.umem = umem;
1141 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
1142 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
1143 }
1144
1145 qplib_qp->dpi = &cntx->dpi;
1146 return 0;
1147 rqfail:
1148 ib_umem_release(qp->sumem);
1149 qp->sumem = NULL;
1150 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
1151
1152 return PTR_ERR(umem);
1153 }
1154
1155 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
1156 (struct bnxt_re_pd *pd,
1157 struct bnxt_qplib_res *qp1_res,
1158 struct bnxt_qplib_qp *qp1_qp)
1159 {
1160 struct bnxt_re_dev *rdev = pd->rdev;
1161 struct bnxt_re_ah *ah;
1162 union ib_gid sgid;
1163 int rc;
1164
1165 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
1166 if (!ah)
1167 return NULL;
1168
1169 ah->rdev = rdev;
1170 ah->qplib_ah.pd = &pd->qplib_pd;
1171
1172 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
1173 if (rc)
1174 goto fail;
1175
1176 /* supply the dgid data same as sgid */
1177 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
1178 sizeof(union ib_gid));
1179 ah->qplib_ah.sgid_index = 0;
1180
1181 ah->qplib_ah.traffic_class = 0;
1182 ah->qplib_ah.flow_label = 0;
1183 ah->qplib_ah.hop_limit = 1;
1184 ah->qplib_ah.sl = 0;
1185 /* Have DMAC same as SMAC */
1186 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1187
1188 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1189 if (rc) {
1190 ibdev_err(&rdev->ibdev,
1191 "Failed to allocate HW AH for Shadow QP");
1192 goto fail;
1193 }
1194 atomic_inc(&rdev->stats.res.ah_count);
1195
1196 return ah;
1197
1198 fail:
1199 kfree(ah);
1200 return NULL;
1201 }
1202
1203 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1204 (struct bnxt_re_pd *pd,
1205 struct bnxt_qplib_res *qp1_res,
1206 struct bnxt_qplib_qp *qp1_qp)
1207 {
1208 struct bnxt_re_dev *rdev = pd->rdev;
1209 struct bnxt_re_qp *qp;
1210 int rc;
1211
1212 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1213 if (!qp)
1214 return NULL;
1215
1216 qp->rdev = rdev;
1217
1218 /* Initialize the shadow QP structure from the QP1 values */
1219 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1220
1221 qp->qplib_qp.pd = &pd->qplib_pd;
1222 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1223 qp->qplib_qp.type = IB_QPT_UD;
1224
1225 qp->qplib_qp.max_inline_data = 0;
1226 qp->qplib_qp.sig_type = true;
1227
1228 /* Shadow QP SQ depth should be same as QP1 RQ depth */
1229 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1230 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1231 qp->qplib_qp.sq.max_sw_wqe = qp1_qp->rq.max_wqe;
1232 qp->qplib_qp.sq.max_sge = 2;
1233 /* Q full delta can be 1 since it is internal QP */
1234 qp->qplib_qp.sq.q_full_delta = 1;
1235 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1236 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1237
1238 qp->qplib_qp.scq = qp1_qp->scq;
1239 qp->qplib_qp.rcq = qp1_qp->rcq;
1240
1241 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1242 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1243 qp->qplib_qp.rq.max_sw_wqe = qp1_qp->rq.max_wqe;
1244 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1245 /* Q full delta can be 1 since it is internal QP */
1246 qp->qplib_qp.rq.q_full_delta = 1;
1247 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1248 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1249
1250 qp->qplib_qp.mtu = qp1_qp->mtu;
1251
1252 qp->qplib_qp.sq_hdr_buf_size = 0;
1253 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1254 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1255
1256 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1257 if (rc)
1258 goto fail;
1259
1260 spin_lock_init(&qp->sq_lock);
1261 INIT_LIST_HEAD(&qp->list);
1262 mutex_lock(&rdev->qp_lock);
1263 list_add_tail(&qp->list, &rdev->qp_list);
1264 atomic_inc(&rdev->stats.res.qp_count);
1265 mutex_unlock(&rdev->qp_lock);
1266 return qp;
1267 fail:
1268 kfree(qp);
1269 return NULL;
1270 }
1271
1272 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1273 struct ib_qp_init_attr *init_attr,
1274 struct bnxt_re_ucontext *uctx)
1275 {
1276 struct bnxt_qplib_dev_attr *dev_attr;
1277 struct bnxt_qplib_qp *qplqp;
1278 struct bnxt_re_dev *rdev;
1279 struct bnxt_qplib_q *rq;
1280 int entries;
1281
1282 rdev = qp->rdev;
1283 qplqp = &qp->qplib_qp;
1284 rq = &qplqp->rq;
1285 dev_attr = &rdev->dev_attr;
1286
1287 if (init_attr->srq) {
1288 struct bnxt_re_srq *srq;
1289
1290 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1291 qplqp->srq = &srq->qplib_srq;
1292 rq->max_wqe = 0;
1293 } else {
1294 rq->max_sge = init_attr->cap.max_recv_sge;
1295 if (rq->max_sge > dev_attr->max_qp_sges)
1296 rq->max_sge = dev_attr->max_qp_sges;
1297 init_attr->cap.max_recv_sge = rq->max_sge;
1298 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1299 dev_attr->max_qp_sges);
1300 /* Allocate 1 more than what's provided so posting max doesn't
1301 * mean empty.
1302 */
1303 entries = bnxt_re_init_depth(init_attr->cap.max_recv_wr + 1, uctx);
1304 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1305 rq->max_sw_wqe = rq->max_wqe;
1306 rq->q_full_delta = 0;
1307 rq->sg_info.pgsize = PAGE_SIZE;
1308 rq->sg_info.pgshft = PAGE_SHIFT;
1309 }
1310
1311 return 0;
1312 }
1313
1314 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1315 {
1316 struct bnxt_qplib_dev_attr *dev_attr;
1317 struct bnxt_qplib_qp *qplqp;
1318 struct bnxt_re_dev *rdev;
1319
1320 rdev = qp->rdev;
1321 qplqp = &qp->qplib_qp;
1322 dev_attr = &rdev->dev_attr;
1323
1324 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
1325 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1326 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1327 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1328 qplqp->rq.max_sge = 6;
1329 }
1330 }
1331
1332 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1333 struct ib_qp_init_attr *init_attr,
1334 struct bnxt_re_ucontext *uctx,
1335 struct bnxt_re_qp_req *ureq)
1336 {
1337 struct bnxt_qplib_dev_attr *dev_attr;
1338 struct bnxt_qplib_qp *qplqp;
1339 struct bnxt_re_dev *rdev;
1340 struct bnxt_qplib_q *sq;
1341 int diff = 0;
1342 int entries;
1343 int rc;
1344
1345 rdev = qp->rdev;
1346 qplqp = &qp->qplib_qp;
1347 sq = &qplqp->sq;
1348 dev_attr = &rdev->dev_attr;
1349
1350 sq->max_sge = init_attr->cap.max_send_sge;
1351 entries = init_attr->cap.max_send_wr;
1352 if (uctx && qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) {
1353 sq->max_wqe = ureq->sq_slots;
1354 sq->max_sw_wqe = ureq->sq_slots;
1355 sq->wqe_size = sizeof(struct sq_sge);
1356 } else {
1357 if (sq->max_sge > dev_attr->max_qp_sges) {
1358 sq->max_sge = dev_attr->max_qp_sges;
1359 init_attr->cap.max_send_sge = sq->max_sge;
1360 }
1361
1362 rc = bnxt_re_setup_swqe_size(qp, init_attr);
1363 if (rc)
1364 return rc;
1365
1366 /* Allocate 128 + 1 more than what's provided */
1367 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1368 0 : BNXT_QPLIB_RESERVED_QP_WRS;
1369 entries = bnxt_re_init_depth(entries + diff + 1, uctx);
1370 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1371 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
1372 sq->max_sw_wqe = bnxt_qplib_get_depth(sq, qplqp->wqe_mode, true);
1373 else
1374 sq->max_sw_wqe = sq->max_wqe;
1375
1376 }
1377 sq->q_full_delta = diff + 1;
1378 /*
1379 * Reserving one slot for Phantom WQE. Application can
1380 * post one extra entry in this case. But allowing this to avoid
1381 * unexpected Queue full condition
1382 */
1383 qplqp->sq.q_full_delta -= 1;
1384 qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1385 qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1386
1387 return 0;
1388 }
1389
1390 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1391 struct ib_qp_init_attr *init_attr,
1392 struct bnxt_re_ucontext *uctx)
1393 {
1394 struct bnxt_qplib_dev_attr *dev_attr;
1395 struct bnxt_qplib_qp *qplqp;
1396 struct bnxt_re_dev *rdev;
1397 int entries;
1398
1399 rdev = qp->rdev;
1400 qplqp = &qp->qplib_qp;
1401 dev_attr = &rdev->dev_attr;
1402
1403 if (!bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx)) {
1404 entries = bnxt_re_init_depth(init_attr->cap.max_send_wr + 1, uctx);
1405 qplqp->sq.max_wqe = min_t(u32, entries,
1406 dev_attr->max_qp_wqes + 1);
1407 qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1408 init_attr->cap.max_send_wr;
1409 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1410 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1411 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1412 }
1413 }
1414
1415 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1416 struct ib_qp_init_attr *init_attr)
1417 {
1418 struct bnxt_qplib_chip_ctx *chip_ctx;
1419 int qptype;
1420
1421 chip_ctx = rdev->chip_ctx;
1422
1423 qptype = __from_ib_qp_type(init_attr->qp_type);
1424 if (qptype == IB_QPT_MAX) {
1425 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1426 qptype = -EOPNOTSUPP;
1427 goto out;
1428 }
1429
1430 if (bnxt_qplib_is_chip_gen_p5_p7(chip_ctx) &&
1431 init_attr->qp_type == IB_QPT_GSI)
1432 qptype = CMDQ_CREATE_QP_TYPE_GSI;
1433 out:
1434 return qptype;
1435 }
1436
1437 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1438 struct ib_qp_init_attr *init_attr,
1439 struct bnxt_re_ucontext *uctx,
1440 struct bnxt_re_qp_req *ureq)
1441 {
1442 struct bnxt_qplib_dev_attr *dev_attr;
1443 struct bnxt_qplib_qp *qplqp;
1444 struct bnxt_re_dev *rdev;
1445 struct bnxt_re_cq *cq;
1446 int rc = 0, qptype;
1447
1448 rdev = qp->rdev;
1449 qplqp = &qp->qplib_qp;
1450 dev_attr = &rdev->dev_attr;
1451
1452 /* Setup misc params */
1453 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1454 qplqp->pd = &pd->qplib_pd;
1455 qplqp->qp_handle = (u64)qplqp;
1456 qplqp->max_inline_data = init_attr->cap.max_inline_data;
1457 qplqp->sig_type = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR;
1458 qptype = bnxt_re_init_qp_type(rdev, init_attr);
1459 if (qptype < 0) {
1460 rc = qptype;
1461 goto out;
1462 }
1463 qplqp->type = (u8)qptype;
1464 qplqp->wqe_mode = bnxt_re_is_var_size_supported(rdev, uctx);
1465 if (init_attr->qp_type == IB_QPT_RC) {
1466 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1467 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1468 }
1469 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1470 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1471 if (init_attr->create_flags) {
1472 ibdev_dbg(&rdev->ibdev,
1473 "QP create flags 0x%x not supported",
1474 init_attr->create_flags);
1475 return -EOPNOTSUPP;
1476 }
1477
1478 /* Setup CQs */
1479 if (init_attr->send_cq) {
1480 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1481 qplqp->scq = &cq->qplib_cq;
1482 qp->scq = cq;
1483 }
1484
1485 if (init_attr->recv_cq) {
1486 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1487 qplqp->rcq = &cq->qplib_cq;
1488 qp->rcq = cq;
1489 }
1490
1491 /* Setup RQ/SRQ */
1492 rc = bnxt_re_init_rq_attr(qp, init_attr, uctx);
1493 if (rc)
1494 goto out;
1495 if (init_attr->qp_type == IB_QPT_GSI)
1496 bnxt_re_adjust_gsi_rq_attr(qp);
1497
1498 /* Setup SQ */
1499 rc = bnxt_re_init_sq_attr(qp, init_attr, uctx, ureq);
1500 if (rc)
1501 goto out;
1502 if (init_attr->qp_type == IB_QPT_GSI)
1503 bnxt_re_adjust_gsi_sq_attr(qp, init_attr, uctx);
1504
1505 if (uctx) /* This will update DPI and qp_handle */
1506 rc = bnxt_re_init_user_qp(rdev, pd, qp, uctx, ureq);
1507 out:
1508 return rc;
1509 }
1510
1511 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1512 struct bnxt_re_pd *pd)
1513 {
1514 struct bnxt_re_sqp_entries *sqp_tbl;
1515 struct bnxt_re_dev *rdev;
1516 struct bnxt_re_qp *sqp;
1517 struct bnxt_re_ah *sah;
1518 int rc = 0;
1519
1520 rdev = qp->rdev;
1521 /* Create a shadow QP to handle the QP1 traffic */
1522 sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl),
1523 GFP_KERNEL);
1524 if (!sqp_tbl)
1525 return -ENOMEM;
1526 rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1527
1528 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1529 if (!sqp) {
1530 rc = -ENODEV;
1531 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1532 goto out;
1533 }
1534 rdev->gsi_ctx.gsi_sqp = sqp;
1535
1536 sqp->rcq = qp->rcq;
1537 sqp->scq = qp->scq;
1538 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1539 &qp->qplib_qp);
1540 if (!sah) {
1541 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1542 &sqp->qplib_qp);
1543 rc = -ENODEV;
1544 ibdev_err(&rdev->ibdev,
1545 "Failed to create AH entry for ShadowQP");
1546 goto out;
1547 }
1548 rdev->gsi_ctx.gsi_sah = sah;
1549
1550 return 0;
1551 out:
1552 kfree(sqp_tbl);
1553 return rc;
1554 }
1555
1556 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1557 struct ib_qp_init_attr *init_attr)
1558 {
1559 struct bnxt_re_dev *rdev;
1560 struct bnxt_qplib_qp *qplqp;
1561 int rc;
1562
1563 rdev = qp->rdev;
1564 qplqp = &qp->qplib_qp;
1565
1566 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1567 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1568
1569 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1570 if (rc) {
1571 ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1572 goto out;
1573 }
1574
1575 rc = bnxt_re_create_shadow_gsi(qp, pd);
1576 out:
1577 return rc;
1578 }
1579
1580 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1581 struct ib_qp_init_attr *init_attr,
1582 struct bnxt_qplib_dev_attr *dev_attr)
1583 {
1584 bool rc = true;
1585
1586 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1587 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1588 init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1589 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1590 init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1591 ibdev_err(&rdev->ibdev,
1592 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1593 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1594 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1595 init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1596 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1597 init_attr->cap.max_inline_data,
1598 dev_attr->max_inline_data);
1599 rc = false;
1600 }
1601 return rc;
1602 }
1603
1604 int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr,
1605 struct ib_udata *udata)
1606 {
1607 struct bnxt_qplib_dev_attr *dev_attr;
1608 struct bnxt_re_ucontext *uctx;
1609 struct bnxt_re_qp_req ureq;
1610 struct bnxt_re_dev *rdev;
1611 struct bnxt_re_pd *pd;
1612 struct bnxt_re_qp *qp;
1613 struct ib_pd *ib_pd;
1614 u32 active_qps;
1615 int rc;
1616
1617 ib_pd = ib_qp->pd;
1618 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1619 rdev = pd->rdev;
1620 dev_attr = &rdev->dev_attr;
1621 qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1622
1623 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1624 if (udata)
1625 if (ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq))))
1626 return -EFAULT;
1627
1628 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1629 if (!rc) {
1630 rc = -EINVAL;
1631 goto fail;
1632 }
1633
1634 qp->rdev = rdev;
1635 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, uctx, &ureq);
1636 if (rc)
1637 goto fail;
1638
1639 if (qp_init_attr->qp_type == IB_QPT_GSI &&
1640 !(bnxt_qplib_is_chip_gen_p5_p7(rdev->chip_ctx))) {
1641 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1642 if (rc == -ENODEV)
1643 goto qp_destroy;
1644 if (rc)
1645 goto fail;
1646 } else {
1647 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1648 if (rc) {
1649 ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1650 goto free_umem;
1651 }
1652 if (udata) {
1653 struct bnxt_re_qp_resp resp;
1654
1655 resp.qpid = qp->qplib_qp.id;
1656 resp.rsvd = 0;
1657 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1658 if (rc) {
1659 ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1660 goto qp_destroy;
1661 }
1662 }
1663 }
1664
1665 qp->ib_qp.qp_num = qp->qplib_qp.id;
1666 if (qp_init_attr->qp_type == IB_QPT_GSI)
1667 rdev->gsi_ctx.gsi_qp = qp;
1668 spin_lock_init(&qp->sq_lock);
1669 spin_lock_init(&qp->rq_lock);
1670 INIT_LIST_HEAD(&qp->list);
1671 mutex_lock(&rdev->qp_lock);
1672 list_add_tail(&qp->list, &rdev->qp_list);
1673 mutex_unlock(&rdev->qp_lock);
1674 active_qps = atomic_inc_return(&rdev->stats.res.qp_count);
1675 if (active_qps > rdev->stats.res.qp_watermark)
1676 rdev->stats.res.qp_watermark = active_qps;
1677 if (qp_init_attr->qp_type == IB_QPT_RC) {
1678 active_qps = atomic_inc_return(&rdev->stats.res.rc_qp_count);
1679 if (active_qps > rdev->stats.res.rc_qp_watermark)
1680 rdev->stats.res.rc_qp_watermark = active_qps;
1681 } else if (qp_init_attr->qp_type == IB_QPT_UD) {
1682 active_qps = atomic_inc_return(&rdev->stats.res.ud_qp_count);
1683 if (active_qps > rdev->stats.res.ud_qp_watermark)
1684 rdev->stats.res.ud_qp_watermark = active_qps;
1685 }
1686 bnxt_re_debug_add_qpinfo(rdev, qp);
1687
1688 return 0;
1689 qp_destroy:
1690 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1691 free_umem:
1692 ib_umem_release(qp->rumem);
1693 ib_umem_release(qp->sumem);
1694 fail:
1695 return rc;
1696 }
1697
1698 static u8 __from_ib_qp_state(enum ib_qp_state state)
1699 {
1700 switch (state) {
1701 case IB_QPS_RESET:
1702 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1703 case IB_QPS_INIT:
1704 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1705 case IB_QPS_RTR:
1706 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1707 case IB_QPS_RTS:
1708 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1709 case IB_QPS_SQD:
1710 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1711 case IB_QPS_SQE:
1712 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1713 case IB_QPS_ERR:
1714 default:
1715 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1716 }
1717 }
1718
1719 static enum ib_qp_state __to_ib_qp_state(u8 state)
1720 {
1721 switch (state) {
1722 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1723 return IB_QPS_RESET;
1724 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1725 return IB_QPS_INIT;
1726 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1727 return IB_QPS_RTR;
1728 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1729 return IB_QPS_RTS;
1730 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1731 return IB_QPS_SQD;
1732 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1733 return IB_QPS_SQE;
1734 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1735 default:
1736 return IB_QPS_ERR;
1737 }
1738 }
1739
1740 static u32 __from_ib_mtu(enum ib_mtu mtu)
1741 {
1742 switch (mtu) {
1743 case IB_MTU_256:
1744 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1745 case IB_MTU_512:
1746 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1747 case IB_MTU_1024:
1748 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1749 case IB_MTU_2048:
1750 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1751 case IB_MTU_4096:
1752 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1753 default:
1754 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1755 }
1756 }
1757
1758 static enum ib_mtu __to_ib_mtu(u32 mtu)
1759 {
1760 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1761 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1762 return IB_MTU_256;
1763 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1764 return IB_MTU_512;
1765 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1766 return IB_MTU_1024;
1767 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1768 return IB_MTU_2048;
1769 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1770 return IB_MTU_4096;
1771 default:
1772 return IB_MTU_2048;
1773 }
1774 }
1775
1776 /* Shared Receive Queues */
1777 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1778 {
1779 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1780 ib_srq);
1781 struct bnxt_re_dev *rdev = srq->rdev;
1782 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1783 struct bnxt_qplib_nq *nq = NULL;
1784
1785 if (qplib_srq->cq)
1786 nq = qplib_srq->cq->nq;
1787 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) {
1788 free_page((unsigned long)srq->uctx_srq_page);
1789 hash_del(&srq->hash_entry);
1790 }
1791 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1792 ib_umem_release(srq->umem);
1793 atomic_dec(&rdev->stats.res.srq_count);
1794 if (nq)
1795 nq->budget--;
1796 return 0;
1797 }
1798
1799 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1800 struct bnxt_re_pd *pd,
1801 struct bnxt_re_srq *srq,
1802 struct ib_udata *udata)
1803 {
1804 struct bnxt_re_srq_req ureq;
1805 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1806 struct ib_umem *umem;
1807 int bytes = 0;
1808 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1809 udata, struct bnxt_re_ucontext, ib_uctx);
1810
1811 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1812 return -EFAULT;
1813
1814 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1815 bytes = PAGE_ALIGN(bytes);
1816 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1817 IB_ACCESS_LOCAL_WRITE);
1818 if (IS_ERR(umem))
1819 return PTR_ERR(umem);
1820
1821 srq->umem = umem;
1822 qplib_srq->sg_info.umem = umem;
1823 qplib_srq->sg_info.pgsize = PAGE_SIZE;
1824 qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1825 qplib_srq->srq_handle = ureq.srq_handle;
1826 qplib_srq->dpi = &cntx->dpi;
1827
1828 return 0;
1829 }
1830
1831 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1832 struct ib_srq_init_attr *srq_init_attr,
1833 struct ib_udata *udata)
1834 {
1835 struct bnxt_qplib_dev_attr *dev_attr;
1836 struct bnxt_qplib_nq *nq = NULL;
1837 struct bnxt_re_ucontext *uctx;
1838 struct bnxt_re_dev *rdev;
1839 struct bnxt_re_srq *srq;
1840 struct bnxt_re_pd *pd;
1841 struct ib_pd *ib_pd;
1842 u32 active_srqs;
1843 int rc, entries;
1844
1845 ib_pd = ib_srq->pd;
1846 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1847 rdev = pd->rdev;
1848 dev_attr = &rdev->dev_attr;
1849 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1850
1851 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1852 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1853 rc = -EINVAL;
1854 goto exit;
1855 }
1856
1857 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1858 rc = -EOPNOTSUPP;
1859 goto exit;
1860 }
1861
1862 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
1863 srq->rdev = rdev;
1864 srq->qplib_srq.pd = &pd->qplib_pd;
1865 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1866 /* Allocate 1 more than what's provided so posting max doesn't
1867 * mean empty
1868 */
1869 entries = bnxt_re_init_depth(srq_init_attr->attr.max_wr + 1, uctx);
1870 if (entries > dev_attr->max_srq_wqes + 1)
1871 entries = dev_attr->max_srq_wqes + 1;
1872 srq->qplib_srq.max_wqe = entries;
1873
1874 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1875 /* 128 byte wqe size for SRQ . So use max sges */
1876 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1877 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1878 srq->srq_limit = srq_init_attr->attr.srq_limit;
1879 srq->qplib_srq.eventq_hw_ring_id = rdev->nqr->nq[0].ring_id;
1880 nq = &rdev->nqr->nq[0];
1881
1882 if (udata) {
1883 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1884 if (rc)
1885 goto fail;
1886 }
1887
1888 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1889 if (rc) {
1890 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1891 goto fail;
1892 }
1893
1894 if (udata) {
1895 struct bnxt_re_srq_resp resp = {};
1896
1897 resp.srqid = srq->qplib_srq.id;
1898 if (rdev->chip_ctx->modes.toggle_bits & BNXT_QPLIB_SRQ_TOGGLE_BIT) {
1899 hash_add(rdev->srq_hash, &srq->hash_entry, srq->qplib_srq.id);
1900 srq->uctx_srq_page = (void *)get_zeroed_page(GFP_KERNEL);
1901 if (!srq->uctx_srq_page) {
1902 rc = -ENOMEM;
1903 goto fail;
1904 }
1905 resp.comp_mask |= BNXT_RE_SRQ_TOGGLE_PAGE_SUPPORT;
1906 }
1907 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1908 if (rc) {
1909 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1910 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1911 &srq->qplib_srq);
1912 goto fail;
1913 }
1914 }
1915 if (nq)
1916 nq->budget++;
1917 active_srqs = atomic_inc_return(&rdev->stats.res.srq_count);
1918 if (active_srqs > rdev->stats.res.srq_watermark)
1919 rdev->stats.res.srq_watermark = active_srqs;
1920 spin_lock_init(&srq->lock);
1921
1922 return 0;
1923
1924 fail:
1925 ib_umem_release(srq->umem);
1926 exit:
1927 return rc;
1928 }
1929
1930 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1931 enum ib_srq_attr_mask srq_attr_mask,
1932 struct ib_udata *udata)
1933 {
1934 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1935 ib_srq);
1936 struct bnxt_re_dev *rdev = srq->rdev;
1937 int rc;
1938
1939 switch (srq_attr_mask) {
1940 case IB_SRQ_MAX_WR:
1941 /* SRQ resize is not supported */
1942 return -EINVAL;
1943 case IB_SRQ_LIMIT:
1944 /* Change the SRQ threshold */
1945 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1946 return -EINVAL;
1947
1948 srq->qplib_srq.threshold = srq_attr->srq_limit;
1949 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1950 if (rc) {
1951 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1952 return rc;
1953 }
1954 /* On success, update the shadow */
1955 srq->srq_limit = srq_attr->srq_limit;
1956 /* No need to Build and send response back to udata */
1957 return 0;
1958 default:
1959 ibdev_err(&rdev->ibdev,
1960 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1961 return -EINVAL;
1962 }
1963 }
1964
1965 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1966 {
1967 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1968 ib_srq);
1969 struct bnxt_re_srq tsrq;
1970 struct bnxt_re_dev *rdev = srq->rdev;
1971 int rc;
1972
1973 /* Get live SRQ attr */
1974 tsrq.qplib_srq.id = srq->qplib_srq.id;
1975 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1976 if (rc) {
1977 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1978 return rc;
1979 }
1980 srq_attr->max_wr = srq->qplib_srq.max_wqe;
1981 srq_attr->max_sge = srq->qplib_srq.max_sge;
1982 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1983
1984 return 0;
1985 }
1986
1987 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1988 const struct ib_recv_wr **bad_wr)
1989 {
1990 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1991 ib_srq);
1992 struct bnxt_qplib_swqe wqe;
1993 unsigned long flags;
1994 int rc = 0;
1995
1996 spin_lock_irqsave(&srq->lock, flags);
1997 while (wr) {
1998 /* Transcribe each ib_recv_wr to qplib_swqe */
1999 wqe.num_sge = wr->num_sge;
2000 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2001 wqe.wr_id = wr->wr_id;
2002 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2003
2004 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
2005 if (rc) {
2006 *bad_wr = wr;
2007 break;
2008 }
2009 wr = wr->next;
2010 }
2011 spin_unlock_irqrestore(&srq->lock, flags);
2012
2013 return rc;
2014 }
2015 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
2016 struct bnxt_re_qp *qp1_qp,
2017 int qp_attr_mask)
2018 {
2019 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
2020 int rc;
2021
2022 if (qp_attr_mask & IB_QP_STATE) {
2023 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
2024 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
2025 }
2026 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
2027 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
2028 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
2029 }
2030
2031 if (qp_attr_mask & IB_QP_QKEY) {
2032 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
2033 /* Using a Random QKEY */
2034 qp->qplib_qp.qkey = 0x81818181;
2035 }
2036 if (qp_attr_mask & IB_QP_SQ_PSN) {
2037 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2038 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
2039 }
2040
2041 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2042 if (rc)
2043 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
2044 return rc;
2045 }
2046
2047 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2048 int qp_attr_mask, struct ib_udata *udata)
2049 {
2050 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2051 struct bnxt_re_dev *rdev = qp->rdev;
2052 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2053 enum ib_qp_state curr_qp_state, new_qp_state;
2054 int rc, entries;
2055 unsigned int flags;
2056 u8 nw_type;
2057
2058 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
2059 return -EOPNOTSUPP;
2060
2061 qp->qplib_qp.modify_flags = 0;
2062 if (qp_attr_mask & IB_QP_STATE) {
2063 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
2064 new_qp_state = qp_attr->qp_state;
2065 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
2066 ib_qp->qp_type, qp_attr_mask)) {
2067 ibdev_err(&rdev->ibdev,
2068 "Invalid attribute mask: %#x specified ",
2069 qp_attr_mask);
2070 ibdev_err(&rdev->ibdev,
2071 "for qpn: %#x type: %#x",
2072 ib_qp->qp_num, ib_qp->qp_type);
2073 ibdev_err(&rdev->ibdev,
2074 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
2075 curr_qp_state, new_qp_state);
2076 return -EINVAL;
2077 }
2078 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
2079 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
2080
2081 if (!qp->sumem &&
2082 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
2083 ibdev_dbg(&rdev->ibdev,
2084 "Move QP = %p to flush list\n", qp);
2085 flags = bnxt_re_lock_cqs(qp);
2086 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
2087 bnxt_re_unlock_cqs(qp, flags);
2088 }
2089 if (!qp->sumem &&
2090 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
2091 ibdev_dbg(&rdev->ibdev,
2092 "Move QP = %p out of flush list\n", qp);
2093 flags = bnxt_re_lock_cqs(qp);
2094 bnxt_qplib_clean_qp(&qp->qplib_qp);
2095 bnxt_re_unlock_cqs(qp, flags);
2096 }
2097 }
2098 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
2099 qp->qplib_qp.modify_flags |=
2100 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
2101 qp->qplib_qp.en_sqd_async_notify = true;
2102 }
2103 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
2104 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
2105 qp->qplib_qp.access =
2106 __qp_access_flags_from_ib(qp->qplib_qp.cctx,
2107 qp_attr->qp_access_flags);
2108 /* LOCAL_WRITE access must be set to allow RC receive */
2109 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE;
2110 }
2111 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
2112 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
2113 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
2114 }
2115 if (qp_attr_mask & IB_QP_QKEY) {
2116 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
2117 qp->qplib_qp.qkey = qp_attr->qkey;
2118 }
2119 if (qp_attr_mask & IB_QP_AV) {
2120 const struct ib_global_route *grh =
2121 rdma_ah_read_grh(&qp_attr->ah_attr);
2122 const struct ib_gid_attr *sgid_attr;
2123 struct bnxt_re_gid_ctx *ctx;
2124
2125 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
2126 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
2127 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
2128 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
2129 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
2130 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
2131 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
2132 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
2133 sizeof(qp->qplib_qp.ah.dgid.data));
2134 qp->qplib_qp.ah.flow_label = grh->flow_label;
2135 sgid_attr = grh->sgid_attr;
2136 /* Get the HW context of the GID. The reference
2137 * of GID table entry is already taken by the caller.
2138 */
2139 ctx = rdma_read_gid_hw_context(sgid_attr);
2140 qp->qplib_qp.ah.sgid_index = ctx->idx;
2141 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
2142 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
2143 qp->qplib_qp.ah.traffic_class = grh->traffic_class >> 2;
2144 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
2145 ether_addr_copy(qp->qplib_qp.ah.dmac,
2146 qp_attr->ah_attr.roce.dmac);
2147
2148 rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
2149 &qp->qplib_qp.smac[0]);
2150 if (rc)
2151 return rc;
2152
2153 nw_type = rdma_gid_attr_network_type(sgid_attr);
2154 switch (nw_type) {
2155 case RDMA_NETWORK_IPV4:
2156 qp->qplib_qp.nw_type =
2157 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
2158 break;
2159 case RDMA_NETWORK_IPV6:
2160 qp->qplib_qp.nw_type =
2161 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
2162 break;
2163 default:
2164 qp->qplib_qp.nw_type =
2165 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
2166 break;
2167 }
2168 }
2169
2170 if (qp_attr_mask & IB_QP_PATH_MTU) {
2171 qp->qplib_qp.modify_flags |=
2172 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
2173 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
2174 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
2175 } else if (qp_attr->qp_state == IB_QPS_RTR) {
2176 qp->qplib_qp.modify_flags |=
2177 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
2178 qp->qplib_qp.path_mtu =
2179 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
2180 qp->qplib_qp.mtu =
2181 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
2182 }
2183
2184 if (qp_attr_mask & IB_QP_TIMEOUT) {
2185 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
2186 qp->qplib_qp.timeout = qp_attr->timeout;
2187 }
2188 if (qp_attr_mask & IB_QP_RETRY_CNT) {
2189 qp->qplib_qp.modify_flags |=
2190 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
2191 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
2192 }
2193 if (qp_attr_mask & IB_QP_RNR_RETRY) {
2194 qp->qplib_qp.modify_flags |=
2195 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
2196 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
2197 }
2198 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
2199 qp->qplib_qp.modify_flags |=
2200 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
2201 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
2202 }
2203 if (qp_attr_mask & IB_QP_RQ_PSN) {
2204 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
2205 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
2206 }
2207 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2208 qp->qplib_qp.modify_flags |=
2209 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
2210 /* Cap the max_rd_atomic to device max */
2211 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
2212 dev_attr->max_qp_rd_atom);
2213 }
2214 if (qp_attr_mask & IB_QP_SQ_PSN) {
2215 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
2216 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
2217 }
2218 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2219 if (qp_attr->max_dest_rd_atomic >
2220 dev_attr->max_qp_init_rd_atom) {
2221 ibdev_err(&rdev->ibdev,
2222 "max_dest_rd_atomic requested%d is > dev_max%d",
2223 qp_attr->max_dest_rd_atomic,
2224 dev_attr->max_qp_init_rd_atom);
2225 return -EINVAL;
2226 }
2227
2228 qp->qplib_qp.modify_flags |=
2229 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
2230 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
2231 }
2232 if (qp_attr_mask & IB_QP_CAP) {
2233 struct bnxt_re_ucontext *uctx =
2234 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
2235
2236 qp->qplib_qp.modify_flags |=
2237 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
2238 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
2239 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2240 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2241 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2242 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2243 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2244 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2245 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2246 (qp_attr->cap.max_inline_data >=
2247 dev_attr->max_inline_data)) {
2248 ibdev_err(&rdev->ibdev,
2249 "Create QP failed - max exceeded");
2250 return -EINVAL;
2251 }
2252 entries = bnxt_re_init_depth(qp_attr->cap.max_send_wr, uctx);
2253 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2254 dev_attr->max_qp_wqes + 1);
2255 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2256 qp_attr->cap.max_send_wr;
2257 /*
2258 * Reserving one slot for Phantom WQE. Some application can
2259 * post one extra entry in this case. Allowing this to avoid
2260 * unexpected Queue full condition
2261 */
2262 qp->qplib_qp.sq.q_full_delta -= 1;
2263 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2264 if (qp->qplib_qp.rq.max_wqe) {
2265 entries = bnxt_re_init_depth(qp_attr->cap.max_recv_wr, uctx);
2266 qp->qplib_qp.rq.max_wqe =
2267 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2268 qp->qplib_qp.rq.max_sw_wqe = qp->qplib_qp.rq.max_wqe;
2269 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2270 qp_attr->cap.max_recv_wr;
2271 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2272 } else {
2273 /* SRQ was used prior, just ignore the RQ caps */
2274 }
2275 }
2276 if (qp_attr_mask & IB_QP_DEST_QPN) {
2277 qp->qplib_qp.modify_flags |=
2278 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2279 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2280 }
2281 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2282 if (rc) {
2283 ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2284 return rc;
2285 }
2286 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2287 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2288 return rc;
2289 }
2290
2291 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2292 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2293 {
2294 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2295 struct bnxt_re_dev *rdev = qp->rdev;
2296 struct bnxt_qplib_qp *qplib_qp;
2297 int rc;
2298
2299 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
2300 if (!qplib_qp)
2301 return -ENOMEM;
2302
2303 qplib_qp->id = qp->qplib_qp.id;
2304 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2305
2306 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2307 if (rc) {
2308 ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2309 goto out;
2310 }
2311 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2312 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2313 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2314 qp_attr->qp_access_flags = __qp_access_flags_to_ib(qp->qplib_qp.cctx,
2315 qplib_qp->access);
2316 qp_attr->pkey_index = qplib_qp->pkey_index;
2317 qp_attr->qkey = qplib_qp->qkey;
2318 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2319 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2320 qplib_qp->ah.host_sgid_index,
2321 qplib_qp->ah.hop_limit,
2322 qplib_qp->ah.traffic_class);
2323 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2324 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2325 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2326 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2327 qp_attr->timeout = qplib_qp->timeout;
2328 qp_attr->retry_cnt = qplib_qp->retry_cnt;
2329 qp_attr->rnr_retry = qplib_qp->rnr_retry;
2330 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2331 qp_attr->rq_psn = qplib_qp->rq.psn;
2332 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2333 qp_attr->sq_psn = qplib_qp->sq.psn;
2334 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2335 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2336 IB_SIGNAL_REQ_WR;
2337 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2338
2339 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2340 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2341 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2342 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2343 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2344 qp_init_attr->cap = qp_attr->cap;
2345
2346 out:
2347 kfree(qplib_qp);
2348 return rc;
2349 }
2350
2351 /* Routine for sending QP1 packets for RoCE V1 an V2
2352 */
2353 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2354 const struct ib_send_wr *wr,
2355 struct bnxt_qplib_swqe *wqe,
2356 int payload_size)
2357 {
2358 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2359 ib_ah);
2360 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2361 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2362 struct bnxt_qplib_sge sge;
2363 u8 nw_type;
2364 u16 ether_type;
2365 union ib_gid dgid;
2366 bool is_eth = false;
2367 bool is_vlan = false;
2368 bool is_grh = false;
2369 bool is_udp = false;
2370 u8 ip_version = 0;
2371 u16 vlan_id = 0xFFFF;
2372 void *buf;
2373 int i, rc;
2374
2375 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2376
2377 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2378 if (rc)
2379 return rc;
2380
2381 /* Get network header type for this GID */
2382 nw_type = rdma_gid_attr_network_type(sgid_attr);
2383 switch (nw_type) {
2384 case RDMA_NETWORK_IPV4:
2385 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2386 break;
2387 case RDMA_NETWORK_IPV6:
2388 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2389 break;
2390 default:
2391 nw_type = BNXT_RE_ROCE_V1_PACKET;
2392 break;
2393 }
2394 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2395 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2396 if (is_udp) {
2397 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2398 ip_version = 4;
2399 ether_type = ETH_P_IP;
2400 } else {
2401 ip_version = 6;
2402 ether_type = ETH_P_IPV6;
2403 }
2404 is_grh = false;
2405 } else {
2406 ether_type = ETH_P_IBOE;
2407 is_grh = true;
2408 }
2409
2410 is_eth = true;
2411 is_vlan = vlan_id && (vlan_id < 0x1000);
2412
2413 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2414 ip_version, is_udp, 0, &qp->qp1_hdr);
2415
2416 /* ETH */
2417 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2418 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2419
2420 /* For vlan, check the sgid for vlan existence */
2421
2422 if (!is_vlan) {
2423 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2424 } else {
2425 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2426 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2427 }
2428
2429 if (is_grh || (ip_version == 6)) {
2430 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2431 sizeof(sgid_attr->gid));
2432 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2433 sizeof(sgid_attr->gid));
2434 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
2435 }
2436
2437 if (ip_version == 4) {
2438 qp->qp1_hdr.ip4.tos = 0;
2439 qp->qp1_hdr.ip4.id = 0;
2440 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2441 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2442
2443 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2444 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2445 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2446 }
2447
2448 if (is_udp) {
2449 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2450 qp->qp1_hdr.udp.sport = htons(0x8CD1);
2451 qp->qp1_hdr.udp.csum = 0;
2452 }
2453
2454 /* BTH */
2455 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2456 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2457 qp->qp1_hdr.immediate_present = 1;
2458 } else {
2459 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2460 }
2461 if (wr->send_flags & IB_SEND_SOLICITED)
2462 qp->qp1_hdr.bth.solicited_event = 1;
2463 /* pad_count */
2464 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2465
2466 /* P_key for QP1 is for all members */
2467 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2468 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2469 qp->qp1_hdr.bth.ack_req = 0;
2470 qp->send_psn++;
2471 qp->send_psn &= BTH_PSN_MASK;
2472 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2473 /* DETH */
2474 /* Use the priviledged Q_Key for QP1 */
2475 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2476 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2477
2478 /* Pack the QP1 to the transmit buffer */
2479 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2480 if (buf) {
2481 ib_ud_header_pack(&qp->qp1_hdr, buf);
2482 for (i = wqe->num_sge; i; i--) {
2483 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2484 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2485 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2486 }
2487
2488 /*
2489 * Max Header buf size for IPV6 RoCE V2 is 86,
2490 * which is same as the QP1 SQ header buffer.
2491 * Header buf size for IPV4 RoCE V2 can be 66.
2492 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2493 * Subtract 20 bytes from QP1 SQ header buf size
2494 */
2495 if (is_udp && ip_version == 4)
2496 sge.size -= 20;
2497 /*
2498 * Max Header buf size for RoCE V1 is 78.
2499 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2500 * Subtract 8 bytes from QP1 SQ header buf size
2501 */
2502 if (!is_udp)
2503 sge.size -= 8;
2504
2505 /* Subtract 4 bytes for non vlan packets */
2506 if (!is_vlan)
2507 sge.size -= 4;
2508
2509 wqe->sg_list[0].addr = sge.addr;
2510 wqe->sg_list[0].lkey = sge.lkey;
2511 wqe->sg_list[0].size = sge.size;
2512 wqe->num_sge++;
2513
2514 } else {
2515 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2516 rc = -ENOMEM;
2517 }
2518 return rc;
2519 }
2520
2521 /* For the MAD layer, it only provides the recv SGE the size of
2522 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2523 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2524 * receive packet (334 bytes) with no VLAN and then copy the GRH
2525 * and the MAD datagram out to the provided SGE.
2526 */
2527 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2528 const struct ib_recv_wr *wr,
2529 struct bnxt_qplib_swqe *wqe,
2530 int payload_size)
2531 {
2532 struct bnxt_re_sqp_entries *sqp_entry;
2533 struct bnxt_qplib_sge ref, sge;
2534 struct bnxt_re_dev *rdev;
2535 u32 rq_prod_index;
2536
2537 rdev = qp->rdev;
2538
2539 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2540
2541 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2542 return -ENOMEM;
2543
2544 /* Create 1 SGE to receive the entire
2545 * ethernet packet
2546 */
2547 /* Save the reference from ULP */
2548 ref.addr = wqe->sg_list[0].addr;
2549 ref.lkey = wqe->sg_list[0].lkey;
2550 ref.size = wqe->sg_list[0].size;
2551
2552 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2553
2554 /* SGE 1 */
2555 wqe->sg_list[0].addr = sge.addr;
2556 wqe->sg_list[0].lkey = sge.lkey;
2557 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2558 sge.size -= wqe->sg_list[0].size;
2559
2560 sqp_entry->sge.addr = ref.addr;
2561 sqp_entry->sge.lkey = ref.lkey;
2562 sqp_entry->sge.size = ref.size;
2563 /* Store the wrid for reporting completion */
2564 sqp_entry->wrid = wqe->wr_id;
2565 /* change the wqe->wrid to table index */
2566 wqe->wr_id = rq_prod_index;
2567 return 0;
2568 }
2569
2570 static int is_ud_qp(struct bnxt_re_qp *qp)
2571 {
2572 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2573 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2574 }
2575
2576 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2577 const struct ib_send_wr *wr,
2578 struct bnxt_qplib_swqe *wqe)
2579 {
2580 struct bnxt_re_ah *ah = NULL;
2581
2582 if (is_ud_qp(qp)) {
2583 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2584 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2585 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2586 wqe->send.avid = ah->qplib_ah.id;
2587 }
2588 switch (wr->opcode) {
2589 case IB_WR_SEND:
2590 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2591 break;
2592 case IB_WR_SEND_WITH_IMM:
2593 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2594 wqe->send.imm_data = be32_to_cpu(wr->ex.imm_data);
2595 break;
2596 case IB_WR_SEND_WITH_INV:
2597 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2598 wqe->send.inv_key = wr->ex.invalidate_rkey;
2599 break;
2600 default:
2601 return -EINVAL;
2602 }
2603 if (wr->send_flags & IB_SEND_SIGNALED)
2604 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2605 if (wr->send_flags & IB_SEND_FENCE)
2606 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2607 if (wr->send_flags & IB_SEND_SOLICITED)
2608 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2609 if (wr->send_flags & IB_SEND_INLINE)
2610 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2611
2612 return 0;
2613 }
2614
2615 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2616 struct bnxt_qplib_swqe *wqe)
2617 {
2618 switch (wr->opcode) {
2619 case IB_WR_RDMA_WRITE:
2620 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2621 break;
2622 case IB_WR_RDMA_WRITE_WITH_IMM:
2623 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2624 wqe->rdma.imm_data = be32_to_cpu(wr->ex.imm_data);
2625 break;
2626 case IB_WR_RDMA_READ:
2627 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2628 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2629 break;
2630 default:
2631 return -EINVAL;
2632 }
2633 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2634 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2635 if (wr->send_flags & IB_SEND_SIGNALED)
2636 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2637 if (wr->send_flags & IB_SEND_FENCE)
2638 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2639 if (wr->send_flags & IB_SEND_SOLICITED)
2640 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2641 if (wr->send_flags & IB_SEND_INLINE)
2642 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2643
2644 return 0;
2645 }
2646
2647 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2648 struct bnxt_qplib_swqe *wqe)
2649 {
2650 switch (wr->opcode) {
2651 case IB_WR_ATOMIC_CMP_AND_SWP:
2652 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2653 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2654 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2655 break;
2656 case IB_WR_ATOMIC_FETCH_AND_ADD:
2657 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2658 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2659 break;
2660 default:
2661 return -EINVAL;
2662 }
2663 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2664 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2665 if (wr->send_flags & IB_SEND_SIGNALED)
2666 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2667 if (wr->send_flags & IB_SEND_FENCE)
2668 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2669 if (wr->send_flags & IB_SEND_SOLICITED)
2670 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2671 return 0;
2672 }
2673
2674 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2675 struct bnxt_qplib_swqe *wqe)
2676 {
2677 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2678 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2679
2680 if (wr->send_flags & IB_SEND_SIGNALED)
2681 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2682 if (wr->send_flags & IB_SEND_SOLICITED)
2683 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2684
2685 return 0;
2686 }
2687
2688 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2689 struct bnxt_qplib_swqe *wqe)
2690 {
2691 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2692 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2693 int access = wr->access;
2694
2695 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2696 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2697 wqe->frmr.page_list = mr->pages;
2698 wqe->frmr.page_list_len = mr->npages;
2699 wqe->frmr.levels = qplib_frpl->hwq.level;
2700 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2701
2702 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2703 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2704
2705 if (access & IB_ACCESS_LOCAL_WRITE)
2706 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2707 if (access & IB_ACCESS_REMOTE_READ)
2708 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2709 if (access & IB_ACCESS_REMOTE_WRITE)
2710 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2711 if (access & IB_ACCESS_REMOTE_ATOMIC)
2712 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2713 if (access & IB_ACCESS_MW_BIND)
2714 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2715
2716 wqe->frmr.l_key = wr->key;
2717 wqe->frmr.length = wr->mr->length;
2718 wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K);
2719 wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K);
2720 wqe->frmr.va = wr->mr->iova;
2721 return 0;
2722 }
2723
2724 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2725 const struct ib_send_wr *wr,
2726 struct bnxt_qplib_swqe *wqe)
2727 {
2728 /* Copy the inline data to the data field */
2729 u8 *in_data;
2730 u32 i, sge_len;
2731 void *sge_addr;
2732
2733 in_data = wqe->inline_data;
2734 for (i = 0; i < wr->num_sge; i++) {
2735 sge_addr = (void *)(unsigned long)
2736 wr->sg_list[i].addr;
2737 sge_len = wr->sg_list[i].length;
2738
2739 if ((sge_len + wqe->inline_len) >
2740 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2741 ibdev_err(&rdev->ibdev,
2742 "Inline data size requested > supported value");
2743 return -EINVAL;
2744 }
2745 sge_len = wr->sg_list[i].length;
2746
2747 memcpy(in_data, sge_addr, sge_len);
2748 in_data += wr->sg_list[i].length;
2749 wqe->inline_len += wr->sg_list[i].length;
2750 }
2751 return wqe->inline_len;
2752 }
2753
2754 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2755 const struct ib_send_wr *wr,
2756 struct bnxt_qplib_swqe *wqe)
2757 {
2758 int payload_sz = 0;
2759
2760 if (wr->send_flags & IB_SEND_INLINE)
2761 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2762 else
2763 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2764 wqe->num_sge);
2765
2766 return payload_sz;
2767 }
2768
2769 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2770 {
2771 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2772 qp->ib_qp.qp_type == IB_QPT_GSI ||
2773 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2774 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2775 int qp_attr_mask;
2776 struct ib_qp_attr qp_attr;
2777
2778 qp_attr_mask = IB_QP_STATE;
2779 qp_attr.qp_state = IB_QPS_RTS;
2780 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2781 qp->qplib_qp.wqe_cnt = 0;
2782 }
2783 }
2784
2785 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2786 struct bnxt_re_qp *qp,
2787 const struct ib_send_wr *wr)
2788 {
2789 int rc = 0, payload_sz = 0;
2790 unsigned long flags;
2791
2792 spin_lock_irqsave(&qp->sq_lock, flags);
2793 while (wr) {
2794 struct bnxt_qplib_swqe wqe = {};
2795
2796 /* Common */
2797 wqe.num_sge = wr->num_sge;
2798 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2799 ibdev_err(&rdev->ibdev,
2800 "Limit exceeded for Send SGEs");
2801 rc = -EINVAL;
2802 goto bad;
2803 }
2804
2805 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2806 if (payload_sz < 0) {
2807 rc = -EINVAL;
2808 goto bad;
2809 }
2810 wqe.wr_id = wr->wr_id;
2811
2812 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2813
2814 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2815 if (!rc)
2816 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2817 bad:
2818 if (rc) {
2819 ibdev_err(&rdev->ibdev,
2820 "Post send failed opcode = %#x rc = %d",
2821 wr->opcode, rc);
2822 break;
2823 }
2824 wr = wr->next;
2825 }
2826 bnxt_qplib_post_send_db(&qp->qplib_qp);
2827 bnxt_ud_qp_hw_stall_workaround(qp);
2828 spin_unlock_irqrestore(&qp->sq_lock, flags);
2829 return rc;
2830 }
2831
2832 static void bnxt_re_legacy_set_uc_fence(struct bnxt_qplib_swqe *wqe)
2833 {
2834 /* Need unconditional fence for non-wire memory opcode
2835 * to work as expected.
2836 */
2837 if (wqe->type == BNXT_QPLIB_SWQE_TYPE_LOCAL_INV ||
2838 wqe->type == BNXT_QPLIB_SWQE_TYPE_FAST_REG_MR ||
2839 wqe->type == BNXT_QPLIB_SWQE_TYPE_REG_MR ||
2840 wqe->type == BNXT_QPLIB_SWQE_TYPE_BIND_MW)
2841 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2842 }
2843
2844 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2845 const struct ib_send_wr **bad_wr)
2846 {
2847 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2848 struct bnxt_qplib_swqe wqe;
2849 int rc = 0, payload_sz = 0;
2850 unsigned long flags;
2851
2852 spin_lock_irqsave(&qp->sq_lock, flags);
2853 while (wr) {
2854 /* House keeping */
2855 memset(&wqe, 0, sizeof(wqe));
2856
2857 /* Common */
2858 wqe.num_sge = wr->num_sge;
2859 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2860 ibdev_err(&qp->rdev->ibdev,
2861 "Limit exceeded for Send SGEs");
2862 rc = -EINVAL;
2863 goto bad;
2864 }
2865
2866 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2867 if (payload_sz < 0) {
2868 rc = -EINVAL;
2869 goto bad;
2870 }
2871 wqe.wr_id = wr->wr_id;
2872
2873 switch (wr->opcode) {
2874 case IB_WR_SEND:
2875 case IB_WR_SEND_WITH_IMM:
2876 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2877 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2878 payload_sz);
2879 if (rc)
2880 goto bad;
2881 wqe.rawqp1.lflags |=
2882 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2883 }
2884 switch (wr->send_flags) {
2885 case IB_SEND_IP_CSUM:
2886 wqe.rawqp1.lflags |=
2887 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2888 break;
2889 default:
2890 break;
2891 }
2892 fallthrough;
2893 case IB_WR_SEND_WITH_INV:
2894 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2895 break;
2896 case IB_WR_RDMA_WRITE:
2897 case IB_WR_RDMA_WRITE_WITH_IMM:
2898 case IB_WR_RDMA_READ:
2899 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2900 break;
2901 case IB_WR_ATOMIC_CMP_AND_SWP:
2902 case IB_WR_ATOMIC_FETCH_AND_ADD:
2903 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2904 break;
2905 case IB_WR_RDMA_READ_WITH_INV:
2906 ibdev_err(&qp->rdev->ibdev,
2907 "RDMA Read with Invalidate is not supported");
2908 rc = -EINVAL;
2909 goto bad;
2910 case IB_WR_LOCAL_INV:
2911 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2912 break;
2913 case IB_WR_REG_MR:
2914 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2915 break;
2916 default:
2917 /* Unsupported WRs */
2918 ibdev_err(&qp->rdev->ibdev,
2919 "WR (%#x) is not supported", wr->opcode);
2920 rc = -EINVAL;
2921 goto bad;
2922 }
2923 if (!rc) {
2924 if (!bnxt_qplib_is_chip_gen_p5_p7(qp->rdev->chip_ctx))
2925 bnxt_re_legacy_set_uc_fence(&wqe);
2926 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2927 }
2928 bad:
2929 if (rc) {
2930 ibdev_err(&qp->rdev->ibdev,
2931 "post_send failed op:%#x qps = %#x rc = %d\n",
2932 wr->opcode, qp->qplib_qp.state, rc);
2933 *bad_wr = wr;
2934 break;
2935 }
2936 wr = wr->next;
2937 }
2938 bnxt_qplib_post_send_db(&qp->qplib_qp);
2939 bnxt_ud_qp_hw_stall_workaround(qp);
2940 spin_unlock_irqrestore(&qp->sq_lock, flags);
2941
2942 return rc;
2943 }
2944
2945 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2946 struct bnxt_re_qp *qp,
2947 const struct ib_recv_wr *wr)
2948 {
2949 struct bnxt_qplib_swqe wqe;
2950 int rc = 0;
2951
2952 while (wr) {
2953 /* House keeping */
2954 memset(&wqe, 0, sizeof(wqe));
2955
2956 /* Common */
2957 wqe.num_sge = wr->num_sge;
2958 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2959 ibdev_err(&rdev->ibdev,
2960 "Limit exceeded for Receive SGEs");
2961 rc = -EINVAL;
2962 break;
2963 }
2964 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2965 wqe.wr_id = wr->wr_id;
2966 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2967
2968 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2969 if (rc)
2970 break;
2971
2972 wr = wr->next;
2973 }
2974 if (!rc)
2975 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2976 return rc;
2977 }
2978
2979 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2980 const struct ib_recv_wr **bad_wr)
2981 {
2982 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2983 struct bnxt_qplib_swqe wqe;
2984 int rc = 0, payload_sz = 0;
2985 unsigned long flags;
2986 u32 count = 0;
2987
2988 spin_lock_irqsave(&qp->rq_lock, flags);
2989 while (wr) {
2990 /* House keeping */
2991 memset(&wqe, 0, sizeof(wqe));
2992
2993 /* Common */
2994 wqe.num_sge = wr->num_sge;
2995 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2996 ibdev_err(&qp->rdev->ibdev,
2997 "Limit exceeded for Receive SGEs");
2998 rc = -EINVAL;
2999 *bad_wr = wr;
3000 break;
3001 }
3002
3003 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
3004 wr->num_sge);
3005 wqe.wr_id = wr->wr_id;
3006 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
3007
3008 if (ib_qp->qp_type == IB_QPT_GSI &&
3009 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
3010 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
3011 payload_sz);
3012 if (!rc)
3013 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
3014 if (rc) {
3015 *bad_wr = wr;
3016 break;
3017 }
3018
3019 /* Ring DB if the RQEs posted reaches a threshold value */
3020 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
3021 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3022 count = 0;
3023 }
3024
3025 wr = wr->next;
3026 }
3027
3028 if (count)
3029 bnxt_qplib_post_recv_db(&qp->qplib_qp);
3030
3031 spin_unlock_irqrestore(&qp->rq_lock, flags);
3032
3033 return rc;
3034 }
3035
3036 static struct bnxt_qplib_nq *bnxt_re_get_nq(struct bnxt_re_dev *rdev)
3037 {
3038 int min, indx;
3039
3040 mutex_lock(&rdev->nqr->load_lock);
3041 for (indx = 0, min = 0; indx < (rdev->nqr->num_msix - 1); indx++) {
3042 if (rdev->nqr->nq[min].load > rdev->nqr->nq[indx].load)
3043 min = indx;
3044 }
3045 rdev->nqr->nq[min].load++;
3046 mutex_unlock(&rdev->nqr->load_lock);
3047
3048 return &rdev->nqr->nq[min];
3049 }
3050
3051 static void bnxt_re_put_nq(struct bnxt_re_dev *rdev, struct bnxt_qplib_nq *nq)
3052 {
3053 mutex_lock(&rdev->nqr->load_lock);
3054 nq->load--;
3055 mutex_unlock(&rdev->nqr->load_lock);
3056 }
3057
3058 /* Completion Queues */
3059 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
3060 {
3061 struct bnxt_qplib_chip_ctx *cctx;
3062 struct bnxt_qplib_nq *nq;
3063 struct bnxt_re_dev *rdev;
3064 struct bnxt_re_cq *cq;
3065
3066 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3067 rdev = cq->rdev;
3068 nq = cq->qplib_cq.nq;
3069 cctx = rdev->chip_ctx;
3070
3071 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {
3072 free_page((unsigned long)cq->uctx_cq_page);
3073 hash_del(&cq->hash_entry);
3074 }
3075 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3076
3077 bnxt_re_put_nq(rdev, nq);
3078 ib_umem_release(cq->umem);
3079
3080 atomic_dec(&rdev->stats.res.cq_count);
3081 nq->budget--;
3082 kfree(cq->cql);
3083 return 0;
3084 }
3085
3086 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
3087 struct uverbs_attr_bundle *attrs)
3088 {
3089 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
3090 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
3091 struct ib_udata *udata = &attrs->driver_udata;
3092 struct bnxt_re_ucontext *uctx =
3093 rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3094 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3095 struct bnxt_qplib_chip_ctx *cctx;
3096 int cqe = attr->cqe;
3097 int rc, entries;
3098 u32 active_cqs;
3099
3100 if (attr->flags)
3101 return -EOPNOTSUPP;
3102
3103 /* Validate CQ fields */
3104 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3105 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
3106 return -EINVAL;
3107 }
3108
3109 cq->rdev = rdev;
3110 cctx = rdev->chip_ctx;
3111 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
3112
3113 entries = bnxt_re_init_depth(cqe + 1, uctx);
3114 if (entries > dev_attr->max_cq_wqes + 1)
3115 entries = dev_attr->max_cq_wqes + 1;
3116
3117 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3118 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3119 if (udata) {
3120 struct bnxt_re_cq_req req;
3121 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3122 rc = -EFAULT;
3123 goto fail;
3124 }
3125
3126 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3127 entries * sizeof(struct cq_base),
3128 IB_ACCESS_LOCAL_WRITE);
3129 if (IS_ERR(cq->umem)) {
3130 rc = PTR_ERR(cq->umem);
3131 goto fail;
3132 }
3133 cq->qplib_cq.sg_info.umem = cq->umem;
3134 cq->qplib_cq.dpi = &uctx->dpi;
3135 } else {
3136 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
3137 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
3138 GFP_KERNEL);
3139 if (!cq->cql) {
3140 rc = -ENOMEM;
3141 goto fail;
3142 }
3143
3144 cq->qplib_cq.dpi = &rdev->dpi_privileged;
3145 }
3146 cq->qplib_cq.max_wqe = entries;
3147 cq->qplib_cq.coalescing = &rdev->cq_coalescing;
3148 cq->qplib_cq.nq = bnxt_re_get_nq(rdev);
3149 cq->qplib_cq.cnq_hw_ring_id = cq->qplib_cq.nq->ring_id;
3150
3151 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
3152 if (rc) {
3153 ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
3154 goto fail;
3155 }
3156
3157 cq->ib_cq.cqe = entries;
3158 cq->cq_period = cq->qplib_cq.period;
3159
3160 active_cqs = atomic_inc_return(&rdev->stats.res.cq_count);
3161 if (active_cqs > rdev->stats.res.cq_watermark)
3162 rdev->stats.res.cq_watermark = active_cqs;
3163 spin_lock_init(&cq->cq_lock);
3164
3165 if (udata) {
3166 struct bnxt_re_cq_resp resp = {};
3167
3168 if (cctx->modes.toggle_bits & BNXT_QPLIB_CQ_TOGGLE_BIT) {
3169 hash_add(rdev->cq_hash, &cq->hash_entry, cq->qplib_cq.id);
3170 /* Allocate a page */
3171 cq->uctx_cq_page = (void *)get_zeroed_page(GFP_KERNEL);
3172 if (!cq->uctx_cq_page) {
3173 rc = -ENOMEM;
3174 goto c2fail;
3175 }
3176 resp.comp_mask |= BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT;
3177 }
3178 resp.cqid = cq->qplib_cq.id;
3179 resp.tail = cq->qplib_cq.hwq.cons;
3180 resp.phase = cq->qplib_cq.period;
3181 resp.rsvd = 0;
3182 rc = ib_copy_to_udata(udata, &resp, min(sizeof(resp), udata->outlen));
3183 if (rc) {
3184 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
3185 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
3186 goto free_mem;
3187 }
3188 }
3189
3190 return 0;
3191
3192 free_mem:
3193 free_page((unsigned long)cq->uctx_cq_page);
3194 c2fail:
3195 ib_umem_release(cq->umem);
3196 fail:
3197 kfree(cq->cql);
3198 return rc;
3199 }
3200
3201 static void bnxt_re_resize_cq_complete(struct bnxt_re_cq *cq)
3202 {
3203 struct bnxt_re_dev *rdev = cq->rdev;
3204
3205 bnxt_qplib_resize_cq_complete(&rdev->qplib_res, &cq->qplib_cq);
3206
3207 cq->qplib_cq.max_wqe = cq->resize_cqe;
3208 if (cq->resize_umem) {
3209 ib_umem_release(cq->umem);
3210 cq->umem = cq->resize_umem;
3211 cq->resize_umem = NULL;
3212 cq->resize_cqe = 0;
3213 }
3214 }
3215
3216 int bnxt_re_resize_cq(struct ib_cq *ibcq, int cqe, struct ib_udata *udata)
3217 {
3218 struct bnxt_qplib_sg_info sg_info = {};
3219 struct bnxt_qplib_dpi *orig_dpi = NULL;
3220 struct bnxt_qplib_dev_attr *dev_attr;
3221 struct bnxt_re_ucontext *uctx = NULL;
3222 struct bnxt_re_resize_cq_req req;
3223 struct bnxt_re_dev *rdev;
3224 struct bnxt_re_cq *cq;
3225 int rc, entries;
3226
3227 cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
3228 rdev = cq->rdev;
3229 dev_attr = &rdev->dev_attr;
3230 if (!ibcq->uobject) {
3231 ibdev_err(&rdev->ibdev, "Kernel CQ Resize not supported");
3232 return -EOPNOTSUPP;
3233 }
3234
3235 if (cq->resize_umem) {
3236 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - Busy",
3237 cq->qplib_cq.id);
3238 return -EBUSY;
3239 }
3240
3241 /* Check the requested cq depth out of supported depth */
3242 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
3243 ibdev_err(&rdev->ibdev, "Resize CQ %#x failed - out of range cqe %d",
3244 cq->qplib_cq.id, cqe);
3245 return -EINVAL;
3246 }
3247
3248 uctx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext, ib_uctx);
3249 entries = bnxt_re_init_depth(cqe + 1, uctx);
3250 if (entries > dev_attr->max_cq_wqes + 1)
3251 entries = dev_attr->max_cq_wqes + 1;
3252
3253 /* uverbs consumer */
3254 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
3255 rc = -EFAULT;
3256 goto fail;
3257 }
3258
3259 cq->resize_umem = ib_umem_get(&rdev->ibdev, req.cq_va,
3260 entries * sizeof(struct cq_base),
3261 IB_ACCESS_LOCAL_WRITE);
3262 if (IS_ERR(cq->resize_umem)) {
3263 rc = PTR_ERR(cq->resize_umem);
3264 cq->resize_umem = NULL;
3265 ibdev_err(&rdev->ibdev, "%s: ib_umem_get failed! rc = %d\n",
3266 __func__, rc);
3267 goto fail;
3268 }
3269 cq->resize_cqe = entries;
3270 memcpy(&sg_info, &cq->qplib_cq.sg_info, sizeof(sg_info));
3271 orig_dpi = cq->qplib_cq.dpi;
3272
3273 cq->qplib_cq.sg_info.umem = cq->resize_umem;
3274 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
3275 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
3276 cq->qplib_cq.dpi = &uctx->dpi;
3277
3278 rc = bnxt_qplib_resize_cq(&rdev->qplib_res, &cq->qplib_cq, entries);
3279 if (rc) {
3280 ibdev_err(&rdev->ibdev, "Resize HW CQ %#x failed!",
3281 cq->qplib_cq.id);
3282 goto fail;
3283 }
3284
3285 cq->ib_cq.cqe = cq->resize_cqe;
3286 atomic_inc(&rdev->stats.res.resize_count);
3287
3288 return 0;
3289
3290 fail:
3291 if (cq->resize_umem) {
3292 ib_umem_release(cq->resize_umem);
3293 cq->resize_umem = NULL;
3294 cq->resize_cqe = 0;
3295 memcpy(&cq->qplib_cq.sg_info, &sg_info, sizeof(sg_info));
3296 cq->qplib_cq.dpi = orig_dpi;
3297 }
3298 return rc;
3299 }
3300
3301 static u8 __req_to_ib_wc_status(u8 qstatus)
3302 {
3303 switch (qstatus) {
3304 case CQ_REQ_STATUS_OK:
3305 return IB_WC_SUCCESS;
3306 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
3307 return IB_WC_BAD_RESP_ERR;
3308 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
3309 return IB_WC_LOC_LEN_ERR;
3310 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
3311 return IB_WC_LOC_QP_OP_ERR;
3312 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
3313 return IB_WC_LOC_PROT_ERR;
3314 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
3315 return IB_WC_GENERAL_ERR;
3316 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
3317 return IB_WC_REM_INV_REQ_ERR;
3318 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
3319 return IB_WC_REM_ACCESS_ERR;
3320 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
3321 return IB_WC_REM_OP_ERR;
3322 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
3323 return IB_WC_RNR_RETRY_EXC_ERR;
3324 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
3325 return IB_WC_RETRY_EXC_ERR;
3326 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
3327 return IB_WC_WR_FLUSH_ERR;
3328 default:
3329 return IB_WC_GENERAL_ERR;
3330 }
3331 return 0;
3332 }
3333
3334 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
3335 {
3336 switch (qstatus) {
3337 case CQ_RES_RAWETH_QP1_STATUS_OK:
3338 return IB_WC_SUCCESS;
3339 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
3340 return IB_WC_LOC_ACCESS_ERR;
3341 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
3342 return IB_WC_LOC_LEN_ERR;
3343 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
3344 return IB_WC_LOC_PROT_ERR;
3345 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
3346 return IB_WC_LOC_QP_OP_ERR;
3347 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
3348 return IB_WC_GENERAL_ERR;
3349 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
3350 return IB_WC_WR_FLUSH_ERR;
3351 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
3352 return IB_WC_WR_FLUSH_ERR;
3353 default:
3354 return IB_WC_GENERAL_ERR;
3355 }
3356 }
3357
3358 static u8 __rc_to_ib_wc_status(u8 qstatus)
3359 {
3360 switch (qstatus) {
3361 case CQ_RES_RC_STATUS_OK:
3362 return IB_WC_SUCCESS;
3363 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
3364 return IB_WC_LOC_ACCESS_ERR;
3365 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
3366 return IB_WC_LOC_LEN_ERR;
3367 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
3368 return IB_WC_LOC_PROT_ERR;
3369 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
3370 return IB_WC_LOC_QP_OP_ERR;
3371 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
3372 return IB_WC_GENERAL_ERR;
3373 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
3374 return IB_WC_REM_INV_REQ_ERR;
3375 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
3376 return IB_WC_WR_FLUSH_ERR;
3377 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
3378 return IB_WC_WR_FLUSH_ERR;
3379 default:
3380 return IB_WC_GENERAL_ERR;
3381 }
3382 }
3383
3384 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3385 {
3386 switch (cqe->type) {
3387 case BNXT_QPLIB_SWQE_TYPE_SEND:
3388 wc->opcode = IB_WC_SEND;
3389 break;
3390 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3391 wc->opcode = IB_WC_SEND;
3392 wc->wc_flags |= IB_WC_WITH_IMM;
3393 break;
3394 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3395 wc->opcode = IB_WC_SEND;
3396 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3397 break;
3398 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3399 wc->opcode = IB_WC_RDMA_WRITE;
3400 break;
3401 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3402 wc->opcode = IB_WC_RDMA_WRITE;
3403 wc->wc_flags |= IB_WC_WITH_IMM;
3404 break;
3405 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3406 wc->opcode = IB_WC_RDMA_READ;
3407 break;
3408 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3409 wc->opcode = IB_WC_COMP_SWAP;
3410 break;
3411 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3412 wc->opcode = IB_WC_FETCH_ADD;
3413 break;
3414 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3415 wc->opcode = IB_WC_LOCAL_INV;
3416 break;
3417 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3418 wc->opcode = IB_WC_REG_MR;
3419 break;
3420 default:
3421 wc->opcode = IB_WC_SEND;
3422 break;
3423 }
3424
3425 wc->status = __req_to_ib_wc_status(cqe->status);
3426 }
3427
3428 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3429 u16 raweth_qp1_flags2)
3430 {
3431 bool is_ipv6 = false, is_ipv4 = false;
3432
3433 /* raweth_qp1_flags Bit 9-6 indicates itype */
3434 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3435 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3436 return -1;
3437
3438 if (raweth_qp1_flags2 &
3439 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3440 raweth_qp1_flags2 &
3441 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3442 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3443 (raweth_qp1_flags2 &
3444 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3445 (is_ipv6 = true) : (is_ipv4 = true);
3446 return ((is_ipv6) ?
3447 BNXT_RE_ROCEV2_IPV6_PACKET :
3448 BNXT_RE_ROCEV2_IPV4_PACKET);
3449 } else {
3450 return BNXT_RE_ROCE_V1_PACKET;
3451 }
3452 }
3453
3454 static int bnxt_re_to_ib_nw_type(int nw_type)
3455 {
3456 u8 nw_hdr_type = 0xFF;
3457
3458 switch (nw_type) {
3459 case BNXT_RE_ROCE_V1_PACKET:
3460 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3461 break;
3462 case BNXT_RE_ROCEV2_IPV4_PACKET:
3463 nw_hdr_type = RDMA_NETWORK_IPV4;
3464 break;
3465 case BNXT_RE_ROCEV2_IPV6_PACKET:
3466 nw_hdr_type = RDMA_NETWORK_IPV6;
3467 break;
3468 }
3469 return nw_hdr_type;
3470 }
3471
3472 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3473 void *rq_hdr_buf)
3474 {
3475 u8 *tmp_buf = NULL;
3476 struct ethhdr *eth_hdr;
3477 u16 eth_type;
3478 bool rc = false;
3479
3480 tmp_buf = (u8 *)rq_hdr_buf;
3481 /*
3482 * If dest mac is not same as I/F mac, this could be a
3483 * loopback address or multicast address, check whether
3484 * it is a loopback packet
3485 */
3486 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3487 tmp_buf += 4;
3488 /* Check the ether type */
3489 eth_hdr = (struct ethhdr *)tmp_buf;
3490 eth_type = ntohs(eth_hdr->h_proto);
3491 switch (eth_type) {
3492 case ETH_P_IBOE:
3493 rc = true;
3494 break;
3495 case ETH_P_IP:
3496 case ETH_P_IPV6: {
3497 u32 len;
3498 struct udphdr *udp_hdr;
3499
3500 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3501 sizeof(struct ipv6hdr));
3502 tmp_buf += sizeof(struct ethhdr) + len;
3503 udp_hdr = (struct udphdr *)tmp_buf;
3504 if (ntohs(udp_hdr->dest) ==
3505 ROCE_V2_UDP_DPORT)
3506 rc = true;
3507 break;
3508 }
3509 default:
3510 break;
3511 }
3512 }
3513
3514 return rc;
3515 }
3516
3517 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3518 struct bnxt_qplib_cqe *cqe)
3519 {
3520 struct bnxt_re_dev *rdev = gsi_qp->rdev;
3521 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3522 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3523 dma_addr_t shrq_hdr_buf_map;
3524 struct ib_sge s_sge[2] = {};
3525 struct ib_sge r_sge[2] = {};
3526 struct bnxt_re_ah *gsi_sah;
3527 struct ib_recv_wr rwr = {};
3528 dma_addr_t rq_hdr_buf_map;
3529 struct ib_ud_wr udwr = {};
3530 struct ib_send_wr *swr;
3531 u32 skip_bytes = 0;
3532 int pkt_type = 0;
3533 void *rq_hdr_buf;
3534 u32 offset = 0;
3535 u32 tbl_idx;
3536 int rc;
3537
3538 swr = &udwr.wr;
3539 tbl_idx = cqe->wr_id;
3540
3541 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3542 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3543 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3544 tbl_idx);
3545
3546 /* Shadow QP header buffer */
3547 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3548 tbl_idx);
3549 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3550
3551 /* Store this cqe */
3552 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3553 sqp_entry->qp1_qp = gsi_qp;
3554
3555 /* Find packet type from the cqe */
3556
3557 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3558 cqe->raweth_qp1_flags2);
3559 if (pkt_type < 0) {
3560 ibdev_err(&rdev->ibdev, "Invalid packet\n");
3561 return -EINVAL;
3562 }
3563
3564 /* Adjust the offset for the user buffer and post in the rq */
3565
3566 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3567 offset = 20;
3568
3569 /*
3570 * QP1 loopback packet has 4 bytes of internal header before
3571 * ether header. Skip these four bytes.
3572 */
3573 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3574 skip_bytes = 4;
3575
3576 /* First send SGE . Skip the ether header*/
3577 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3578 + skip_bytes;
3579 s_sge[0].lkey = 0xFFFFFFFF;
3580 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3581 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3582
3583 /* Second Send SGE */
3584 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3585 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3586 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3587 s_sge[1].addr += 8;
3588 s_sge[1].lkey = 0xFFFFFFFF;
3589 s_sge[1].length = 256;
3590
3591 /* First recv SGE */
3592
3593 r_sge[0].addr = shrq_hdr_buf_map;
3594 r_sge[0].lkey = 0xFFFFFFFF;
3595 r_sge[0].length = 40;
3596
3597 r_sge[1].addr = sqp_entry->sge.addr + offset;
3598 r_sge[1].lkey = sqp_entry->sge.lkey;
3599 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3600
3601 /* Create receive work request */
3602 rwr.num_sge = 2;
3603 rwr.sg_list = r_sge;
3604 rwr.wr_id = tbl_idx;
3605 rwr.next = NULL;
3606
3607 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3608 if (rc) {
3609 ibdev_err(&rdev->ibdev,
3610 "Failed to post Rx buffers to shadow QP");
3611 return -ENOMEM;
3612 }
3613
3614 swr->num_sge = 2;
3615 swr->sg_list = s_sge;
3616 swr->wr_id = tbl_idx;
3617 swr->opcode = IB_WR_SEND;
3618 swr->next = NULL;
3619 gsi_sah = rdev->gsi_ctx.gsi_sah;
3620 udwr.ah = &gsi_sah->ib_ah;
3621 udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3622 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3623
3624 /* post data received in the send queue */
3625 return bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3626 }
3627
3628 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3629 struct bnxt_qplib_cqe *cqe)
3630 {
3631 wc->opcode = IB_WC_RECV;
3632 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3633 wc->wc_flags |= IB_WC_GRH;
3634 }
3635
3636 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3637 u16 vlan_id)
3638 {
3639 /*
3640 * Check if the vlan is configured in the host. If not configured, it
3641 * can be a transparent VLAN. So dont report the vlan id.
3642 */
3643 if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3644 htons(ETH_P_8021Q), vlan_id))
3645 return false;
3646 return true;
3647 }
3648
3649 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3650 u16 *vid, u8 *sl)
3651 {
3652 bool ret = false;
3653 u32 metadata;
3654 u16 tpid;
3655
3656 metadata = orig_cqe->raweth_qp1_metadata;
3657 if (orig_cqe->raweth_qp1_flags2 &
3658 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3659 tpid = ((metadata &
3660 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3661 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3662 if (tpid == ETH_P_8021Q) {
3663 *vid = metadata &
3664 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3665 *sl = (metadata &
3666 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3667 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3668 ret = true;
3669 }
3670 }
3671
3672 return ret;
3673 }
3674
3675 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3676 struct bnxt_qplib_cqe *cqe)
3677 {
3678 wc->opcode = IB_WC_RECV;
3679 wc->status = __rc_to_ib_wc_status(cqe->status);
3680
3681 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3682 wc->wc_flags |= IB_WC_WITH_IMM;
3683 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3684 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3685 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3686 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3687 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3688 }
3689
3690 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3691 struct ib_wc *wc,
3692 struct bnxt_qplib_cqe *cqe)
3693 {
3694 struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3695 struct bnxt_re_qp *gsi_qp = NULL;
3696 struct bnxt_qplib_cqe *orig_cqe = NULL;
3697 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3698 int nw_type;
3699 u32 tbl_idx;
3700 u16 vlan_id;
3701 u8 sl;
3702
3703 tbl_idx = cqe->wr_id;
3704
3705 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3706 gsi_qp = sqp_entry->qp1_qp;
3707 orig_cqe = &sqp_entry->cqe;
3708
3709 wc->wr_id = sqp_entry->wrid;
3710 wc->byte_len = orig_cqe->length;
3711 wc->qp = &gsi_qp->ib_qp;
3712
3713 wc->ex.imm_data = cpu_to_be32(orig_cqe->immdata);
3714 wc->src_qp = orig_cqe->src_qp;
3715 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3716 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3717 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3718 wc->vlan_id = vlan_id;
3719 wc->sl = sl;
3720 wc->wc_flags |= IB_WC_WITH_VLAN;
3721 }
3722 }
3723 wc->port_num = 1;
3724 wc->vendor_err = orig_cqe->status;
3725
3726 wc->opcode = IB_WC_RECV;
3727 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3728 wc->wc_flags |= IB_WC_GRH;
3729
3730 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3731 orig_cqe->raweth_qp1_flags2);
3732 if (nw_type >= 0) {
3733 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3734 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3735 }
3736 }
3737
3738 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3739 struct ib_wc *wc,
3740 struct bnxt_qplib_cqe *cqe)
3741 {
3742 struct bnxt_re_dev *rdev;
3743 u16 vlan_id = 0;
3744 u8 nw_type;
3745
3746 rdev = qp->rdev;
3747 wc->opcode = IB_WC_RECV;
3748 wc->status = __rc_to_ib_wc_status(cqe->status);
3749
3750 if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3751 wc->wc_flags |= IB_WC_WITH_IMM;
3752 /* report only on GSI QP for Thor */
3753 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3754 wc->wc_flags |= IB_WC_GRH;
3755 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3756 wc->wc_flags |= IB_WC_WITH_SMAC;
3757 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3758 vlan_id = (cqe->cfa_meta & 0xFFF);
3759 }
3760 /* Mark only if vlan_id is non zero */
3761 if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3762 wc->vlan_id = vlan_id;
3763 wc->wc_flags |= IB_WC_WITH_VLAN;
3764 }
3765 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3766 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3767 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3768 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3769 }
3770
3771 }
3772
3773 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3774 {
3775 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3776 unsigned long flags;
3777 int rc;
3778
3779 spin_lock_irqsave(&qp->sq_lock, flags);
3780
3781 rc = bnxt_re_bind_fence_mw(lib_qp);
3782 if (!rc) {
3783 lib_qp->sq.phantom_wqe_cnt++;
3784 ibdev_dbg(&qp->rdev->ibdev,
3785 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3786 lib_qp->id, lib_qp->sq.hwq.prod,
3787 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3788 lib_qp->sq.phantom_wqe_cnt);
3789 }
3790
3791 spin_unlock_irqrestore(&qp->sq_lock, flags);
3792 return rc;
3793 }
3794
3795 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3796 {
3797 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3798 struct bnxt_re_qp *qp, *sh_qp;
3799 struct bnxt_qplib_cqe *cqe;
3800 int i, ncqe, budget;
3801 struct bnxt_qplib_q *sq;
3802 struct bnxt_qplib_qp *lib_qp;
3803 u32 tbl_idx;
3804 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3805 unsigned long flags;
3806
3807 /* User CQ; the only processing we do is to
3808 * complete any pending CQ resize operation.
3809 */
3810 if (cq->umem) {
3811 if (cq->resize_umem)
3812 bnxt_re_resize_cq_complete(cq);
3813 return 0;
3814 }
3815
3816 spin_lock_irqsave(&cq->cq_lock, flags);
3817 budget = min_t(u32, num_entries, cq->max_cql);
3818 num_entries = budget;
3819 if (!cq->cql) {
3820 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3821 goto exit;
3822 }
3823 cqe = &cq->cql[0];
3824 while (budget) {
3825 lib_qp = NULL;
3826 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3827 if (lib_qp) {
3828 sq = &lib_qp->sq;
3829 if (sq->send_phantom) {
3830 qp = container_of(lib_qp,
3831 struct bnxt_re_qp, qplib_qp);
3832 if (send_phantom_wqe(qp) == -ENOMEM)
3833 ibdev_err(&cq->rdev->ibdev,
3834 "Phantom failed! Scheduled to send again\n");
3835 else
3836 sq->send_phantom = false;
3837 }
3838 }
3839 if (ncqe < budget)
3840 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3841 cqe + ncqe,
3842 budget - ncqe);
3843
3844 if (!ncqe)
3845 break;
3846
3847 for (i = 0; i < ncqe; i++, cqe++) {
3848 /* Transcribe each qplib_wqe back to ib_wc */
3849 memset(wc, 0, sizeof(*wc));
3850
3851 wc->wr_id = cqe->wr_id;
3852 wc->byte_len = cqe->length;
3853 qp = container_of
3854 ((struct bnxt_qplib_qp *)
3855 (unsigned long)(cqe->qp_handle),
3856 struct bnxt_re_qp, qplib_qp);
3857 wc->qp = &qp->ib_qp;
3858 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3859 wc->ex.imm_data = cpu_to_be32(cqe->immdata);
3860 else
3861 wc->ex.invalidate_rkey = cqe->invrkey;
3862 wc->src_qp = cqe->src_qp;
3863 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3864 wc->port_num = 1;
3865 wc->vendor_err = cqe->status;
3866
3867 switch (cqe->opcode) {
3868 case CQ_BASE_CQE_TYPE_REQ:
3869 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3870 if (sh_qp &&
3871 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3872 /* Handle this completion with
3873 * the stored completion
3874 */
3875 memset(wc, 0, sizeof(*wc));
3876 continue;
3877 }
3878 bnxt_re_process_req_wc(wc, cqe);
3879 break;
3880 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3881 if (!cqe->status) {
3882 int rc = 0;
3883
3884 rc = bnxt_re_process_raw_qp_pkt_rx
3885 (qp, cqe);
3886 if (!rc) {
3887 memset(wc, 0, sizeof(*wc));
3888 continue;
3889 }
3890 cqe->status = -1;
3891 }
3892 /* Errors need not be looped back.
3893 * But change the wr_id to the one
3894 * stored in the table
3895 */
3896 tbl_idx = cqe->wr_id;
3897 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3898 wc->wr_id = sqp_entry->wrid;
3899 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3900 break;
3901 case CQ_BASE_CQE_TYPE_RES_RC:
3902 bnxt_re_process_res_rc_wc(wc, cqe);
3903 break;
3904 case CQ_BASE_CQE_TYPE_RES_UD:
3905 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3906 if (sh_qp &&
3907 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3908 /* Handle this completion with
3909 * the stored completion
3910 */
3911 if (cqe->status) {
3912 continue;
3913 } else {
3914 bnxt_re_process_res_shadow_qp_wc
3915 (qp, wc, cqe);
3916 break;
3917 }
3918 }
3919 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3920 break;
3921 default:
3922 ibdev_err(&cq->rdev->ibdev,
3923 "POLL CQ : type 0x%x not handled",
3924 cqe->opcode);
3925 continue;
3926 }
3927 wc++;
3928 budget--;
3929 }
3930 }
3931 exit:
3932 spin_unlock_irqrestore(&cq->cq_lock, flags);
3933 return num_entries - budget;
3934 }
3935
3936 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3937 enum ib_cq_notify_flags ib_cqn_flags)
3938 {
3939 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3940 int type = 0, rc = 0;
3941 unsigned long flags;
3942
3943 spin_lock_irqsave(&cq->cq_lock, flags);
3944 /* Trigger on the very next completion */
3945 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3946 type = DBC_DBC_TYPE_CQ_ARMALL;
3947 /* Trigger on the next solicited completion */
3948 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3949 type = DBC_DBC_TYPE_CQ_ARMSE;
3950
3951 /* Poll to see if there are missed events */
3952 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3953 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3954 rc = 1;
3955 goto exit;
3956 }
3957 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3958
3959 exit:
3960 spin_unlock_irqrestore(&cq->cq_lock, flags);
3961 return rc;
3962 }
3963
3964 /* Memory Regions */
3965 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3966 {
3967 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3968 struct bnxt_re_dev *rdev = pd->rdev;
3969 struct bnxt_re_mr *mr;
3970 u32 active_mrs;
3971 int rc;
3972
3973 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3974 if (!mr)
3975 return ERR_PTR(-ENOMEM);
3976
3977 mr->rdev = rdev;
3978 mr->qplib_mr.pd = &pd->qplib_pd;
3979 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
3980 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3981
3982 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING)
3983 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr);
3984
3985 /* Allocate and register 0 as the address */
3986 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3987 if (rc)
3988 goto fail;
3989
3990 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3991 mr->qplib_mr.total_size = -1; /* Infinte length */
3992 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0,
3993 PAGE_SIZE);
3994 if (rc)
3995 goto fail_mr;
3996
3997 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3998 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3999 IB_ACCESS_REMOTE_ATOMIC))
4000 mr->ib_mr.rkey = mr->ib_mr.lkey;
4001 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4002 if (active_mrs > rdev->stats.res.mr_watermark)
4003 rdev->stats.res.mr_watermark = active_mrs;
4004
4005 return &mr->ib_mr;
4006
4007 fail_mr:
4008 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4009 fail:
4010 kfree(mr);
4011 return ERR_PTR(rc);
4012 }
4013
4014 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
4015 {
4016 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4017 struct bnxt_re_dev *rdev = mr->rdev;
4018 int rc;
4019
4020 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4021 if (rc) {
4022 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
4023 return rc;
4024 }
4025
4026 if (mr->pages) {
4027 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
4028 &mr->qplib_frpl);
4029 kfree(mr->pages);
4030 mr->npages = 0;
4031 mr->pages = NULL;
4032 }
4033 ib_umem_release(mr->ib_umem);
4034
4035 kfree(mr);
4036 atomic_dec(&rdev->stats.res.mr_count);
4037 return rc;
4038 }
4039
4040 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
4041 {
4042 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4043
4044 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
4045 return -ENOMEM;
4046
4047 mr->pages[mr->npages++] = addr;
4048 return 0;
4049 }
4050
4051 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
4052 unsigned int *sg_offset)
4053 {
4054 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
4055
4056 mr->npages = 0;
4057 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
4058 }
4059
4060 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
4061 u32 max_num_sg)
4062 {
4063 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4064 struct bnxt_re_dev *rdev = pd->rdev;
4065 struct bnxt_re_mr *mr = NULL;
4066 u32 active_mrs;
4067 int rc;
4068
4069 if (type != IB_MR_TYPE_MEM_REG) {
4070 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
4071 return ERR_PTR(-EINVAL);
4072 }
4073 if (max_num_sg > MAX_PBL_LVL_1_PGS)
4074 return ERR_PTR(-EINVAL);
4075
4076 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
4077 if (!mr)
4078 return ERR_PTR(-ENOMEM);
4079
4080 mr->rdev = rdev;
4081 mr->qplib_mr.pd = &pd->qplib_pd;
4082 mr->qplib_mr.access_flags = BNXT_QPLIB_FR_PMR;
4083 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
4084
4085 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4086 if (rc)
4087 goto bail;
4088
4089 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4090 mr->ib_mr.rkey = mr->ib_mr.lkey;
4091
4092 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
4093 if (!mr->pages) {
4094 rc = -ENOMEM;
4095 goto fail;
4096 }
4097 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
4098 &mr->qplib_frpl, max_num_sg);
4099 if (rc) {
4100 ibdev_err(&rdev->ibdev,
4101 "Failed to allocate HW FR page list");
4102 goto fail_mr;
4103 }
4104
4105 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4106 if (active_mrs > rdev->stats.res.mr_watermark)
4107 rdev->stats.res.mr_watermark = active_mrs;
4108 return &mr->ib_mr;
4109
4110 fail_mr:
4111 kfree(mr->pages);
4112 fail:
4113 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4114 bail:
4115 kfree(mr);
4116 return ERR_PTR(rc);
4117 }
4118
4119 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
4120 struct ib_udata *udata)
4121 {
4122 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4123 struct bnxt_re_dev *rdev = pd->rdev;
4124 struct bnxt_re_mw *mw;
4125 u32 active_mws;
4126 int rc;
4127
4128 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
4129 if (!mw)
4130 return ERR_PTR(-ENOMEM);
4131 mw->rdev = rdev;
4132 mw->qplib_mw.pd = &pd->qplib_pd;
4133
4134 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
4135 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
4136 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
4137 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
4138 if (rc) {
4139 ibdev_err(&rdev->ibdev, "Allocate MW failed!");
4140 goto fail;
4141 }
4142 mw->ib_mw.rkey = mw->qplib_mw.rkey;
4143
4144 active_mws = atomic_inc_return(&rdev->stats.res.mw_count);
4145 if (active_mws > rdev->stats.res.mw_watermark)
4146 rdev->stats.res.mw_watermark = active_mws;
4147 return &mw->ib_mw;
4148
4149 fail:
4150 kfree(mw);
4151 return ERR_PTR(rc);
4152 }
4153
4154 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
4155 {
4156 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
4157 struct bnxt_re_dev *rdev = mw->rdev;
4158 int rc;
4159
4160 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
4161 if (rc) {
4162 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
4163 return rc;
4164 }
4165
4166 kfree(mw);
4167 atomic_dec(&rdev->stats.res.mw_count);
4168 return rc;
4169 }
4170
4171 static struct ib_mr *__bnxt_re_user_reg_mr(struct ib_pd *ib_pd, u64 length, u64 virt_addr,
4172 int mr_access_flags, struct ib_umem *umem)
4173 {
4174 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4175 struct bnxt_re_dev *rdev = pd->rdev;
4176 unsigned long page_size;
4177 struct bnxt_re_mr *mr;
4178 int umem_pgs, rc;
4179 u32 active_mrs;
4180
4181 if (length > BNXT_RE_MAX_MR_SIZE) {
4182 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
4183 length, BNXT_RE_MAX_MR_SIZE);
4184 return ERR_PTR(-ENOMEM);
4185 }
4186
4187 page_size = ib_umem_find_best_pgsz(umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr);
4188 if (!page_size) {
4189 ibdev_err(&rdev->ibdev, "umem page size unsupported!");
4190 return ERR_PTR(-EINVAL);
4191 }
4192
4193 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
4194 if (!mr)
4195 return ERR_PTR(-ENOMEM);
4196
4197 mr->rdev = rdev;
4198 mr->qplib_mr.pd = &pd->qplib_pd;
4199 mr->qplib_mr.access_flags = __from_ib_access_flags(mr_access_flags);
4200 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
4201
4202 if (!_is_alloc_mr_unified(rdev->dev_attr.dev_cap_flags)) {
4203 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
4204 if (rc) {
4205 ibdev_err(&rdev->ibdev, "Failed to allocate MR rc = %d", rc);
4206 rc = -EIO;
4207 goto free_mr;
4208 }
4209 /* The fixed portion of the rkey is the same as the lkey */
4210 mr->ib_mr.rkey = mr->qplib_mr.rkey;
4211 } else {
4212 mr->qplib_mr.flags = CMDQ_REGISTER_MR_FLAGS_ALLOC_MR;
4213 }
4214 mr->ib_umem = umem;
4215 mr->qplib_mr.va = virt_addr;
4216 mr->qplib_mr.total_size = length;
4217
4218 if (mr_access_flags & IB_ACCESS_RELAXED_ORDERING)
4219 bnxt_re_check_and_set_relaxed_ordering(rdev, &mr->qplib_mr);
4220
4221 umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
4222 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem,
4223 umem_pgs, page_size);
4224 if (rc) {
4225 ibdev_err(&rdev->ibdev, "Failed to register user MR - rc = %d\n", rc);
4226 rc = -EIO;
4227 goto free_mrw;
4228 }
4229
4230 mr->ib_mr.lkey = mr->qplib_mr.lkey;
4231 mr->ib_mr.rkey = mr->qplib_mr.lkey;
4232 active_mrs = atomic_inc_return(&rdev->stats.res.mr_count);
4233 if (active_mrs > rdev->stats.res.mr_watermark)
4234 rdev->stats.res.mr_watermark = active_mrs;
4235
4236 return &mr->ib_mr;
4237
4238 free_mrw:
4239 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
4240 free_mr:
4241 kfree(mr);
4242 return ERR_PTR(rc);
4243 }
4244
4245 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
4246 u64 virt_addr, int mr_access_flags,
4247 struct ib_udata *udata)
4248 {
4249 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4250 struct bnxt_re_dev *rdev = pd->rdev;
4251 struct ib_umem *umem;
4252 struct ib_mr *ib_mr;
4253
4254 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
4255 if (IS_ERR(umem))
4256 return ERR_CAST(umem);
4257
4258 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4259 if (IS_ERR(ib_mr))
4260 ib_umem_release(umem);
4261 return ib_mr;
4262 }
4263
4264 struct ib_mr *bnxt_re_reg_user_mr_dmabuf(struct ib_pd *ib_pd, u64 start,
4265 u64 length, u64 virt_addr, int fd,
4266 int mr_access_flags,
4267 struct uverbs_attr_bundle *attrs)
4268 {
4269 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
4270 struct bnxt_re_dev *rdev = pd->rdev;
4271 struct ib_umem_dmabuf *umem_dmabuf;
4272 struct ib_umem *umem;
4273 struct ib_mr *ib_mr;
4274
4275 umem_dmabuf = ib_umem_dmabuf_get_pinned(&rdev->ibdev, start, length,
4276 fd, mr_access_flags);
4277 if (IS_ERR(umem_dmabuf))
4278 return ERR_CAST(umem_dmabuf);
4279
4280 umem = &umem_dmabuf->umem;
4281
4282 ib_mr = __bnxt_re_user_reg_mr(ib_pd, length, virt_addr, mr_access_flags, umem);
4283 if (IS_ERR(ib_mr))
4284 ib_umem_release(umem);
4285 return ib_mr;
4286 }
4287
4288 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
4289 {
4290 struct ib_device *ibdev = ctx->device;
4291 struct bnxt_re_ucontext *uctx =
4292 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
4293 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
4294 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
4295 struct bnxt_re_user_mmap_entry *entry;
4296 struct bnxt_re_uctx_resp resp = {};
4297 struct bnxt_re_uctx_req ureq = {};
4298 u32 chip_met_rev_num = 0;
4299 int rc;
4300
4301 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
4302
4303 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
4304 ibdev_dbg(ibdev, " is different from the device %d ",
4305 BNXT_RE_ABI_VERSION);
4306 return -EPERM;
4307 }
4308
4309 uctx->rdev = rdev;
4310
4311 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
4312 if (!uctx->shpg) {
4313 rc = -ENOMEM;
4314 goto fail;
4315 }
4316 spin_lock_init(&uctx->sh_lock);
4317
4318 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
4319 chip_met_rev_num = rdev->chip_ctx->chip_num;
4320 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
4321 BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
4322 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
4323 BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
4324 resp.chip_id0 = chip_met_rev_num;
4325 /*Temp, Use xa_alloc instead */
4326 resp.dev_id = rdev->en_dev->pdev->devfn;
4327 resp.max_qp = rdev->qplib_ctx.qpc_count;
4328 resp.pg_size = PAGE_SIZE;
4329 resp.cqe_sz = sizeof(struct cq_base);
4330 resp.max_cqd = dev_attr->max_cq_wqes;
4331
4332 if (rdev->chip_ctx->modes.db_push)
4333 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_WC_DPI_ENABLED;
4334
4335 entry = bnxt_re_mmap_entry_insert(uctx, 0, BNXT_RE_MMAP_SH_PAGE, NULL);
4336 if (!entry) {
4337 rc = -ENOMEM;
4338 goto cfail;
4339 }
4340 uctx->shpage_mmap = &entry->rdma_entry;
4341 if (rdev->pacing.dbr_pacing)
4342 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_DBR_PACING_ENABLED;
4343
4344 if (_is_host_msn_table(rdev->qplib_res.dattr->dev_cap_flags2))
4345 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_MSN_TABLE_ENABLED;
4346
4347 if (udata->inlen >= sizeof(ureq)) {
4348 rc = ib_copy_from_udata(&ureq, udata, min(udata->inlen, sizeof(ureq)));
4349 if (rc)
4350 goto cfail;
4351 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT) {
4352 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_POW2_DISABLED;
4353 uctx->cmask |= BNXT_RE_UCNTX_CAP_POW2_DISABLED;
4354 }
4355 if (ureq.comp_mask & BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT) {
4356 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE;
4357 resp.mode = rdev->chip_ctx->modes.wqe_mode;
4358 if (resp.mode == BNXT_QPLIB_WQE_MODE_VARIABLE)
4359 uctx->cmask |= BNXT_RE_UCNTX_CAP_VAR_WQE_ENABLED;
4360 }
4361 }
4362
4363 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
4364 if (rc) {
4365 ibdev_err(ibdev, "Failed to copy user context");
4366 rc = -EFAULT;
4367 goto cfail;
4368 }
4369
4370 return 0;
4371 cfail:
4372 free_page((unsigned long)uctx->shpg);
4373 uctx->shpg = NULL;
4374 fail:
4375 return rc;
4376 }
4377
4378 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
4379 {
4380 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4381 struct bnxt_re_ucontext,
4382 ib_uctx);
4383
4384 struct bnxt_re_dev *rdev = uctx->rdev;
4385
4386 rdma_user_mmap_entry_remove(uctx->shpage_mmap);
4387 uctx->shpage_mmap = NULL;
4388 if (uctx->shpg)
4389 free_page((unsigned long)uctx->shpg);
4390
4391 if (uctx->dpi.dbr) {
4392 /* Free DPI only if this is the first PD allocated by the
4393 * application and mark the context dpi as NULL
4394 */
4395 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->dpi);
4396 uctx->dpi.dbr = NULL;
4397 }
4398 }
4399
4400 static struct bnxt_re_cq *bnxt_re_search_for_cq(struct bnxt_re_dev *rdev, u32 cq_id)
4401 {
4402 struct bnxt_re_cq *cq = NULL, *tmp_cq;
4403
4404 hash_for_each_possible(rdev->cq_hash, tmp_cq, hash_entry, cq_id) {
4405 if (tmp_cq->qplib_cq.id == cq_id) {
4406 cq = tmp_cq;
4407 break;
4408 }
4409 }
4410 return cq;
4411 }
4412
4413 static struct bnxt_re_srq *bnxt_re_search_for_srq(struct bnxt_re_dev *rdev, u32 srq_id)
4414 {
4415 struct bnxt_re_srq *srq = NULL, *tmp_srq;
4416
4417 hash_for_each_possible(rdev->srq_hash, tmp_srq, hash_entry, srq_id) {
4418 if (tmp_srq->qplib_srq.id == srq_id) {
4419 srq = tmp_srq;
4420 break;
4421 }
4422 }
4423 return srq;
4424 }
4425
4426 /* Helper function to mmap the virtual memory from user app */
4427 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
4428 {
4429 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
4430 struct bnxt_re_ucontext,
4431 ib_uctx);
4432 struct bnxt_re_user_mmap_entry *bnxt_entry;
4433 struct rdma_user_mmap_entry *rdma_entry;
4434 int ret = 0;
4435 u64 pfn;
4436
4437 rdma_entry = rdma_user_mmap_entry_get(&uctx->ib_uctx, vma);
4438 if (!rdma_entry)
4439 return -EINVAL;
4440
4441 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4442 rdma_entry);
4443
4444 switch (bnxt_entry->mmap_flag) {
4445 case BNXT_RE_MMAP_WC_DB:
4446 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4447 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4448 pgprot_writecombine(vma->vm_page_prot),
4449 rdma_entry);
4450 break;
4451 case BNXT_RE_MMAP_UC_DB:
4452 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4453 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4454 pgprot_noncached(vma->vm_page_prot),
4455 rdma_entry);
4456 break;
4457 case BNXT_RE_MMAP_SH_PAGE:
4458 ret = vm_insert_page(vma, vma->vm_start, virt_to_page(uctx->shpg));
4459 break;
4460 case BNXT_RE_MMAP_DBR_BAR:
4461 pfn = bnxt_entry->mem_offset >> PAGE_SHIFT;
4462 ret = rdma_user_mmap_io(ib_uctx, vma, pfn, PAGE_SIZE,
4463 pgprot_noncached(vma->vm_page_prot),
4464 rdma_entry);
4465 break;
4466 case BNXT_RE_MMAP_DBR_PAGE:
4467 case BNXT_RE_MMAP_TOGGLE_PAGE:
4468 /* Driver doesn't expect write access for user space */
4469 if (vma->vm_flags & VM_WRITE)
4470 return -EFAULT;
4471 ret = vm_insert_page(vma, vma->vm_start,
4472 virt_to_page((void *)bnxt_entry->mem_offset));
4473 break;
4474 default:
4475 ret = -EINVAL;
4476 break;
4477 }
4478
4479 rdma_user_mmap_entry_put(rdma_entry);
4480 return ret;
4481 }
4482
4483 void bnxt_re_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
4484 {
4485 struct bnxt_re_user_mmap_entry *bnxt_entry;
4486
4487 bnxt_entry = container_of(rdma_entry, struct bnxt_re_user_mmap_entry,
4488 rdma_entry);
4489
4490 kfree(bnxt_entry);
4491 }
4492
4493 static int UVERBS_HANDLER(BNXT_RE_METHOD_NOTIFY_DRV)(struct uverbs_attr_bundle *attrs)
4494 {
4495 struct bnxt_re_ucontext *uctx;
4496
4497 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4498 bnxt_re_pacing_alert(uctx->rdev);
4499 return 0;
4500 }
4501
4502 static int UVERBS_HANDLER(BNXT_RE_METHOD_ALLOC_PAGE)(struct uverbs_attr_bundle *attrs)
4503 {
4504 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4505 enum bnxt_re_alloc_page_type alloc_type;
4506 struct bnxt_re_user_mmap_entry *entry;
4507 enum bnxt_re_mmap_flag mmap_flag;
4508 struct bnxt_qplib_chip_ctx *cctx;
4509 struct bnxt_re_ucontext *uctx;
4510 struct bnxt_re_dev *rdev;
4511 u64 mmap_offset;
4512 u32 length;
4513 u32 dpi;
4514 u64 addr;
4515 int err;
4516
4517 uctx = container_of(ib_uverbs_get_ucontext(attrs), struct bnxt_re_ucontext, ib_uctx);
4518 if (IS_ERR(uctx))
4519 return PTR_ERR(uctx);
4520
4521 err = uverbs_get_const(&alloc_type, attrs, BNXT_RE_ALLOC_PAGE_TYPE);
4522 if (err)
4523 return err;
4524
4525 rdev = uctx->rdev;
4526 cctx = rdev->chip_ctx;
4527
4528 switch (alloc_type) {
4529 case BNXT_RE_ALLOC_WC_PAGE:
4530 if (cctx->modes.db_push) {
4531 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res, &uctx->wcdpi,
4532 uctx, BNXT_QPLIB_DPI_TYPE_WC))
4533 return -ENOMEM;
4534 length = PAGE_SIZE;
4535 dpi = uctx->wcdpi.dpi;
4536 addr = (u64)uctx->wcdpi.umdbr;
4537 mmap_flag = BNXT_RE_MMAP_WC_DB;
4538 } else {
4539 return -EINVAL;
4540 }
4541
4542 break;
4543 case BNXT_RE_ALLOC_DBR_BAR_PAGE:
4544 length = PAGE_SIZE;
4545 addr = (u64)rdev->pacing.dbr_bar_addr;
4546 mmap_flag = BNXT_RE_MMAP_DBR_BAR;
4547 break;
4548
4549 case BNXT_RE_ALLOC_DBR_PAGE:
4550 length = PAGE_SIZE;
4551 addr = (u64)rdev->pacing.dbr_page;
4552 mmap_flag = BNXT_RE_MMAP_DBR_PAGE;
4553 break;
4554
4555 default:
4556 return -EOPNOTSUPP;
4557 }
4558
4559 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mmap_offset);
4560 if (!entry)
4561 return -ENOMEM;
4562
4563 uobj->object = entry;
4564 uverbs_finalize_uobj_create(attrs, BNXT_RE_ALLOC_PAGE_HANDLE);
4565 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4566 &mmap_offset, sizeof(mmap_offset));
4567 if (err)
4568 return err;
4569
4570 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4571 &length, sizeof(length));
4572 if (err)
4573 return err;
4574
4575 err = uverbs_copy_to(attrs, BNXT_RE_ALLOC_PAGE_DPI,
4576 &dpi, sizeof(length));
4577 if (err)
4578 return err;
4579
4580 return 0;
4581 }
4582
4583 static int alloc_page_obj_cleanup(struct ib_uobject *uobject,
4584 enum rdma_remove_reason why,
4585 struct uverbs_attr_bundle *attrs)
4586 {
4587 struct bnxt_re_user_mmap_entry *entry = uobject->object;
4588 struct bnxt_re_ucontext *uctx = entry->uctx;
4589
4590 switch (entry->mmap_flag) {
4591 case BNXT_RE_MMAP_WC_DB:
4592 if (uctx && uctx->wcdpi.dbr) {
4593 struct bnxt_re_dev *rdev = uctx->rdev;
4594
4595 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, &uctx->wcdpi);
4596 uctx->wcdpi.dbr = NULL;
4597 }
4598 break;
4599 case BNXT_RE_MMAP_DBR_BAR:
4600 case BNXT_RE_MMAP_DBR_PAGE:
4601 break;
4602 default:
4603 goto exit;
4604 }
4605 rdma_user_mmap_entry_remove(&entry->rdma_entry);
4606 exit:
4607 return 0;
4608 }
4609
4610 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_ALLOC_PAGE,
4611 UVERBS_ATTR_IDR(BNXT_RE_ALLOC_PAGE_HANDLE,
4612 BNXT_RE_OBJECT_ALLOC_PAGE,
4613 UVERBS_ACCESS_NEW,
4614 UA_MANDATORY),
4615 UVERBS_ATTR_CONST_IN(BNXT_RE_ALLOC_PAGE_TYPE,
4616 enum bnxt_re_alloc_page_type,
4617 UA_MANDATORY),
4618 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_OFFSET,
4619 UVERBS_ATTR_TYPE(u64),
4620 UA_MANDATORY),
4621 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_MMAP_LENGTH,
4622 UVERBS_ATTR_TYPE(u32),
4623 UA_MANDATORY),
4624 UVERBS_ATTR_PTR_OUT(BNXT_RE_ALLOC_PAGE_DPI,
4625 UVERBS_ATTR_TYPE(u32),
4626 UA_MANDATORY));
4627
4628 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_DESTROY_PAGE,
4629 UVERBS_ATTR_IDR(BNXT_RE_DESTROY_PAGE_HANDLE,
4630 BNXT_RE_OBJECT_ALLOC_PAGE,
4631 UVERBS_ACCESS_DESTROY,
4632 UA_MANDATORY));
4633
4634 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_ALLOC_PAGE,
4635 UVERBS_TYPE_ALLOC_IDR(alloc_page_obj_cleanup),
4636 &UVERBS_METHOD(BNXT_RE_METHOD_ALLOC_PAGE),
4637 &UVERBS_METHOD(BNXT_RE_METHOD_DESTROY_PAGE));
4638
4639 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_NOTIFY_DRV);
4640
4641 DECLARE_UVERBS_GLOBAL_METHODS(BNXT_RE_OBJECT_NOTIFY_DRV,
4642 &UVERBS_METHOD(BNXT_RE_METHOD_NOTIFY_DRV));
4643
4644 /* Toggle MEM */
4645 static int UVERBS_HANDLER(BNXT_RE_METHOD_GET_TOGGLE_MEM)(struct uverbs_attr_bundle *attrs)
4646 {
4647 struct ib_uobject *uobj = uverbs_attr_get_uobject(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);
4648 enum bnxt_re_mmap_flag mmap_flag = BNXT_RE_MMAP_TOGGLE_PAGE;
4649 enum bnxt_re_get_toggle_mem_type res_type;
4650 struct bnxt_re_user_mmap_entry *entry;
4651 struct bnxt_re_ucontext *uctx;
4652 struct ib_ucontext *ib_uctx;
4653 struct bnxt_re_dev *rdev;
4654 struct bnxt_re_srq *srq;
4655 u32 length = PAGE_SIZE;
4656 struct bnxt_re_cq *cq;
4657 u64 mem_offset;
4658 u32 offset = 0;
4659 u64 addr = 0;
4660 u32 res_id;
4661 int err;
4662
4663 ib_uctx = ib_uverbs_get_ucontext(attrs);
4664 if (IS_ERR(ib_uctx))
4665 return PTR_ERR(ib_uctx);
4666
4667 err = uverbs_get_const(&res_type, attrs, BNXT_RE_TOGGLE_MEM_TYPE);
4668 if (err)
4669 return err;
4670
4671 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
4672 rdev = uctx->rdev;
4673 err = uverbs_copy_from(&res_id, attrs, BNXT_RE_TOGGLE_MEM_RES_ID);
4674 if (err)
4675 return err;
4676
4677 switch (res_type) {
4678 case BNXT_RE_CQ_TOGGLE_MEM:
4679 cq = bnxt_re_search_for_cq(rdev, res_id);
4680 if (!cq)
4681 return -EINVAL;
4682
4683 addr = (u64)cq->uctx_cq_page;
4684 break;
4685 case BNXT_RE_SRQ_TOGGLE_MEM:
4686 srq = bnxt_re_search_for_srq(rdev, res_id);
4687 if (!srq)
4688 return -EINVAL;
4689
4690 addr = (u64)srq->uctx_srq_page;
4691 break;
4692
4693 default:
4694 return -EOPNOTSUPP;
4695 }
4696
4697 entry = bnxt_re_mmap_entry_insert(uctx, addr, mmap_flag, &mem_offset);
4698 if (!entry)
4699 return -ENOMEM;
4700
4701 uobj->object = entry;
4702 uverbs_finalize_uobj_create(attrs, BNXT_RE_TOGGLE_MEM_HANDLE);
4703 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
4704 &mem_offset, sizeof(mem_offset));
4705 if (err)
4706 return err;
4707
4708 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
4709 &length, sizeof(length));
4710 if (err)
4711 return err;
4712
4713 err = uverbs_copy_to(attrs, BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
4714 &offset, sizeof(length));
4715 if (err)
4716 return err;
4717
4718 return 0;
4719 }
4720
4721 static int get_toggle_mem_obj_cleanup(struct ib_uobject *uobject,
4722 enum rdma_remove_reason why,
4723 struct uverbs_attr_bundle *attrs)
4724 {
4725 struct bnxt_re_user_mmap_entry *entry = uobject->object;
4726
4727 rdma_user_mmap_entry_remove(&entry->rdma_entry);
4728 return 0;
4729 }
4730
4731 DECLARE_UVERBS_NAMED_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM,
4732 UVERBS_ATTR_IDR(BNXT_RE_TOGGLE_MEM_HANDLE,
4733 BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4734 UVERBS_ACCESS_NEW,
4735 UA_MANDATORY),
4736 UVERBS_ATTR_CONST_IN(BNXT_RE_TOGGLE_MEM_TYPE,
4737 enum bnxt_re_get_toggle_mem_type,
4738 UA_MANDATORY),
4739 UVERBS_ATTR_PTR_IN(BNXT_RE_TOGGLE_MEM_RES_ID,
4740 UVERBS_ATTR_TYPE(u32),
4741 UA_MANDATORY),
4742 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
4743 UVERBS_ATTR_TYPE(u64),
4744 UA_MANDATORY),
4745 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
4746 UVERBS_ATTR_TYPE(u32),
4747 UA_MANDATORY),
4748 UVERBS_ATTR_PTR_OUT(BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
4749 UVERBS_ATTR_TYPE(u32),
4750 UA_MANDATORY));
4751
4752 DECLARE_UVERBS_NAMED_METHOD_DESTROY(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,
4753 UVERBS_ATTR_IDR(BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE,
4754 BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4755 UVERBS_ACCESS_DESTROY,
4756 UA_MANDATORY));
4757
4758 DECLARE_UVERBS_NAMED_OBJECT(BNXT_RE_OBJECT_GET_TOGGLE_MEM,
4759 UVERBS_TYPE_ALLOC_IDR(get_toggle_mem_obj_cleanup),
4760 &UVERBS_METHOD(BNXT_RE_METHOD_GET_TOGGLE_MEM),
4761 &UVERBS_METHOD(BNXT_RE_METHOD_RELEASE_TOGGLE_MEM));
4762
4763 const struct uapi_definition bnxt_re_uapi_defs[] = {
4764 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_ALLOC_PAGE),
4765 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_NOTIFY_DRV),
4766 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(BNXT_RE_OBJECT_GET_TOGGLE_MEM),
4767 {}
4768 };
Kernel DRM miscellaneous fixes and cross-tree changes