drivers/infiniband/hw/hns/hns_roce_common.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_COMMON_H
  34 #define _HNS_ROCE_COMMON_H
  35 #include <linux/bitfield.h>
  36
  37 #define roce_write(dev, reg, val)       writel((val), (dev)->reg_base + (reg))
  38 #define roce_read(dev, reg)             readl((dev)->reg_base + (reg))
  39 #define roce_raw_write(value, addr) \
  40         __raw_writel((__force u32)cpu_to_le32(value), (addr))
  41
  42 #define roce_get_field(origin, mask, shift)                                    \
  43         ((le32_to_cpu(origin) & (mask)) >> (u32)(shift))
  44
  45 #define roce_get_bit(origin, shift) \
  46         roce_get_field((origin), (1ul << (shift)), (shift))
  47
  48 #define roce_set_field(origin, mask, shift, val)                               \
  49         do {                                                                   \
  50                 (origin) &= ~cpu_to_le32(mask);                                \
  51                 (origin) |=                                                    \
  52                         cpu_to_le32(((u32)(val) << (u32)(shift)) & (mask));    \
  53         } while (0)
  54
  55 #define roce_set_bit(origin, shift, val)                                       \
  56         roce_set_field((origin), (1ul << (shift)), (shift), (val))
  57
  58 #define FIELD_LOC(field_type, field_h, field_l) field_type, field_h, field_l
  59
  60 #define _hr_reg_enable(ptr, field_type, field_h, field_l)                      \
  61         ({                                                                     \
  62                 const field_type *_ptr = ptr;                                  \
  63                 *((__le32 *)_ptr + (field_h) / 32) |= cpu_to_le32(             \
  64                         BIT((field_l) % 32) +                                  \
  65                         BUILD_BUG_ON_ZERO((field_h) != (field_l)));            \
  66         })
  67
  68 #define hr_reg_enable(ptr, field) _hr_reg_enable(ptr, field)
  69
  70 #define _hr_reg_clear(ptr, field_type, field_h, field_l)                       \
  71         ({                                                                     \
  72                 const field_type *_ptr = ptr;                                  \
  73                 BUILD_BUG_ON(((field_h) / 32) != ((field_l) / 32));            \
  74                 *((__le32 *)_ptr + (field_h) / 32) &=                          \
  75                         ~cpu_to_le32(GENMASK((field_h) % 32, (field_l) % 32)); \
  76         })
  77
  78 #define hr_reg_clear(ptr, field) _hr_reg_clear(ptr, field)
  79
  80 #define _hr_reg_write_bool(ptr, field_type, field_h, field_l, val)             \
  81         ({                                                                     \
  82                 (val) ? _hr_reg_enable(ptr, field_type, field_h, field_l) :    \
  83                         _hr_reg_clear(ptr, field_type, field_h, field_l);      \
  84         })
  85
  86 #define hr_reg_write_bool(ptr, field, val) _hr_reg_write_bool(ptr, field, val)
  87
  88 #define _hr_reg_write(ptr, field_type, field_h, field_l, val)                  \
  89         ({                                                                     \
  90                 _hr_reg_clear(ptr, field_type, field_h, field_l);              \
  91                 *((__le32 *)ptr + (field_h) / 32) |= cpu_to_le32(FIELD_PREP(   \
  92                         GENMASK((field_h) % 32, (field_l) % 32), val));        \
  93         })
  94
  95 #define hr_reg_write(ptr, field, val) _hr_reg_write(ptr, field, val)
  96
  97 #define _hr_reg_read(ptr, field_type, field_h, field_l)                        \
  98         ({                                                                     \
  99                 const field_type *_ptr = ptr;                                  \
 100                 BUILD_BUG_ON(((field_h) / 32) != ((field_l) / 32));            \
 101                 FIELD_GET(GENMASK((field_h) % 32, (field_l) % 32),             \
 102                           le32_to_cpu(*((__le32 *)_ptr + (field_h) / 32)));    \
 103         })
 104
 105 #define hr_reg_read(ptr, field) _hr_reg_read(ptr, field)
 106
 107 /*************ROCEE_REG DEFINITION****************/
 108 #define ROCEE_VENDOR_ID_REG                     0x0
 109 #define ROCEE_VENDOR_PART_ID_REG                0x4
 110
 111 #define ROCEE_SYS_IMAGE_GUID_L_REG              0xC
 112 #define ROCEE_SYS_IMAGE_GUID_H_REG              0x10
 113
 114 #define ROCEE_PORT_GID_L_0_REG                  0x50
 115 #define ROCEE_PORT_GID_ML_0_REG                 0x54
 116 #define ROCEE_PORT_GID_MH_0_REG                 0x58
 117 #define ROCEE_PORT_GID_H_0_REG                  0x5C
 118
 119 #define ROCEE_BT_CMD_H_REG                      0x204
 120
 121 #define ROCEE_SMAC_L_0_REG                      0x240
 122 #define ROCEE_SMAC_H_0_REG                      0x244
 123
 124 #define ROCEE_QP1C_CFG3_0_REG                   0x27C
 125
 126 #define ROCEE_CAEP_AEQE_CONS_IDX_REG            0x3AC
 127 #define ROCEE_CAEP_CEQC_CONS_IDX_0_REG          0x3BC
 128
 129 #define ROCEE_ECC_UCERR_ALM1_REG                0xB38
 130 #define ROCEE_ECC_UCERR_ALM2_REG                0xB3C
 131 #define ROCEE_ECC_CERR_ALM1_REG                 0xB44
 132 #define ROCEE_ECC_CERR_ALM2_REG                 0xB48
 133
 134 #define ROCEE_ACK_DELAY_REG                     0x14
 135 #define ROCEE_GLB_CFG_REG                       0x18
 136
 137 #define ROCEE_DMAE_USER_CFG1_REG                0x40
 138 #define ROCEE_DMAE_USER_CFG2_REG                0x44
 139
 140 #define ROCEE_DB_SQ_WL_REG                      0x154
 141 #define ROCEE_DB_OTHERS_WL_REG                  0x158
 142 #define ROCEE_RAQ_WL_REG                        0x15C
 143 #define ROCEE_WRMS_POL_TIME_INTERVAL_REG        0x160
 144 #define ROCEE_EXT_DB_SQ_REG                     0x164
 145 #define ROCEE_EXT_DB_SQ_H_REG                   0x168
 146 #define ROCEE_EXT_DB_OTH_REG                    0x16C
 147
 148 #define ROCEE_EXT_DB_OTH_H_REG                  0x170
 149 #define ROCEE_EXT_DB_SQ_WL_EMPTY_REG            0x174
 150 #define ROCEE_EXT_DB_SQ_WL_REG                  0x178
 151 #define ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG        0x17C
 152 #define ROCEE_EXT_DB_OTHERS_WL_REG              0x180
 153 #define ROCEE_EXT_RAQ_REG                       0x184
 154 #define ROCEE_EXT_RAQ_H_REG                     0x188
 155
 156 #define ROCEE_CAEP_CE_INTERVAL_CFG_REG          0x190
 157 #define ROCEE_CAEP_CE_BURST_NUM_CFG_REG         0x194
 158 #define ROCEE_BT_CMD_L_REG                      0x200
 159
 160 #define ROCEE_MB1_REG                           0x210
 161 #define ROCEE_MB6_REG                           0x224
 162 #define ROCEE_DB_SQ_L_0_REG                     0x230
 163 #define ROCEE_DB_OTHERS_L_0_REG                 0x238
 164 #define ROCEE_QP1C_CFG0_0_REG                   0x270
 165
 166 #define ROCEE_CAEP_AEQC_AEQE_SHIFT_REG          0x3A0
 167 #define ROCEE_CAEP_CEQC_SHIFT_0_REG             0x3B0
 168 #define ROCEE_CAEP_CE_IRQ_MASK_0_REG            0x3C0
 169 #define ROCEE_CAEP_CEQ_ALM_OVF_0_REG            0x3C4
 170 #define ROCEE_CAEP_AE_MASK_REG                  0x6C8
 171 #define ROCEE_CAEP_AE_ST_REG                    0x6CC
 172
 173 #define ROCEE_CAEP_CQE_WCMD_EMPTY               0x850
 174 #define ROCEE_SCAEP_WR_CQE_CNT                  0x8D0
 175 #define ROCEE_ECC_UCERR_ALM0_REG                0xB34
 176 #define ROCEE_ECC_CERR_ALM0_REG                 0xB40
 177
 178 /* V2 ROCEE REG */
 179 #define ROCEE_TX_CMQ_BASEADDR_L_REG             0x07000
 180 #define ROCEE_TX_CMQ_BASEADDR_H_REG             0x07004
 181 #define ROCEE_TX_CMQ_DEPTH_REG                  0x07008
 182 #define ROCEE_TX_CMQ_PI_REG                     0x07010
 183 #define ROCEE_TX_CMQ_CI_REG                     0x07014
 184
 185 #define ROCEE_RX_CMQ_BASEADDR_L_REG             0x07018
 186 #define ROCEE_RX_CMQ_BASEADDR_H_REG             0x0701c
 187 #define ROCEE_RX_CMQ_DEPTH_REG                  0x07020
 188 #define ROCEE_RX_CMQ_TAIL_REG                   0x07024
 189 #define ROCEE_RX_CMQ_HEAD_REG                   0x07028
 190
 191 #define ROCEE_VF_EQ_DB_CFG0_REG                 0x238
 192 #define ROCEE_VF_EQ_DB_CFG1_REG                 0x23C
 193
 194 #define ROCEE_VF_ABN_INT_CFG_REG                0x13000
 195 #define ROCEE_VF_ABN_INT_ST_REG                 0x13004
 196 #define ROCEE_VF_ABN_INT_EN_REG                 0x13008
 197 #define ROCEE_VF_EVENT_INT_EN_REG               0x1300c
 198
 199 #endif /* _HNS_ROCE_COMMON_H */