drivers/infiniband/hw/irdma/i40iw_hw.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
   2 /* Copyright (c) 2015 - 2021 Intel Corporation */
   3 #ifndef I40IW_HW_H
   4 #define I40IW_HW_H
   5 #define I40E_VFPE_CQPTAIL1            0x0000A000 /* Reset: VFR */
   6 #define I40E_VFPE_CQPDB1              0x0000BC00 /* Reset: VFR */
   7 #define I40E_VFPE_CCQPSTATUS1         0x0000B800 /* Reset: VFR */
   8 #define I40E_VFPE_CCQPHIGH1           0x00009800 /* Reset: VFR */
   9 #define I40E_VFPE_CCQPLOW1            0x0000AC00 /* Reset: VFR */
  10 #define I40E_VFPE_CQARM1              0x0000B400 /* Reset: VFR */
  11 #define I40E_VFPE_CQACK1              0x0000B000 /* Reset: VFR */
  12 #define I40E_VFPE_AEQALLOC1           0x0000A400 /* Reset: VFR */
  13 #define I40E_VFPE_CQPERRCODES1        0x00009C00 /* Reset: VFR */
  14 #define I40E_VFPE_WQEALLOC1           0x0000C000 /* Reset: VFR */
  15 #define I40E_VFINT_DYN_CTLN(_INTVF)   (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
  16
  17 #define I40E_PFPE_CQPTAIL             0x00008080 /* Reset: PFR */
  18
  19 #define I40E_PFPE_CQPDB               0x00008000 /* Reset: PFR */
  20 #define I40E_PFPE_CCQPSTATUS          0x00008100 /* Reset: PFR */
  21 #define I40E_PFPE_CCQPHIGH            0x00008200 /* Reset: PFR */
  22 #define I40E_PFPE_CCQPLOW             0x00008180 /* Reset: PFR */
  23 #define I40E_PFPE_CQARM               0x00131080 /* Reset: PFR */
  24 #define I40E_PFPE_CQACK               0x00131100 /* Reset: PFR */
  25 #define I40E_PFPE_AEQALLOC            0x00131180 /* Reset: PFR */
  26 #define I40E_PFPE_CQPERRCODES         0x00008880 /* Reset: PFR */
  27 #define I40E_PFPE_WQEALLOC            0x00138C00 /* Reset: PFR */
  28 #define I40E_GLPCI_LBARCTRL           0x000BE484 /* Reset: POR */
  29 #define I40E_GLPE_CPUSTATUS0          0x0000D040 /* Reset: PE_CORER */
  30 #define I40E_GLPE_CPUSTATUS1          0x0000D044 /* Reset: PE_CORER */
  31 #define I40E_GLPE_CPUSTATUS2          0x0000D048 /* Reset: PE_CORER */
  32 #define I40E_GLPE_CRITERR             0x000B4000 /* Reset: PE_CORER */
  33 #define I40E_PFHMC_PDINV              0x000C0300 /* Reset: PFR */
  34 #define I40E_GLHMC_VFPDINV(_i)        (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */
  35 #define I40E_PFINT_DYN_CTLN(_INTPF)   (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */    /* Reset: PFR */
  36 #define I40E_PFINT_AEQCTL             0x00038700 /* Reset: CORER */
  37
  38 #define I40E_GLPES_PFIP4RXDISCARD(_i)            (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  39 #define I40E_GLPES_PFIP4RXTRUNC(_i)              (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  40 #define I40E_GLPES_PFIP4TXNOROUTE(_i)            (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  41 #define I40E_GLPES_PFIP6RXDISCARD(_i)            (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  42 #define I40E_GLPES_PFIP6RXTRUNC(_i)              (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  43
  44 #define I40E_GLPES_PFRDMAVBNDLO(_i)              (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  45 #define I40E_GLPES_PFIP4TXMCOCTSLO(_i)           (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  46 #define I40E_GLPES_PFIP6RXMCOCTSLO(_i)           (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  47 #define I40E_GLPES_PFIP6TXMCOCTSLO(_i)           (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  48 #define I40E_GLPES_PFUDPRXPKTSLO(_i)             (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  49 #define I40E_GLPES_PFUDPTXPKTSLO(_i)             (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  50
  51 #define I40E_GLPES_PFIP6TXNOROUTE(_i)            (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  52 #define I40E_GLPES_PFTCPRTXSEG(_i)               (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  53 #define I40E_GLPES_PFTCPRXOPTERR(_i)             (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  54 #define I40E_GLPES_PFTCPRXPROTOERR(_i)           (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  55 #define I40E_GLPES_PFRXVLANERR(_i)               (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */
  56 #define I40E_GLPES_PFIP4RXOCTSLO(_i)             (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  57 #define I40E_GLPES_PFIP4RXPKTSLO(_i)             (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  58 #define I40E_GLPES_PFIP4RXFRAGSLO(_i)            (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  59 #define I40E_GLPES_PFIP4RXMCPKTSLO(_i)           (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  60 #define I40E_GLPES_PFIP4TXOCTSLO(_i)             (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  61 #define I40E_GLPES_PFIP4TXPKTSLO(_i)             (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  62 #define I40E_GLPES_PFIP4TXFRAGSLO(_i)            (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  63 #define I40E_GLPES_PFIP4TXMCPKTSLO(_i)           (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  64 #define I40E_GLPES_PFIP6RXOCTSLO(_i)             (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  65 #define I40E_GLPES_PFIP6RXPKTSLO(_i)             (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  66 #define I40E_GLPES_PFIP6RXFRAGSLO(_i)            (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  67 #define I40E_GLPES_PFIP6TXOCTSLO(_i)             (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  68 #define I40E_GLPES_PFIP6TXPKTSLO(_i)             (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  69 #define I40E_GLPES_PFIP6TXFRAGSLO(_i)            (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  70 #define I40E_GLPES_PFIP6TXMCPKTSLO(_i)           (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  71 #define I40E_GLPES_PFTCPTXSEGLO(_i)              (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  72 #define I40E_GLPES_PFRDMARXRDSLO(_i)             (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  73 #define I40E_GLPES_PFRDMARXSNDSLO(_i)            (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  74 #define I40E_GLPES_PFRDMARXWRSLO(_i)             (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  75 #define I40E_GLPES_PFRDMATXRDSLO(_i)             (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  76 #define I40E_GLPES_PFRDMATXSNDSLO(_i)            (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  77 #define I40E_GLPES_PFRDMATXWRSLO(_i)             (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  78 #define I40E_GLPES_PFIP4RXMCOCTSLO(_i)           (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  79 #define I40E_GLPES_PFIP6RXMCPKTSLO(_i)           (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  80 #define I40E_GLPES_PFTCPRXSEGSLO(_i)             (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  81 #define I40E_GLPES_PFRDMAVINVLO(_i)              (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */
  82
  83 #define I40IW_DB_ADDR_OFFSET    (4 * 1024 * 1024 - 64 * 1024)
  84
  85 #define I40IW_VF_DB_ADDR_OFFSET (64 * 1024)
  86
  87 #define I40E_PFINT_LNKLSTN(_INTPF)           (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
  88 #define I40E_PFINT_LNKLSTN_MAX_INDEX         511
  89 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX GENMASK(10, 0)
  90 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE GENMASK(12, 11)
  91
  92 #define I40E_PFINT_CEQCTL(_INTPF)          (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
  93 #define I40E_PFINT_CEQCTL_MAX_INDEX        511
  94
  95 /* shifts/masks for FLD_[LS/RS]_64 macros used in device table */
  96 #define I40E_PFINT_CEQCTL_MSIX_INDX_S 0
  97 #define I40E_PFINT_CEQCTL_MSIX_INDX GENMASK(7, 0)
  98 #define I40E_PFINT_CEQCTL_ITR_INDX_S 11
  99 #define I40E_PFINT_CEQCTL_ITR_INDX GENMASK(12, 11)
 100 #define I40E_PFINT_CEQCTL_MSIX0_INDX_S 13
 101 #define I40E_PFINT_CEQCTL_MSIX0_INDX GENMASK(15, 13)
 102 #define I40E_PFINT_CEQCTL_NEXTQ_INDX_S 16
 103 #define I40E_PFINT_CEQCTL_NEXTQ_INDX GENMASK(26, 16)
 104 #define I40E_PFINT_CEQCTL_NEXTQ_TYPE_S 27
 105 #define I40E_PFINT_CEQCTL_NEXTQ_TYPE GENMASK(28, 27)
 106 #define I40E_PFINT_CEQCTL_CAUSE_ENA_S 30
 107 #define I40E_PFINT_CEQCTL_CAUSE_ENA BIT(30)
 108 #define I40E_PFINT_CEQCTL_INTEVENT_S 31
 109 #define I40E_PFINT_CEQCTL_INTEVENT BIT(31)
 110 #define I40E_CQPSQ_STAG_PDID_S 48
 111 #define I40E_CQPSQ_STAG_PDID GENMASK_ULL(62, 48)
 112 #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_S 0
 113 #define I40E_PFPE_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
 114 #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_S 31
 115 #define I40E_PFPE_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
 116 #define I40E_PFINT_DYN_CTLN_ITR_INDX_S 3
 117 #define I40E_PFINT_DYN_CTLN_ITR_INDX GENMASK(4, 3)
 118 #define I40E_PFINT_DYN_CTLN_INTENA_S 0
 119 #define I40E_PFINT_DYN_CTLN_INTENA BIT(0)
 120 #define I40E_CQPSQ_CQ_CEQID_S 24
 121 #define I40E_CQPSQ_CQ_CEQID GENMASK(30, 24)
 122 #define I40E_CQPSQ_CQ_CQID_S 0
 123 #define I40E_CQPSQ_CQ_CQID GENMASK_ULL(15, 0)
 124 #define I40E_COMMIT_FPM_CQCNT_S 0
 125 #define I40E_COMMIT_FPM_CQCNT GENMASK_ULL(17, 0)
 126
 127 #define I40E_VSIQF_CTL(_VSI)             (0x0020D800 + ((_VSI) * 4))
 128
 129 enum i40iw_device_caps_const {
 130         I40IW_MAX_WQ_FRAGMENT_COUNT             = 3,
 131         I40IW_MAX_SGE_RD                        = 1,
 132         I40IW_MAX_PUSH_PAGE_COUNT               = 0,
 133         I40IW_MAX_INLINE_DATA_SIZE              = 48,
 134         I40IW_MAX_IRD_SIZE                      = 63,
 135         I40IW_MAX_ORD_SIZE                      = 127,
 136         I40IW_MAX_WQ_ENTRIES                    = 2048,
 137         I40IW_MAX_WQE_SIZE_RQ                   = 128,
 138         I40IW_MAX_PDS                           = 32768,
 139         I40IW_MAX_STATS_COUNT                   = 16,
 140         I40IW_MAX_CQ_SIZE                       = 1048575,
 141         I40IW_MAX_OUTBOUND_MSG_SIZE             = 2147483647,
 142         I40IW_MAX_INBOUND_MSG_SIZE              = 2147483647,
 143         I40IW_MIN_WQ_SIZE                       = 4 /* WQEs */,
 144 };
 145
 146 #define I40IW_QP_WQE_MIN_SIZE   32
 147 #define I40IW_QP_WQE_MAX_SIZE   128
 148 #define I40IW_MAX_RQ_WQE_SHIFT  2
 149 #define I40IW_MAX_QUANTA_PER_WR 2
 150
 151 #define I40IW_QP_SW_MAX_SQ_QUANTA 2048
 152 #define I40IW_QP_SW_MAX_RQ_QUANTA 16384
 153 #define I40IW_QP_SW_MAX_WQ_QUANTA 2048
 154 #define I40IW_MAX_QP_WRS ((I40IW_QP_SW_MAX_SQ_QUANTA - IRDMA_SQ_RSVD) / I40IW_MAX_QUANTA_PER_WR)
 155 #define I40IW_FIRST_VF_FPM_ID 16
 156 #define QUEUE_TYPE_CEQ        2
 157 #define NULL_QUEUE_INDEX      0x7FF
 158
 159 void i40iw_init_hw(struct irdma_sc_dev *dev);
 160 #endif /* I40IW_HW_H */