1 // SPDX-License-Identifier: GPL-2.0-only
3 * Apple DART page table allocator.
5 * Copyright (C) 2022 The Asahi Linux Contributors
7 * Based on io-pgtable-arm.
9 * Copyright (C) 2014 ARM Limited
11 * Author: Will Deacon <will.deacon@arm.com>
14 #define pr_fmt(fmt) "dart io-pgtable: " fmt
16 #include <linux/atomic.h>
17 #include <linux/bitfield.h>
18 #include <linux/bitops.h>
19 #include <linux/io-pgtable.h>
20 #include <linux/kernel.h>
21 #include <linux/sizes.h>
22 #include <linux/slab.h>
23 #include <linux/types.h>
25 #include <asm/barrier.h>
26 #include "iommu-pages.h"
28 #define DART1_MAX_ADDR_BITS 36
30 #define DART_MAX_TABLES 4
33 /* Struct accessors */
34 #define io_pgtable_to_data(x) \
35 container_of((x), struct dart_io_pgtable, iop)
37 #define io_pgtable_ops_to_data(x) \
38 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
40 #define DART_GRANULE(d) \
41 (sizeof(dart_iopte) << (d)->bits_per_level)
42 #define DART_PTES_PER_TABLE(d) \
43 (DART_GRANULE(d) >> ilog2(sizeof(dart_iopte)))
45 #define APPLE_DART_PTE_SUBPAGE_START GENMASK_ULL(63, 52)
46 #define APPLE_DART_PTE_SUBPAGE_END GENMASK_ULL(51, 40)
48 #define APPLE_DART1_PADDR_MASK GENMASK_ULL(35, 12)
49 #define APPLE_DART2_PADDR_MASK GENMASK_ULL(37, 10)
50 #define APPLE_DART2_PADDR_SHIFT (4)
52 /* Apple DART1 protection bits */
53 #define APPLE_DART1_PTE_PROT_NO_READ BIT(8)
54 #define APPLE_DART1_PTE_PROT_NO_WRITE BIT(7)
55 #define APPLE_DART1_PTE_PROT_SP_DIS BIT(1)
57 /* Apple DART2 protection bits */
58 #define APPLE_DART2_PTE_PROT_NO_READ BIT(3)
59 #define APPLE_DART2_PTE_PROT_NO_WRITE BIT(2)
60 #define APPLE_DART2_PTE_PROT_NO_CACHE BIT(1)
62 /* marks PTE as valid */
63 #define APPLE_DART_PTE_VALID BIT(0)
66 #define iopte_deref(pte, d) __va(iopte_to_paddr(pte, d))
68 struct dart_io_pgtable
{
69 struct io_pgtable iop
;
74 void *pgd
[DART_MAX_TABLES
];
77 typedef u64 dart_iopte
;
80 static dart_iopte
paddr_to_iopte(phys_addr_t paddr
,
81 struct dart_io_pgtable
*data
)
85 if (data
->iop
.fmt
== APPLE_DART
)
86 return paddr
& APPLE_DART1_PADDR_MASK
;
88 /* format is APPLE_DART2 */
89 pte
= paddr
>> APPLE_DART2_PADDR_SHIFT
;
90 pte
&= APPLE_DART2_PADDR_MASK
;
95 static phys_addr_t
iopte_to_paddr(dart_iopte pte
,
96 struct dart_io_pgtable
*data
)
100 if (data
->iop
.fmt
== APPLE_DART
)
101 return pte
& APPLE_DART1_PADDR_MASK
;
103 /* format is APPLE_DART2 */
104 paddr
= pte
& APPLE_DART2_PADDR_MASK
;
105 paddr
<<= APPLE_DART2_PADDR_SHIFT
;
110 static void *__dart_alloc_pages(size_t size
, gfp_t gfp
)
112 int order
= get_order(size
);
114 VM_BUG_ON((gfp
& __GFP_HIGHMEM
));
115 return iommu_alloc_pages(gfp
, order
);
118 static int dart_init_pte(struct dart_io_pgtable
*data
,
119 unsigned long iova
, phys_addr_t paddr
,
120 dart_iopte prot
, int num_entries
,
124 dart_iopte pte
= prot
;
125 size_t sz
= data
->iop
.cfg
.pgsize_bitmap
;
127 for (i
= 0; i
< num_entries
; i
++)
128 if (ptep
[i
] & APPLE_DART_PTE_VALID
) {
129 /* We require an unmap first */
130 WARN_ON(ptep
[i
] & APPLE_DART_PTE_VALID
);
134 /* subpage protection: always allow access to the entire page */
135 pte
|= FIELD_PREP(APPLE_DART_PTE_SUBPAGE_START
, 0);
136 pte
|= FIELD_PREP(APPLE_DART_PTE_SUBPAGE_END
, 0xfff);
138 pte
|= APPLE_DART1_PTE_PROT_SP_DIS
;
139 pte
|= APPLE_DART_PTE_VALID
;
141 for (i
= 0; i
< num_entries
; i
++)
142 ptep
[i
] = pte
| paddr_to_iopte(paddr
+ i
* sz
, data
);
147 static dart_iopte
dart_install_table(dart_iopte
*table
,
150 struct dart_io_pgtable
*data
)
154 new = paddr_to_iopte(__pa(table
), data
) | APPLE_DART_PTE_VALID
;
157 * Ensure the table itself is visible before its PTE can be.
158 * Whilst we could get away with cmpxchg64_release below, this
159 * doesn't have any ordering semantics when !CONFIG_SMP.
163 old
= cmpxchg64_relaxed(ptep
, curr
, new);
168 static int dart_get_table(struct dart_io_pgtable
*data
, unsigned long iova
)
170 return (iova
>> (3 * data
->bits_per_level
+ ilog2(sizeof(dart_iopte
)))) &
171 ((1 << data
->tbl_bits
) - 1);
174 static int dart_get_l1_index(struct dart_io_pgtable
*data
, unsigned long iova
)
177 return (iova
>> (2 * data
->bits_per_level
+ ilog2(sizeof(dart_iopte
)))) &
178 ((1 << data
->bits_per_level
) - 1);
181 static int dart_get_l2_index(struct dart_io_pgtable
*data
, unsigned long iova
)
184 return (iova
>> (data
->bits_per_level
+ ilog2(sizeof(dart_iopte
)))) &
185 ((1 << data
->bits_per_level
) - 1);
188 static dart_iopte
*dart_get_l2(struct dart_io_pgtable
*data
, unsigned long iova
)
190 dart_iopte pte
, *ptep
;
191 int tbl
= dart_get_table(data
, iova
);
193 ptep
= data
->pgd
[tbl
];
197 ptep
+= dart_get_l1_index(data
, iova
);
198 pte
= READ_ONCE(*ptep
);
204 /* Deref to get level 2 table */
205 return iopte_deref(pte
, data
);
208 static dart_iopte
dart_prot_to_pte(struct dart_io_pgtable
*data
,
213 if (data
->iop
.fmt
== APPLE_DART
) {
214 if (!(prot
& IOMMU_WRITE
))
215 pte
|= APPLE_DART1_PTE_PROT_NO_WRITE
;
216 if (!(prot
& IOMMU_READ
))
217 pte
|= APPLE_DART1_PTE_PROT_NO_READ
;
219 if (data
->iop
.fmt
== APPLE_DART2
) {
220 if (!(prot
& IOMMU_WRITE
))
221 pte
|= APPLE_DART2_PTE_PROT_NO_WRITE
;
222 if (!(prot
& IOMMU_READ
))
223 pte
|= APPLE_DART2_PTE_PROT_NO_READ
;
224 if (!(prot
& IOMMU_CACHE
))
225 pte
|= APPLE_DART2_PTE_PROT_NO_CACHE
;
231 static int dart_map_pages(struct io_pgtable_ops
*ops
, unsigned long iova
,
232 phys_addr_t paddr
, size_t pgsize
, size_t pgcount
,
233 int iommu_prot
, gfp_t gfp
, size_t *mapped
)
235 struct dart_io_pgtable
*data
= io_pgtable_ops_to_data(ops
);
236 struct io_pgtable_cfg
*cfg
= &data
->iop
.cfg
;
237 size_t tblsz
= DART_GRANULE(data
);
238 int ret
= 0, tbl
, num_entries
, max_entries
, map_idx_start
;
239 dart_iopte pte
, *cptep
, *ptep
;
242 if (WARN_ON(pgsize
!= cfg
->pgsize_bitmap
))
245 if (WARN_ON(paddr
>> cfg
->oas
))
248 if (!(iommu_prot
& (IOMMU_READ
| IOMMU_WRITE
)))
251 tbl
= dart_get_table(data
, iova
);
253 ptep
= data
->pgd
[tbl
];
254 ptep
+= dart_get_l1_index(data
, iova
);
255 pte
= READ_ONCE(*ptep
);
257 /* no L2 table present */
259 cptep
= __dart_alloc_pages(tblsz
, gfp
);
263 pte
= dart_install_table(cptep
, ptep
, 0, data
);
265 iommu_free_pages(cptep
, get_order(tblsz
));
267 /* L2 table is present (now) */
268 pte
= READ_ONCE(*ptep
);
271 ptep
= iopte_deref(pte
, data
);
273 /* install a leaf entries into L2 table */
274 prot
= dart_prot_to_pte(data
, iommu_prot
);
275 map_idx_start
= dart_get_l2_index(data
, iova
);
276 max_entries
= DART_PTES_PER_TABLE(data
) - map_idx_start
;
277 num_entries
= min_t(int, pgcount
, max_entries
);
278 ptep
+= map_idx_start
;
279 ret
= dart_init_pte(data
, iova
, paddr
, prot
, num_entries
, ptep
);
281 *mapped
+= num_entries
* pgsize
;
284 * Synchronise all PTE updates for the new mapping before there's
285 * a chance for anything to kick off a table walk for the new iova.
292 static size_t dart_unmap_pages(struct io_pgtable_ops
*ops
, unsigned long iova
,
293 size_t pgsize
, size_t pgcount
,
294 struct iommu_iotlb_gather
*gather
)
296 struct dart_io_pgtable
*data
= io_pgtable_ops_to_data(ops
);
297 struct io_pgtable_cfg
*cfg
= &data
->iop
.cfg
;
298 int i
= 0, num_entries
, max_entries
, unmap_idx_start
;
299 dart_iopte pte
, *ptep
;
301 if (WARN_ON(pgsize
!= cfg
->pgsize_bitmap
|| !pgcount
))
304 ptep
= dart_get_l2(data
, iova
);
306 /* Valid L2 IOPTE pointer? */
310 unmap_idx_start
= dart_get_l2_index(data
, iova
);
311 ptep
+= unmap_idx_start
;
313 max_entries
= DART_PTES_PER_TABLE(data
) - unmap_idx_start
;
314 num_entries
= min_t(int, pgcount
, max_entries
);
316 while (i
< num_entries
) {
317 pte
= READ_ONCE(*ptep
);
324 if (!iommu_iotlb_gather_queued(gather
))
325 io_pgtable_tlb_add_page(&data
->iop
, gather
,
326 iova
+ i
* pgsize
, pgsize
);
335 static phys_addr_t
dart_iova_to_phys(struct io_pgtable_ops
*ops
,
338 struct dart_io_pgtable
*data
= io_pgtable_ops_to_data(ops
);
339 dart_iopte pte
, *ptep
;
341 ptep
= dart_get_l2(data
, iova
);
343 /* Valid L2 IOPTE pointer? */
347 ptep
+= dart_get_l2_index(data
, iova
);
349 pte
= READ_ONCE(*ptep
);
350 /* Found translation */
352 iova
&= (data
->iop
.cfg
.pgsize_bitmap
- 1);
353 return iopte_to_paddr(pte
, data
) | iova
;
356 /* Ran out of page tables to walk */
360 static struct dart_io_pgtable
*
361 dart_alloc_pgtable(struct io_pgtable_cfg
*cfg
)
363 struct dart_io_pgtable
*data
;
364 int tbl_bits
, bits_per_level
, va_bits
, pg_shift
;
366 pg_shift
= __ffs(cfg
->pgsize_bitmap
);
367 bits_per_level
= pg_shift
- ilog2(sizeof(dart_iopte
));
369 va_bits
= cfg
->ias
- pg_shift
;
371 tbl_bits
= max_t(int, 0, va_bits
- (bits_per_level
* DART_LEVELS
));
372 if ((1 << tbl_bits
) > DART_MAX_TABLES
)
375 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
379 data
->tbl_bits
= tbl_bits
;
380 data
->bits_per_level
= bits_per_level
;
382 data
->iop
.ops
= (struct io_pgtable_ops
) {
383 .map_pages
= dart_map_pages
,
384 .unmap_pages
= dart_unmap_pages
,
385 .iova_to_phys
= dart_iova_to_phys
,
391 static struct io_pgtable
*
392 apple_dart_alloc_pgtable(struct io_pgtable_cfg
*cfg
, void *cookie
)
394 struct dart_io_pgtable
*data
;
397 if (!cfg
->coherent_walk
)
400 if (cfg
->oas
!= 36 && cfg
->oas
!= 42)
403 if (cfg
->ias
> cfg
->oas
)
406 if (!(cfg
->pgsize_bitmap
== SZ_4K
|| cfg
->pgsize_bitmap
== SZ_16K
))
409 data
= dart_alloc_pgtable(cfg
);
413 cfg
->apple_dart_cfg
.n_ttbrs
= 1 << data
->tbl_bits
;
415 for (i
= 0; i
< cfg
->apple_dart_cfg
.n_ttbrs
; ++i
) {
416 data
->pgd
[i
] = __dart_alloc_pages(DART_GRANULE(data
), GFP_KERNEL
);
419 cfg
->apple_dart_cfg
.ttbr
[i
] = virt_to_phys(data
->pgd
[i
]);
426 iommu_free_pages(data
->pgd
[i
],
427 get_order(DART_GRANULE(data
)));
433 static void apple_dart_free_pgtable(struct io_pgtable
*iop
)
435 struct dart_io_pgtable
*data
= io_pgtable_to_data(iop
);
436 int order
= get_order(DART_GRANULE(data
));
437 dart_iopte
*ptep
, *end
;
440 for (i
= 0; i
< (1 << data
->tbl_bits
) && data
->pgd
[i
]; ++i
) {
442 end
= (void *)ptep
+ DART_GRANULE(data
);
444 while (ptep
!= end
) {
445 dart_iopte pte
= *ptep
++;
448 iommu_free_pages(iopte_deref(pte
, data
), order
);
450 iommu_free_pages(data
->pgd
[i
], order
);
456 struct io_pgtable_init_fns io_pgtable_apple_dart_init_fns
= {
457 .alloc
= apple_dart_alloc_pgtable
,
458 .free
= apple_dart_free_pgtable
,